WO2023098211A1

WO2023098211A1 - Display panel, detection method and electronic device

Info

Publication number: WO2023098211A1
Application number: PCT/CN2022/117633
Authority: WO
Inventors: 陈鹏名; 梁吉德
Original assignee: 荣耀终端有限公司
Priority date: 2021-11-30
Filing date: 2022-09-07
Publication date: 2023-06-08
Also published as: CN115019703A; CN115019703B

Abstract

The present application relates to the technical field of display. Provided are a display panel, a detection method and an electronic device, which can automatically detect a data line, thereby improving the detection precision and the detection efficiency. The display panel comprises: N data lines, N detection modules, a detection signal line, and a control module, wherein a first end of an ith data line acquires a first data signal; first ends of data lines, other than the ith data line, acquire second data signals; in a detection stage, an ith detection module transmits a signal of a second end of the ith data line to a second end of the ith detection module; in the detection stage, detection modules, other than the ith detection module, prevent the second data signals from passing through; in the detection stage, the detection signal line transmits a first detection signal of the second end of the ith detection module to the control module, such that the control module determines, according to the first detection signal and the first data signal, whether there is a defect in the ith data line; and 1 ≤ i ≤ N, and i and N are both positive integers.

Description

Display panel, detection method and electronic device

This application claims priority to a Chinese patent application filed with the State Intellectual Property Office of China on November 30, 2021, with application number 202111442729.0 and titled "Display Panel, Detection Method, and Electronic Device", the entire contents of which are incorporated by reference in In this application.

technical field

The present application relates to the field of display technology, in particular to a display panel, a detection method and electronic equipment.

Background technique

An important part of an electronic device to realize a display function is a display panel. Currently, two mainstream display panels in the display field include a liquid crystal display (Liquid Crystal Display, LCD) panel and an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel. LCD panels and OLED display panels are widely used in electronic equipment such as TVs, computers, mobile phones, wearable devices, and vehicles due to their high resolution, transparent display, and flexible display.

However, due to the process or other reasons, the data lines used to drive the pixel circuits in the LCD panel and OLED display panel are prone to disconnection, resulting in black lines (LCD panel) or white lines (OLED display panel), which seriously affect the display panel. display effect.

In order to detect the data lines, the position of the defective data lines is currently found by means of software manual positioning or microscope positioning. The position of the defective data line is found by software manual positioning or microscope positioning, and the detection accuracy is poor, and the cycle is long and the efficiency is low.

Contents of the invention

In order to solve the above technical problems, the present application provides a display panel, a detection method and an electronic device. The data line can be automatically detected to improve detection accuracy and detection efficiency.

In the first aspect, the embodiment of the present application provides a display panel, which includes: N data lines, N detection modules, detection signal lines, and a control module; both the data lines and the detection modules include a first end and a second end ; N data lines extend along the first direction and are arranged along the second direction, and the second ends of the N data lines are coupled with the first ends of the N detection modules one by one; the second ends of the N detection modules are all connected to Detection signal line coupling; wherein, the first direction crosses the second direction; the first end of the i-th data line is used to obtain the first data signal; the first end of other data lines except the i-th data line is used To obtain the second data signal; the i-th detection module is used to transmit the signal of the second end of the i-th data line to the second end of the i-th detection module during the detection phase; other detection modules except the i-th detection module are used In the detection phase, the second data signal is prevented from passing through; the detection signal line is used to transmit the first detection signal of the second end of the i-th detection module to the control module during the detection phase, so that the control module can use the first detection signal according to the first detection signal and the first detection signal. A data signal determines whether there is a defect in the i-th data line; wherein, 1≤i≤N, i and N are both positive integers.

The automatic detection of each data line is completed through the detection module, and the detection efficiency and detection accuracy are high. In addition, the second ends of all the detection modules are coupled with the same detection signal line, so that the number of detection signal lines can be reduced, and there is no need to provide a detection signal line for each detection module. When the number of detection signal lines is reduced, the area occupied by the detection signal lines in the non-display area can be reduced, which is conducive to narrowing the frame of the display panel. In addition, the method for automatically detecting the data lines provided by the embodiment of the present application can complete the automatic detection of the data lines before the electronic equipment leaves the factory, or can complete the automatic detection of the data lines when the electronic equipment has problems after use. Easy to detect.

Wherein, the first detection signal is the detection signal of the second terminal of the i-th detection module in the detection phase, that is, the detection signal transmitted on the detection signal line in the detection phase.

Exemplarily, the first direction and the second direction are perpendicular to each other.

In some possible implementations, the display panel further includes: at least one reset module; the reset module includes a first terminal and a second terminal; the first terminal of the reset module is coupled to the second terminal of the detection module; the reset module is used for resetting In the stage, the reset signal received by the second terminal of the reset module is transmitted to the second terminal of each detection module, so as to reset the second terminal of the detection module. The reset module resets the second end of each detection module to prevent the influence of other signals on the detection, and prevent the influence of the first data signal remaining at the second end of each detection module on the detection when detecting one of the data lines. detection accuracy.

In some possible implementation manners, on the basis that the display panel further includes at least one reset module, the detection signal line is also used to send the second detection signal at the second end of the detection module to the control module during the reset phase, so that the control The module determines whether the reset of the second terminal of the detection module is completed according to the second detection signal and the reset signal, so as to determine whether the signal of the second terminal of the detection module is a reset signal, so as to avoid that the signal of the second terminal of the detection module is not reset even though the reset is performed The signal affects the detection, so that the detection accuracy can be further improved.

Wherein, the second detection signal is the detection signal of the second terminal of the detection module during the reset phase, that is, the detection signal transmitted on the detection signal line during the reset phase.

In some possible implementation manners, on the basis that the display panel further includes at least one reset module, the reset module includes a first transistor, and the first transistor includes a gate, a first electrode, and a second electrode; the first transistor of the first transistor The pole is coupled with the second end of the detection module, the second pole of the first transistor is used to receive the reset signal, and the gate of the first transistor is used to obtain the first switch signal; the first switch signal is used to control the first transistor in the reset phase is turned on, and the first transistor is controlled to be turned off in the detection phase, which will not affect the detection in the detection phase. The reset module includes but is not limited to transistors, as long as the structure that can reset the second terminal of the detection module is within the protection scope of the present application. When the reset module is the first transistor, it can be arranged on the same layer as the transistor in the pixel driving circuit in the display panel. When preparing the transistor in the pixel driving circuit, the first transistor is prepared at the same time, which simplifies the process steps.

In some possible implementation manners, the detection module includes a second transistor and a diode; the second transistor includes a gate, a first electrode, and a second electrode; the first electrode of the second transistor is coupled to the second end of the data line, and the second The second pole of the two transistors is coupled with the anode of the diode, and the gate of the second transistor is used to obtain the second switch signal; the cathodes of each diode are coupled with the detection signal line; the second switch signal is used to control the second transistor in the reset phase turn off, and control the second transistor to turn on during the detection phase. Through the second transistor and the diode, the first data signal can be passed through, and the second data signal can be prevented from passing through, so as to complete the detection of the data line.

In some possible implementation manners, the above detection module includes a second transistor and a third transistor; both the second transistor and the third transistor include a gate, a first pole and a second pole; the first pole of the second transistor and the data line The second end of the second transistor is coupled, the second pole of the second transistor is coupled to the first pole of the third transistor, and the gate of the second transistor is used to obtain the second switch signal; the gate of the third transistor is connected to the first pole of the third transistor The second terminal of each third transistor is coupled to the detection signal line; the second switch signal is used to control the second transistor to turn off in the reset phase, and to control the second transistor to turn on in the detection phase. Through the second transistor and the third transistor, the first data signal can be passed through, and the second data signal can be prevented from passing through, so as to complete the detection of the data line. When the detection module includes the second transistor and the third transistor, it can be arranged on the same layer as the transistor in the pixel driving circuit in the display panel, and the second transistor and the third transistor are prepared at the same time when preparing the transistor in the pixel driving circuit, which simplifies the process step.

In some possible implementation manners, on the basis that the detection module includes a second transistor and a diode, or the detection module includes a second transistor and a third transistor, the display panel further includes an inverter and at least one reset module; the reset module includes The first transistor, the first transistor includes a gate, a first pole and a second pole; the first pole of the first transistor is coupled to the second terminal of the detection module, and the second pole of the first transistor is used to receive a reset signal; reverse phase The input terminal of the inverter is coupled to the gate of the second transistor, and the output terminal of the inverter is coupled to the gate of the first transistor. In this way, there is no need to separately set switch signal lines for the first transistor and the second transistor, for example, only one switch signal line that can transmit the second switch signal needs to be set, or only one switch that can transmit the first switch signal needs to be set signal line. The advantage of such setting is that the structure is simple, and it is beneficial to narrow the frame of the display panel.

In some possible implementation manners, on the basis that the display panel further includes at least one reset module, the number of the reset module is one, and the second terminals of the N detection modules are all coupled to the first terminals of the reset module. The reset of the second ends of the N detection modules can be completed in the reset stage through a reset module, the number of reset modules is reduced, the structure is simple, and correspondingly, the area occupied by the reset module is reduced, which is beneficial to the display panel. Narrow borders.

In some possible implementation manners, on the basis that the display panel further includes at least one reset module, the number of reset modules is N, and the first ends of the N reset modules correspond to the second ends of the N detection modules one by one. Coupling, the second terminals of the N reset modules are coupled, and the second terminals of all the reset modules are coupled to receive the reset signal at the same time. In this way, the synchronization of receiving the reset signal by each reset module is guaranteed, and there is no need to provide a line for each reset module to provide a reset signal, which reduces wiring and is conducive to narrowing the frame of the display panel.

In some possible implementation manners, on the basis that the display panel further includes at least one reset module, the reset signal is a ground potential. The ground potential can be obtained, for example, from a structure in the display panel, such as an electrostatic shielding structure. In this way, there is no need to separately arrange a line for providing a reset signal, which simplifies the process steps.

In a second aspect, an embodiment of the present application provides an electronic device, where the electronic device includes any one of the above display panels. All the effects of the above display panel can be realized.

In the third aspect, the embodiment of the present application provides a detection method, which is applied to any one of the above-mentioned display panels, and can realize all the effects of the above-mentioned display panels;

The detection method includes: in the detection phase, receiving the first detection signal fed back by the detection signal line; in the detection phase, judging whether the first detection signal is equal to the first data signal obtained by the first end of the i-th data line; if so, Then it is determined that there is no defect in the i-th data line; if not, then it is determined that there is a defect in the i-th data line; the above steps are repeated until the detection of all the N data lines is completed.

In some possible implementation manners, the display panel further includes at least one reset module, the reset module includes a first transistor; the detection module includes a second transistor and a third transistor; the first transistor, the second transistor, and the third transistor each include a gate , the first pole and the second pole; the first pole of the first transistor is coupled to the second end of the third transistor, and the second pole of the first transistor is used to receive the reset signal; the first pole of the second transistor is connected to the data line The second end is coupled, the second pole of the second transistor is coupled with the first pole of the third transistor; the gate of the third transistor is coupled with the first pole of the third transistor; the second end of each third transistor is connected with the detection signal line coupling;

Before receiving the first detection signal fed back by the detection signal line, it also includes: in the reset phase, sending the first switch signal to the gate of the first transistor to write the reset signal into the second pole of the third transistor; in the detection phase, A second switch signal is sent to the gate of the second transistor to transmit the signal at the second end of the i-th data line to the detection signal line.

In some possible implementation manners, the display panel further includes at least one reset module, the reset module includes a first transistor; the detection module includes a second transistor and a diode; the first transistor and the second transistor both include Gate, first pole and second pole; the first pole of the first transistor is coupled to the cathode of the diode, and the second pole of the first transistor is used to receive the reset signal; the second transistor The first pole of the second transistor is coupled to the second end of the data line, the second pole of the second transistor is coupled to the anode of the diode; the cathode of the diode is coupled to the first pole of the third transistor; each The cathodes of the diodes are all coupled to the detection signal line;

Before receiving the first detection signal fed back by the detection signal line, it also includes: in the reset phase, sending the first switch signal to the gate of the first transistor to write the reset signal into the cathode of the diode; The gate of the i-th data line sends a second switch signal to transmit the signal at the second end of the i-th data line to the detection signal line.

In some possible implementations, the detection method further includes: in the reset phase, receiving the second detection signal fed back from the detection signal line; in the reset phase, judging whether the second detection signal is equal to the reset signal; If not, then send the first switch signal to the gate of the first transistor to write the reset signal into the second pole of the third transistor; or, if not, send the first switch signal to the gate of the first transistor The gate sends a first switching signal to write a reset signal to the cathode of the diode.

Description of drawings

FIG. 1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of another electronic device provided in the embodiment of the present application;

FIG. 3 is a schematic structural diagram of another electronic device provided in the embodiment of the present application;

FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of another display panel provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram of another display panel provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another display panel provided by the embodiment of the present application;

FIG. 8 is a schematic structural diagram of another display panel provided by the embodiment of the present application;

FIG. 9 is a timing diagram of a detection module and a reset module provided by an embodiment of the present application;

FIG. 10 is a schematic structural diagram of another display panel provided by the embodiment of the present application;

FIG. 11 is a flow chart of a detection method provided by an embodiment of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

The term "and/or" in this article is just an association relationship describing associated objects, which means that there can be three relationships, for example, A and/or B can mean: A exists alone, A and B exist simultaneously, and there exists alone B these three situations.

The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of objects. For example, the first target object, the second target object, etc. are used to distinguish different target objects, rather than describing a specific order of the target objects.

In the embodiments of the present application, words such as "exemplary" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner.

In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

The embodiment of the present application provides an electronic device. The electronic device provided in the embodiment of the present application may be a TV, a computer, a tablet computer, a personal digital assistant (PDA for short), a vehicle-mounted computer, a mobile phone, a smart wearable device, a smart Household equipment and other electronic equipment including display panels, the embodiment of the present application does not specifically limit the specific form of the above electronic equipment.

The specific structure and application of the electronic device provided by the embodiments of the present application will be described below.

As shown in FIG. 1 , FIG. 1 shows a schematic structural diagram of an electronic device provided by an embodiment of the present application. The electronic device 100 includes structures such as a control system 10 , a display panel 20 , and a main board 30 . The control system 10 is, for example, disposed on the main board 30 . The display panel 20 and the main board 30 may be coupled through a flexible circuit board, for example.

The control system 10 includes, for example, a System on Chip (SoC). For example, a central processing unit (Central Processing Unit, CPU), an image processor (Graphic Processing Unit, GPU) and a modem (Modem) are integrated inside the SoC. It should be noted that the CPU, GPU, Modem, etc. may be integrated on the SoC, or may be separately configured, which is not limited in this embodiment of the present application.

The display panel 20 may be, for example, an LCD panel, an OLED display panel, an LED display panel, etc., where the LED display panel includes, for example, a Micro-LED display panel, a Mini-LED display panel, and the like. The embodiment of the present application does not limit the type of the display panel 20 .

Continuing to refer to FIG. 1 , the display panel 20 includes, for example, a display area AA and a non-display area NAA. In the display area AA, the data lines 21 and the scan lines 22 are intersected to define a plurality of sub-pixel areas, and sub-pixels 23 are arranged in the sub-pixel areas, and the sub-pixels 23 include, for example, a pixel driving circuit (not shown in the figure). A plurality of sub-pixels 23 are arranged in an array, for example. The non-display area NAA is provided with a driver chip 24 , and the driver chip 24 includes a plurality of data output pins 241 . Multiple data output pins 241 are coupled to multiple data lines 21 in one-to-one correspondence. The control system 10 sends a control signal to the driver chip 24, and the internal circuit of the driver chip 24 processes the control signal to generate a data signal, and the data signal is transmitted to the data line 21 through the data output pin 241, so as to transmit the data signal to the sub-pixel 23 through the data line 21. Write data signal.

Alternatively, referring to FIG. 2 , a multi-way selection circuit 25 is further provided in the non-display area NAA, and the multi-way selection circuit 25 includes a plurality of multi-way selection units 251 . An input terminal of a multiplexing unit 251 is coupled to a data output pin 241 , and an output terminal of the multiplexing unit 251 may be coupled to at least two data lines 21 , for example. The control system 10 sends the control signal to the driver chip 24, and the internal circuit of the driver chip 24 processes the control signal to generate a data drive signal, and the data drive signal is transmitted to the multiplexing unit 251 through the data output pin 241 to pass through the multiplexing unit. 251 writes data signals to the sub-pixels 23 . The configuration of the multiplexing circuit 25 can reduce the number of data output pins 241 .

It should be noted that, the following examples are all described by taking the non-display area NAA not provided with the multiplexing circuit 25 as an example.

It should also be noted that the driver chip 24 may or may not be disposed on the display panel 20, for example, it may be disposed on a flexible circuit board between the display panel 20 and the main board 30. This is not limited. When the driving chip 24 is disposed on the flexible circuit board, it is beneficial to narrow the frame of the display panel. In the embodiments of the present application, the driver chip 24 is disposed on the display panel 20 as an example for description.

Continue referring to Fig. 1 or Fig. 2, in the non-display area NAA, also be provided with shift register 26, shift register 26 comprises a plurality of cascaded shift register units, the scan signal output end 261 of each stage shift register unit and The scanning lines 22 corresponding to one row of sub-pixels 23 are coupled. The internal circuit of the driving chip 24 also generates a scanning driving signal after processing the control signal. The scan driving signal is transmitted to the shift register 26 to generate a scan signal, which is transmitted to the scan line 22 through the scan signal output terminal 261 of the shift register unit. Wherein, the number of shift registers 26 may be one. As shown in FIG. 1 or FIG. 2 , a group of cascaded shift registers 26 is arranged on one side of the display area AA. Optionally, referring to FIG. 3 , the number of shift registers 26 can also be two, and two groups of cascaded shift registers 26 are respectively located in the non-display area NAA oppositely arranged on both sides of the display area AA, and located on the two sides of the non-display area NAA. The scan signal output terminal 261 of the group shift register 26 is coupled through a scan line 22 , and the shift register 26 coupled with the same scan line 22 synchronously outputs a scan signal to the scan line 22 through the scan signal output terminal 261 . In this way, it is possible to prevent the voltage drop on the scan line 22 from affecting the display effect of the display panel.

It should be noted here that the following examples all take a set of shift registers 26 set in the non-display area NAA as an example for illustration.

In order to solve the problems in the background technology, the display panel provided by the embodiment of the present application also includes a detection module, a detection signal line and a reset module. Automatic detection of each data line, and accurate positioning of defective data lines, improving detection accuracy and detection efficiency.

The display panel and the detection module and reset module in the display panel will be specifically described below in combination with electronic devices.

As shown in FIG. 4 , the display panel 20 further includes a plurality of detection modules 27 and a plurality of reset modules 28 located in the non-display area NAA. Exemplarily, the number of data lines 21 is N, and the number of detection modules 27 and reset modules 28 is also N, wherein N is a positive integer greater than or equal to 1. N data lines 21 include the first data line 21 (1), the second data line 21 (2), ..., the N-1th data line 21 (N-1), the Nth data line 21 (N ). The N detection modules 27 include a first detection module 27(1), a second detection module 27(2), ..., an N-1th detection module 27(N-1), and an Nth detection module 27(N). The N reset modules 28 include a first reset module 28(1), a second reset module 28(2), . . . , an N−1th reset module 28(N−1), and an Nth reset module 28(N). The first end of the first detection module 27 (1) is coupled to the second end of the first data line 21 (1), and the second end of the first detection module 27 (1) is coupled to the second end of the first reset module 28 (1). The first end is coupled, and the second end of the first reset module 28 ( 1 ) is used for receiving the reset signal Vref. The first end of the second detection module 27 (2) is coupled to the second end of the second data line 21 (2), and the second end of the second detection module 27 (2) is coupled to the second end of the second reset module 28 (2). The first end is coupled, and the second end of the second reset module 28 ( 2 ) is used for receiving the reset signal Vref. .... The first end of the N-1 detection module 27 (N-1) is coupled to the second end of the N-1 data line 21 (N-1), and the N-1 detection module 27 (N-1) The two ends are coupled to the first end of the N-1th reset module 28 (N-1), and the second end of the N-1th reset module 28 (N-1) is used to receive the reset signal Vref. The first end of the Nth detection module 27 (N) is coupled to the second end of the Nth data line 21 (N), and the second end of the Nth detection module 27 (N) is connected to the Nth reset module 28 (N). The first end is coupled, and the second end of the Nth reset module 28 (N) is used for receiving the reset signal Vref. In addition, the display panel 20 further includes a detection signal line 29 , and the second ends of each detection module 27 are coupled to the detection signal line 29 .

Taking N as 6 as an example, the working principles of the detection module 27 and the reset module 28 will be described in detail below. In the following embodiments, N is 6 as an example for description, and the following embodiments will not be repeated.

Continuing to refer to FIG. 4 , first, in the reset phase, the second terminal of each reset module 28 receives the reset signal Vref, and transmits the received reset signal Vref to the first terminal of the reset module 28 . Since the first end of the reset module 28 is coupled with the second end of the detection module 27, the reset signal Vref can reset the second end of the detection module 27, preventing the second end of the detection module 27 from having other signals and avoiding other signals. affect detection. In addition, since the detection signal line 29 is coupled to the second end of each detection module 27, the detection signal line 29 can feed back the signal of the second end of the detection module 27 to the control module. The control module compares the detection signal Ts fed back by the detection signal line 29 with the reset signal Vref, and if the detection signal Ts is equal to the reset signal Vref, it indicates that the reset is completed.

After the reset is completed, in the detection stage, the first end of the first data line 21(1) receives the first data signal S1, and transmits the received first data signal S1 to the first detection module 27(1). The second data line 21(2), the third data line 21(3), the fourth data line 21(4), the fifth data line 21(5), the sixth data line 21(6) The first end respectively receives the second data signal S2, and transmits the received second data signal S2 to the detection module 27 coupled thereto, that is, the second data line 21(2) transmits the received second data signal S2 to The second detection module 27(2), the third data line 21(3) transmits the received second data signal S2 to the third detection module 27(3), and the fourth data line 21(4) transmits the received second data signal S2 The second data signal S2 is transmitted to the fourth detection module 27 (4), the fifth data line 21 (5) transmits the received second data signal S2 to the fifth detection module 27 (5), and the sixth data line 21 ( 6) Transmitting the received second data signal S2 to the sixth detection module 27 (6). Wherein, the first data signal S1 may be, for example, a high level signal, and the second data signal S2 may be, for example, a low level signal. The detection module 27 can pass the first data signal S1, but prevent the second data signal S2 from passing. Therefore, if the first data line 21(1) has no line defect, the first data signal S1 is transmitted to the detection signal line 29 after passing through the first data line 21(1) and the first detection module 27(1). However, regardless of the second data line 21(2), the third data line 21(3), the fourth data line 21(4), the fifth data line 21(5) and the sixth data line 21( 6) Whether there is a line defect, the second data signal S2 cannot be transmitted to the detection signal line 29 (the second detection module 27(2), the third detection module 27(3), the fourth detection module 27(4), the fifth detection module The detection module 27(5) and the sixth detection module 27(6) prevent the second data signal S2 from passing through). In this way, the detection signal line 29 only feeds back the signal transmitted by the first data line 21(1) to the control module. The control module compares the detection signal Ts fed back by the detection signal line 29 with the first data signal S1, and if the detection signal Ts is equal to the first data signal S1, it indicates that the first data line 21(1) has no line defect; If the signal Ts is different from the first data signal S1, it indicates that the first data line 21(1) has a line defect. In this way, the automatic detection of the first data line 21(1) is completed.

Next, in the reset phase, the second terminals of each reset module 28 receive the reset signal Vref, and transmit the reset signal Vref to the first terminal of the reset module 28 . The reset signal Vref resets the second end of each detection module 27 to prevent the influence of other signals on the detection, and prevent the first data remaining at the second end of each detection module 27 when detecting the first data line 21 (1). Effect of signal S1 on detection. The detection signal line 29 can feed back the signal of the second terminal of the detection module 27 to the control module. The control module compares the detection signal Ts fed back by the detection signal line 29 with the reset signal Vref, and if the detection signal Ts is equal to the reset signal Vref, it indicates that the reset is completed.

After the reset is completed, in the detection stage, the second data line 21(2) receives the first data signal S1, and transmits the received first data signal S1 to the second detection module 27(2). The first data line 21(1), the third data line 21(3), the fourth data line 21(4), the fifth data line 21(5), and the sixth data line 21(6) respectively Receive the second data signal S2, and transmit the received second data signal S2 to the detection module 27 coupled thereto, that is, the first data line 21(1) transmits the received second data signal S2 to the first detection module 27(1), the third data line 21(3) transmits the received second data signal S2 to the third detection module 27(3), and the fourth data line 21(4) transmits the received second data signal S2 transmitted to the fourth detection module 27(4), the fifth data line 21(5) will transmit the received second data signal S2 to the fifth detection module 27(5), and the sixth data line 21(6) will receive The second data signal S2 of is transmitted to the sixth detection module 27(6). Wherein, the first data signal S1 may be, for example, a high level signal, and the second data signal S2 may be, for example, a low level signal. The detection module 27 can pass the first data signal S1, but prevent the second data signal S2 from passing. Therefore, if the second data line 21(2) has no line defect, the first data signal S1 is transmitted to the detection signal line 29 after passing through the second data line 21(2) and the second detection module 27(2). However, regardless of the first data line 21(1), the third data line 21(3), the fourth data line 21(4), the fifth data line 21(5) and the sixth data line 21( 6) Whether there is a line defect, the second data signal S2 cannot be transmitted to the detection signal line 29 (the first detection module 27(1), the third detection module 27(3), the fourth detection module 27(4), the fifth detection module The detection module 27(5) and the sixth detection module 27(6) prevent the second data signal S2 from passing through). In this way, the detection signal line 29 feeds back the signal transmitted by the second data line 21(2) to the control module. The control module compares the detection signal Ts fed back by the detection signal line 29 with the first data signal S1; if the detection signal Ts is different from the first data signal S1, it indicates that the second data line 21(2) has a line defect. In this way, the automatic detection of the second data line 21(2) is completed.

Then, complete the automatic detection of the third data line 21(3), the fourth data line 21(4), the fifth data line 21(5) and the sixth data line 21(6) in the same way .

It should be noted that the above-mentioned control module may include an analog-to-digital converter and a control unit. The detection signal Ts fed back by the detection signal line 29 is transmitted to the analog-to-digital converter. After the analog-to-digital converter converts the signal into a digital signal, it is sent to the control unit. The control unit compares the digital signal with a signal that needs to be compared (such as the reset signal Vref or first data signal S1). Wherein, the control module can be integrated in the driver chip 24 ; it can also be integrated in the control system 10 ; it can also be set separately on the main board 30 , and the embodiment of the present application does not limit the setting position of the control module.

In the present application, each data line 21 is equipped with a detection module 27, and the automatic detection of each data line 21 is completed through the detection module 27, and the detection efficiency and detection accuracy are high. In addition, the second ends of all detection modules 27 are coupled with the same detection signal line 29, and the second ends of each detection module 27 are reset by the reset module 28, so that the number of detection signal lines 29 can be reduced, and there is no need for Each detection module 27 is provided with a detection signal line 29 . When the number of detection signal lines 29 is reduced, the area occupied by the detection signal lines in the non-display area NAA can be reduced, which is conducive to narrowing the frame of the display panel. In addition, the method for automatically detecting the data line 21 provided by the embodiment of the present application can complete the automatic detection of the data line 21 before the electronic device 100 leaves the factory, or complete the automatic detection of the data line 21 when the electronic device 100 has problems after use. 21 automatic detection, convenient detection.

This embodiment does not specifically limit the manner in which the second end of each reset module 28 receives the reset signal Vref. As long as the second terminal of each reset module 28 can receive the reset signal Vref.

In a possible implementation manner, continue to refer to FIG. 4 , the second terminals of the reset module 28 respectively receive the reset signal Vref. In this way, the time for transmitting the reset signal Vref can be flexibly controlled.

Another possible implementation manner, referring to FIG. 5 , is that the second terminals of all the reset modules 28 are coupled, and receive the reset signal Vref after the second terminals of all the reset modules 28 are coupled. In this way, the synchronization of receiving the reset signal Vref by each reset module 28 is guaranteed, and the wiring can be reduced, which is beneficial to the narrow frame of the display panel 20 .

As for the reset signal Vref, the reset signal Vref may be, for example, a fixed signal sent by the control module. But it does not constitute a limitation to this application. In other optional embodiments, the reset signal Vref can also be a ground potential. The advantage of this setting is that the ground potential can be obtained from the structure in the display panel 20, such as the electrostatic shielding structure. In this way, there is no need to separately set a line for providing the reset signal Vref, which simplifies the process steps.

In addition, regarding the quantity of the reset module 28 , the embodiment of the present application does not limit the quantity of the reset module 28 . The above examples are all described by taking the number of reset modules 28 equal to the number of detection modules 27 as an example, but this does not constitute a limitation to the present application. In other optional implementation manners, for example, the number of the reset module 28 may be only one. For example, referring to FIG. 6 , the second terminals of all detection modules 27 are coupled to the first terminals of the reset module 28 . When the number of the reset module 28 is one, that is, the number of the reset module 28 is reduced, correspondingly, the area occupied by the reset module 28 in the non-display area NAA is reduced, which is beneficial to the narrow frame of the display panel 20 .

It should be noted that, in the following examples, the number of reset modules 28 is N, and the second terminals of all the reset modules 28 are coupled as an example.

Regarding the specific structure of the reset module 28 , this embodiment does not limit the specific structure of the reset module 28 , as long as the second end of the detection module 27 can be reset.

In some possible implementation manners, referring to FIG. 7 , the reset unit 28 includes a first transistor M1. The first pole of the first transistor M1 is coupled to the second terminal of the detection module 27 , the second pole of the first transistor M1 is used to receive the reset signal Vref, and the gate of the first transistor M1 is used to obtain the first switch signal C1 . The first switch signal C1 is used to control whether the first transistor M1 is turned on or off, and further controls whether to transmit the reset signal Vref to the second terminal of the detection module 27 .

It should be noted that, in this embodiment, the first pole of the first transistor M1 is one of the source and drain of the first transistor M1, and the second pole of the first transistor M1 is the source and drain of the first transistor M1. the other of the The transistors in the following embodiments are the same, and will not be repeated in the following embodiments.

Regarding the specific structure of the detection module 27 , this embodiment does not limit the specific structure of the detection module 27 , as long as the first data signal S1 can pass through and the second data signal S2 can be prevented from passing through.

In some possible implementation manners, continue referring to FIG. 7 , the detection module 27 includes a second transistor M2 and a diode D. As shown in FIG. The first pole of the second transistor M2 is coupled to the data line 21, the second pole of the second transistor M2 is coupled to the anode of the diode D, and the cathode of the diode D is coupled to the first pole of the first transistor M1. The gate of the second transistor M2 is used for the second switching signal C2. The second switch signal C2 is used to control the turn-on or turn-off of the second transistor M2, thereby controlling whether to transmit the data signal (first data signal S1 or second data signal S2) transmitted on the data line 21 to the anode of the diode D. The diode D can pass the first data signal S1 and prevent the second data signal S2 from passing.

In some other possible implementation manners, referring to FIG. 8 , the detection module 27 includes a second transistor M2 and a third transistor M3. The first pole of the second transistor M2 is coupled to the data line 21, the second pole of the second transistor M2 is coupled to the first pole of the third transistor M3, the second pole of the third transistor M3 is coupled to the first pole of the first transistor M1 coupling. The gate of the second transistor M2 is used for the second switching signal C2. The gate of the third transistor M3 is coupled to the first electrode of the third transistor M3. The second switch signal C2 is used to control the turn-on or turn-off of the second transistor M2, thereby controlling whether to transmit the data signal (first data signal S1 or second data signal S2) transmitted on the data line 21 to the third transistor M3. first pole. The third transistor M3 can pass the first data signal S1 and prevent the second data signal S2 from passing.

When the reset unit 28 includes a first transistor M1, and the detection module 27 includes a second transistor M2 and a third transistor M3, the first transistor M1, the second transistor M2, and the third transistor M3 can be formed at the same time without setting them separately, so that , can simplify the process steps.

The specific implementation of the present application will be described below assuming that the reset unit 28 includes the first transistor M1, and the detection module 27 includes the second transistor M2 and the third transistor M3. Wherein, the first transistor M1 , the second transistor M2 and the third transistor M3 may all be P-type transistors, or all may be N-type transistors, which is not limited in this embodiment of the present application. The working principles of the detection module 27 and the reset module 28 will be described in detail below with the first transistor M1, the second transistor M2 and the third transistor M3 being N-type transistors:

Fig. 9 is a timing diagram of a detection module and a reset module provided by the embodiment of the present application. Combining Fig. 8 and Fig. 9, in the time period T1, that is, the reset stage, the gate of the first transistor M1 obtains the first switching signal C1 is high level, the second switch signal C2 obtained by the gate of the second transistor M2 is low level, at this time, the first transistor M1 is turned on, and the second transistor M2 and the third transistor M3 are turned off. The reset signal Vref is written into the second pole of the third transistor M3 through the turned-on first transistor M1 to initialize the second pole of the third transistor M3, wherein the reset signal Vref is a low-level signal to prevent other signals from affecting detection impact. In addition, the detection signal line 29 can feed back the signal of the second pole of the third transistor M3 to the control module. The control module compares the detection signal Ts fed back by the detection signal line 29 with the reset signal Vref, and if the detection signal Ts is equal to the reset signal Vref, it indicates that the reset is completed.

During the time period T2, that is, the detection stage, the first switching signal C1 obtained by the gate of the first transistor M1 is at a low level, and the second switching signal C2 obtained by the gate of the second transistor M2 is at a high level. At this time, The first transistor M1 is turned off, and the second transistor M2 and the third transistor M3 are turned on. The first data line 21(1) receives the first data signal S1 (high level signal), and transmits the received first data signal S1 to the first detection module 27(1). The second data line 21(2), the third data line 21(3), the fourth data line 21(4), the fifth data line 21(5), and the sixth data line 21(6) respectively Receive the second data signal S2 (low level signal), and transmit the received second data signal S2 to the detection module 27 coupled thereto, that is, the second data signal S2 to be received by the second data line 21(2) transmitted to the second detection module 27(2), the third data line 21(3) will transmit the received second data signal S2 to the third detection module 27(3), and the fourth data line 21(4) will receive The second data signal S2 transmitted to the fourth detection module 27 (4), the fifth data line 21 (5) transmits the received second data signal S2 to the fifth detection module 27 (5), the sixth data line 21(6) transmits the received second data signal S2 to the sixth detection module 27(6). The second transistor M2 and the third transistor M3 in the first detection module 27(1) can pass the first data signal S1. The second transistor M2 in the second detection module 27(2), the third detection module 27(3), the fourth detection module 27(4), the fifth detection module 27(5) and the sixth detection module 27(6) and the third transistor M3 prevent the second data signal S2 from passing. Therefore, if the first data line 21(1) has no line defect, the first data signal S1 passes through the first data line 21(1) and the second transistor M2 and the third transistor M2 in the first detection module 27(1). After the transistor M3, it is transmitted to the detection signal line 29. However, regardless of the second data line 21(2), the third data line 21(3), the fourth data line 21(4), the fifth data line 21(5) and the sixth data line 21( 6) Whether there is a line defect, the second data signal S2 cannot be transmitted to the detection signal line 29 . In this way, the detection signal line 29 feeds back the signal transmitted by the first data line 21(1) to the control module. The control module compares the detection signal Ts fed back by the detection signal line 29 with the first data signal S1, and if the detection signal Ts is equal to the first data signal S1, it indicates that the first data line 21(1) has no line defect; If the signal Ts is different from the first data signal S1, it indicates that the first data line 21(1) has a line defect. In this way, the automatic detection of the first data line 21(1) is completed.

In the time period T3, that is, the reset phase, the first switching signal C1 obtained by the gate of the first transistor M1 is at a high level, and the second switching signal C2 obtained by the gate of the second transistor M2 is at a low level. At this time, The first transistor M1 is turned on, and the second transistor M2 and the third transistor M3 are turned off. The reset signal Vref is written into the second pole of the third transistor M3 through the turned-on first transistor M1 to initialize the second pole of the third transistor M3, wherein the reset signal Vref is a low-level signal to prevent other signals from affecting The influence of the detection and the prevention of the influence of the first data signal S1 remaining at the second end of each detection module 27 on the detection when the first data line 21 ( 1 ) is detected. In addition, the detection signal line 29 can feed back the signal of the second pole of the third transistor M3 to the control module. The control module compares the detection signal Ts fed back by the detection signal line 29 with the reset signal Vref, and if the detection signal Ts is equal to the reset signal Vref, it indicates that the reset is completed.

In the time period T4, that is, the detection stage, the first switching signal C1 obtained by the gate of the first transistor M1 is at a low level, and the second switching signal C2 obtained by the gate of the second transistor M2 is at a high level. At this time, The first transistor M1 is turned off, and the second transistor M2 and the third transistor M3 are turned on. The second data line 21(2) receives the first data signal S1 (high level signal), and transmits the received first data signal S1 to the second detection module 27(2). The first data line 21(1), the third data line 21(3), the fourth data line 21(4), the fifth data line 21(5), and the sixth data line 21(6) respectively Receive the second data signal S2 (low level signal), and transmit the received second data signal S2 to the detection module 27 coupled thereto, that is, the second data signal S2 to be received by the first data line 21(1) transmitted to the first detection module 27(1), the third data line 21(3) will transmit the received second data signal S2 to the third detection module 27(3), and the fourth data line 21(4) will receive The second data signal S2 transmitted to the fourth detection module 27 (4), the fifth data line 21 (5) transmits the received second data signal S2 to the fifth detection module 27 (5), the sixth data line 21(6) transmits the received second data signal S2 to the sixth detection module 27(6). The second transistor M2 and the third transistor M3 in the second detection module 27(2) can pass the first data signal S1. The second transistor M2 in the first detection module 27(1), the third detection module 27(3), the fourth detection module 27(4), the fifth detection module 27(5) and the sixth detection module 27(6) and the third transistor M3 prevent the second data signal S2 from passing. Therefore, if the second data line 21(2) has no line defect, the first data signal S1 passes through the second data line 21(2) and the second transistor M2 and the third transistor M2 in the second detection module 27(2). After the transistor M3, it is transmitted to the detection signal line 29. However, regardless of the first data line 21(1), the third data line 21(3), the fourth data line 21(4), the fifth data line 21(5) and the sixth data line 21( 6) Whether there is a line defect, the second data signal S2 cannot be transmitted to the detection signal line 29 . In this way, the detection signal line 29 feeds back the signal transmitted by the second data line 21(2) to the control module. The control module compares the detection signal Ts fed back by the detection signal line 29 with the first data signal S1, and if the detection signal Ts is equal to the first data signal S1, it indicates that the second data line 21(2) has no line defect; If the signal Ts is different from the first data signal S1, it indicates that the second data line 21(2) has a line defect. In this way, the automatic detection of the second data line 21(2) is completed.

In the time period T5, that is, the reset phase, the first switching signal C1 obtained by the gate of the first transistor M1 is at a high level, and the second switching signal C2 obtained by the gate of the second transistor M2 is at a low level. At this time, The first transistor M1 is turned on, and the second transistor M2 and the third transistor M3 are turned off. The reset signal Vref is written into the second pole of the third transistor M3 through the turned-on first transistor M1 to initialize the second pole of the third transistor M3, wherein the reset signal Vref is a low-level signal to prevent other signals from affecting The influence of the detection and the prevention of the influence of the first data signal S1 remaining at the second end of each detection module 27 on the detection when the second data line 21 ( 2 ) is detected. In addition, the detection signal line 29 can feed back the signal of the second pole of the third transistor M3 to the control module. The control module compares the detection signal Ts fed back by the detection signal line 29 with the reset signal Vref, and if the detection signal Ts is equal to the reset signal Vref, it indicates that the reset is completed.

It can be known from the above examples that when the first transistor M1 is turned off, the second transistor M2 is turned on; when the first transistor M1 is turned on, the second transistor M2 is turned off. That is, the phases of the first switch signal C1 obtained by the gate of the first transistor M1 and the second switch signal C2 obtained by the gate of the second transistor M2 are opposite. Therefore, referring to FIG. 10 , the display panel 20 further includes an inverter 40 . The input terminal of the inverter 40 is coupled to the gate of the second transistor M2, the output terminal of the inverter 40 is coupled to the gate of the first transistor M1, and the input terminal of the inverter 40 is used to obtain the second switching signal C2. In this way, there is no need to separately provide switch signal lines for the first transistor M1 and the second transistor M2 , that is, only one switch signal line capable of transmitting the second switch signal C2 needs to be provided. The advantage of such setting is that the structure is simple, and it is beneficial to narrow the frame of the display panel 20 .

Based on the same inventive concept, the embodiment of the present application also provides a detection method, which can be applied to the display panel shown in FIG. 8 , and can detect the data lines in the display panel shown in FIG. 8 . Fig. 11 is a flowchart of a detection method provided in the embodiment of the present application. As shown in Fig. 11, the detection method includes:

S111. In the reset phase, send a first switch signal to the gate of the first transistor, so as to write the reset signal into the second pole of the third transistor.

S112. Receive the second detection signal fed back by the detection signal line.

S113. Determine whether the second detection signal is equal to the reset signal; if the second detection signal is equal to the reset signal, execute step S114; if the second detection signal is not equal to the reset signal, return to step S111.

S114. In the detection phase, send a second switch signal to the gate of the second transistor, so as to transmit the signal at the second end of the i-th data line to the detection signal line.

S115. Receive the first detection signal fed back by the detection signal line.

S116. Determine whether the first detection signal is equal to the first data signal transmitted on the i-th data line; if the first detection signal is equal to the first data signal, perform step S117; if the first detection signal is not equal to the first data signal, Then step S118 is executed.

S117. Determine that there is no defect in the i-th data line.

S118. Determine that the i-th data line has a defect.

S119. Repeat step S111 to step S118 until the detection of all N data lines is completed; wherein, i is a positive integer less than or equal to N.

It should be noted that, in order to distinguish between the reset phase and the detection phase, the detection signal Ts fed back by the detection signal line 29 is used. In the reset phase, the detection signal Ts fed back by the detection signal line 29 is the second detection signal, that is, the detection signal Ts at the second end of the detection module 27 is the second detection signal; in the detection phase, the detection signal Ts fed back by the detection signal line 29 is The first detection signal, that is, the detection signal Ts of the second terminal of the i-th detection module 27(i) is the first detection signal. In fact, it is the detection signal Ts fed back by the detection signal line 29 .

Specifically, the control module sends the first switch signal to the gate of the first transistor M1, the first transistor M1 is turned on, and the reset signal Vref is written into the second pole of the third transistor M3 to reset the second pole of the third transistor M3. to initialize. The detection signal line 29 feeds back the signal of the second pole of the third transistor M3 to the control module. The control module compares the detection signal Ts fed back by the detection signal line 29 with the reset signal Vref, and if the detection signal Ts is equal to the reset signal Vref, it indicates that the reset is completed. Then the control module sends a second switching signal C2 to the gate of the second transistor M2, and the second transistor M2 and the third transistor M3 are turned on. The first data line 21(1) receives the first data signal S1 (high level signal), and transmits the received first data signal S1 to the first detection module 27(1). The second data line 21(2), the third data line 21(3), the fourth data line 21(4), the fifth data line 21(5), and the sixth data line 21(6) respectively Receive the second data signal S2 (low level signal), and transmit the received second data signal S2 to the detection module 27 coupled thereto, that is, the second data signal S2 to be received by the second data line 21(2) transmitted to the second detection module 27(2), the third data line 21(3) will transmit the received second data signal S2 to the third detection module 27(3), and the fourth data line 21(4) will receive The second data signal S2 transmitted to the fourth detection module 27 (4), the fifth data line 21 (5) transmits the received second data signal S2 to the fifth detection module 27 (5), the sixth data line 21(6) transmits the received second data signal S2 to the sixth detection module 27(6). The second transistor M2 and the third transistor M3 in the first detection module 27(1) can pass the first data signal S1. The second transistor M2 in the second detection module 27(2), the third detection module 27(3), the fourth detection module 27(4), the fifth detection module 27(5) and the sixth detection module 27(6) and the third transistor M3 prevent the second data signal S2 from passing. Therefore, if the first data line 21(1) has no line defect, the first data signal S1 passes through the first data line 21(1) and the second transistor M2 and the third transistor M2 in the first detection module 27(1). After the transistor M3, it is transmitted to the detection signal line 29. However, regardless of the second data line 21(2), the third data line 21(3), the fourth data line 21(4), the fifth data line 21(5) and the sixth data line 21( 6) Whether there is a line defect, the second data signal S2 cannot be transmitted to the detection signal line 29 . In this way, the detection signal line 29 feeds back the signal transmitted by the first data line 21(1) to the control module. The control module compares the detection signal Ts fed back by the detection signal line 29 with the first data signal S1, and if the detection signal Ts is equal to the first data signal S1, it indicates that the first data line 21(1) has no line defect; If the signal Ts is different from the first data signal S1, it indicates that the first data line 21(1) has a line defect. In this way, the automatic detection of the first data line 21(1) is completed. The above steps are repeated until the detection of all data lines 21 is completed. In this way, the automatic detection of the data line 21 is realized, and the detection efficiency and detection accuracy are high.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still understand the foregoing The technical solutions described in each embodiment are modified, or some of the technical features are replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the various embodiments of the application.

Claims

A display panel, characterized by comprising: N data lines, N detection modules, detection signal lines, and a control module; both the data lines and the detection modules include a first end and a second end;

The N data lines extend along the first direction and are arranged along the second direction, and the second ends of the N data lines are coupled with the first ends of the N detection modules in one-to-one correspondence; the second ends of the N detection modules Both terminals are coupled to the detection signal line; wherein, the first direction crosses the second direction;

The first end of the i-th data line is used to obtain a first data signal; the first ends of other data lines except the i-th data line are used to obtain a second data signal;

The i-th detection module is used to transmit the signal of the second end of the i-th data line to the second end of the i-th detection module during the detection phase; other detection modules except the i-th detection module are used for preventing passage of the second data signal during the detection phase;

The detection signal line is used to transmit the first detection signal of the second end of the i-th detection module to the control module during the detection phase, so that the control module can combine the first detection signal with the first The data signal determines whether the ith data line has a defect;

Wherein, 1≤i≤N, i and N are both positive integers.
The display panel according to claim 1, further comprising: at least one reset module; the reset module includes a first end and a second end; the first end of the reset module is connected to the The second end of the detection module is coupled;

The reset module is used to transmit the reset signal received by the second terminal of the reset module to the second terminals of each of the detection modules during the reset phase, so as to reset the second terminals of the detection modules.
The display panel according to claim 2, wherein the detection signal line is further used to send the second detection signal of the second terminal of the detection module to the control module during the reset phase, so that the The control module determines whether the reset of the second terminal of the detection module is completed according to the second detection signal and the reset signal.
The display panel according to claim 2, wherein the reset module includes a first transistor, and the first transistor includes a gate, a first pole and a second pole;

The first pole of the first transistor is coupled to the second terminal of the detection module, the second pole of the first transistor is used to receive the reset signal, and the gate of the first transistor is used to obtain the first switch signal;

The first switch signal is used to control the first transistor to be turned on in the reset phase, and to control the first transistor to be turned off in the detection phase.
The display panel according to claim 1, wherein the detection module comprises a second transistor and a diode; the second transistor comprises a gate, a first pole and a second pole;

The first pole of the second transistor is coupled to the second end of the data line, the second pole of the second transistor is coupled to the anode of the diode, and the gate of the second transistor is used to obtain the second switch signal; the cathode of each diode is coupled with the detection signal line;

The second switch signal is used to control the second transistor to be turned off in the reset phase, and to control the second transistor to be turned on in the detection phase.
The display panel according to claim 1, wherein the detection module includes a second transistor and a third transistor; each of the second transistor and the third transistor includes a gate, a first electrode, and a second electrode ;

The first pole of the second transistor is coupled to the second end of the data line, the second pole of the second transistor is coupled to the first pole of the third transistor, and the gate of the second transistor is used for Obtaining a second switching signal; the gate of the third transistor is coupled to the first pole of the third transistor; the second end of each third transistor is coupled to the detection signal line;

The second switch signal is used to control the second transistor to be turned off in the reset phase, and to control the second transistor to be turned on in the detection phase.
The display panel according to claim 5 or 6, wherein the display panel further comprises an inverter and at least one reset module; the reset module comprises a first transistor, and the first transistor comprises a gate, a second One pole and a second pole; the first pole of the first transistor is coupled to the second terminal of the detection module, and the second pole of the first transistor is used to receive a reset signal;

The input terminal of the inverter is coupled to the gate of the second transistor, and the output terminal of the inverter is coupled to the gate of the first transistor.
The display panel according to claim 2, wherein the number of the reset module is one, and the second ends of the N detection modules are all coupled to the first ends of the reset module.
The display panel according to claim 2, wherein the number of the reset modules is N, the first ends of the N reset modules are coupled with the second ends of the N detection modules one by one, and the N reset modules The second terminals of the reset module are coupled.
The display panel according to claim 2, wherein the reset signal is a ground potential.
An electronic device, characterized by comprising the display panel described in any one of claims 1-10.
A detection method, which is applied to the display panel according to any one of claims 1-10, the detection method comprising:

In the detection phase, receiving a first detection signal fed back by the detection signal line;

In the detection stage, judging whether the first detection signal is equal to the first data signal obtained by the first end of the i-th data line;

If so, then determine that there is no defect in the i-th data line;

If not, it is determined that the i-th data line has a defect;

The above steps are cyclically executed until the detection of all the N data lines is completed.
The detection method according to claim 12, wherein the display panel further includes at least one reset module, the reset module includes a first transistor; the detection module includes a second transistor and a third transistor; the first A transistor, the second transistor and the third transistor all include a gate, a first pole and a second pole; the first pole of the first transistor is coupled to the second terminal of the third transistor, and the The second pole of the first transistor is used to receive the reset signal; the first pole of the second transistor is coupled to the second end of the data line, and the second pole of the second transistor is coupled to the third transistor The first pole of the third transistor is coupled; the gate of the third transistor is coupled with the first pole of the third transistor; the second end of each third transistor is coupled with the detection signal line;

Before receiving the first detection signal fed back by the detection signal line, it also includes:

In the reset phase, sending a first switch signal to the gate of the first transistor, so as to write the reset signal into the second pole of the third transistor;

In the detection phase, a second switch signal is sent to the gate of the second transistor to transmit the signal at the second end of the i-th data line to the detection signal line.
The detection method according to claim 12, wherein the display panel further includes at least one reset module, the reset module includes a first transistor; the detection module includes a second transistor and a diode; the first transistor and the second transistor both include a gate, a first pole and a second pole; the first pole of the first transistor is coupled to the cathode of the diode, and the second pole of the first transistor is used to receive the reset signal; the first pole of the second transistor is coupled to the second end of the data line, the second pole of the second transistor is coupled to the anode of the diode; the cathode of the diode is coupled to the third The first pole of the transistor is coupled; the cathode of each diode is coupled with the detection signal line;

Before receiving the first detection signal fed back by the detection signal line, it also includes:

In the reset phase, sending a first switching signal to the gate of the first transistor to write the reset signal into the cathode of the diode;

In the detection phase, a second switch signal is sent to the gate of the second transistor to transmit the signal at the second end of the i-th data line to the detection signal line.
The detection method according to claim 13 or 14, further comprising:

In the reset phase, receiving a second detection signal fed back by the detection signal line;

In the reset phase, judging whether the second detection signal is equal to the reset signal;

If so, sending a second switch signal to the gate of the second transistor;

If not, then send a first switch signal to the gate of the first transistor to write the reset signal into the second pole of the third transistor; or, if not, send the first switch signal to the gate of the first transistor The gate sends a first switch signal to write the reset signal into the cathode of the diode.