EP3889951A1

EP3889951A1 - Display screen, and mobile terminal and control method therefor

Info

Publication number: EP3889951A1
Application number: EP19902260.9A
Authority: EP
Inventors: Chun Yen Liu; Dustin Yuk Lun Wai
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-12-25
Filing date: 2019-12-04
Publication date: 2021-10-06
Also published as: WO2020134914A1; CN111369946A; EP3889951A4

Abstract

This application provides a display, a mobile terminal, and a control method thereof. The display includes a display driver (03), a first pixel array (41), and a second pixel array (42). A first voltage input end (112) of a pixel circuit in a first sub-pixel (20a) is electrically connected to a first signal end (113) of the display driver (03), to receive a first supply voltage output by the first signal end (113). A second voltage input end (122) is electrically connected to a second signal end (123) of the display driver (03), to receive a second supply voltage output by the second signal end (123). A third voltage input end (132) of a pixel circuit in a second sub-pixel (20b) is electrically connected to a third signal end (133) of the display driver (03), to receive a third supply voltage output by the third signal end (133). A fourth voltage input end (142) is electrically connected to the second signal end (123) of the display driver (03), to receive the second supply voltage output by the second signal end (123). A voltage value of the third supply voltage is different from a voltage value of the first supply voltage.

Description

This application claims priority to Chinese Patent Application No. 201811593997.0 , filed with the China National Intellectual Property Administration on December 25, 2018 and entitled "DISPLAY, MOBILE TERMINAL, AND CONTROL METHOD THEREOF", which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This application relates to the field of display technologies, and in particular, to a display, a mobile terminal, and a control method thereof.

BACKGROUND

With continuous development of display technologies, mobile terminals having a display function, such as mobile phones, tablet computers, and smartwatches, have an increasingly large market share. However, currently, the mobile terminals cannot implement area-based luminance control based on a user requirement or a product design requirement. This is not conducive to improving competitiveness of a product in a market.

SUMMARY

This application provides a display, a mobile terminal, and a control method thereof, to resolve a problem that a mobile terminal cannot implement area-based luminance control based on a user requirement or a product design requirement.
To achieve the foregoing objective, the following technical solutions are used in this application.
According to one aspect of this application, a display is provided. The display includes a display driver, a first pixel array, and a second pixel array. The display driver includes a first signal end, a second signal end, and a third signal end. In addition, the first pixel array includes a plurality of first sub-pixels, and a pixel circuit in the first sub-pixel includes a first voltage input end and a second voltage input end. The second pixel array includes a plurality of second sub-pixels, and a pixel circuit in the second sub-pixel includes a third voltage input end and a fourth voltage input end. On this basis, the first voltage input end of the pixel circuit in the first sub-pixel is electrically connected to the first signal end of the display driver, to receive a first supply voltage output by the first signal end. The second voltage input end is electrically connected to the second signal end of the display driver, to receive a second supply voltage output by the second signal end. The third voltage input end of the pixel circuit in the second sub-pixel is electrically connected to the third signal end of the display driver, to receive a third supply voltage output by the third signal end. The fourth voltage input end is electrically connected to the second signal end of the display driver, to receive the second supply voltage output by the second signal end. A voltage value of the third supply voltage is different from a voltage value of the first supply voltage. In this way, power is separately supplied for the pixel circuit in the first pixel array and the pixel circuit in the second pixel array, so that ΔV = ELVDD - ELVSS of each pixel circuit in an area in which the first pixel array is located, and ΔV = ELVDD - ELVSS of each pixel circuit in an area in which the second pixel array is located are separately adjusted, so as to implement area-based luminance control on the display.
Optionally, the first supply voltage output by the first signal end of the display driver is greater than the second supply voltage output by the second signal end of the display driver. The third supply voltage output by the third signal end of the display driver is greater than the second supply voltage output by the second signal end of the display driver. In this case, the first sub-pixel and the second sub-pixel may share the second supply voltage. In other words, the second supply voltage is a voltage ELVSS.
Optionally, the pixel circuit in the first sub-pixel in the first pixel array includes a first driving transistor and a first light emitting device. A first electrode of the first driving transistor is electrically connected to the first signal end of the display driver, a second electrode of the first driving transistor is electrically connected to an anode of the first light emitting device, and a cathode of the first light emitting device is electrically connected to the second signal end of the display driver. The second pixel array includes a plurality of second sub-pixels, and the pixel circuit in the second sub-pixel includes a second driving transistor and a second light emitting device. A first electrode of the second driving transistor is electrically connected to the third signal end of the display driver, a second electrode of the second driving transistor is electrically connected to an anode of the second light emitting device, and a cathode of the second light emitting device is electrically connected to the second signal end of the display driver. In this case, the first electrode of the first driving transistor is the first voltage input end of the pixel circuit in the first sub-pixel. The cathode of the first light emitting device is the second voltage input end of the pixel circuit in the first sub-pixel. The first electrode of the second driving transistor is the third voltage input end of the pixel circuit in the second sub-pixel. The cathode of the second light emitting device is the fourth voltage input end of the pixel circuit in the second sub-pixel.
Optionally, the first supply voltage output by the first signal end of the display driver is less than the second supply voltage output by the second signal end of the display driver. The third supply voltage output by the third signal end of the display driver is less than the second supply voltage output by the second signal end of the display driver. In this case, the first sub-pixel and the second sub-pixel may share the second supply voltage. The second supply voltage is a voltage ELVSS.
Optionally, the pixel circuit in the first sub-pixel in the first pixel array includes a first driving transistor and a first light emitting device. A first electrode of the first driving transistor is electrically connected to the second signal end of the display driver, a second electrode of the first driving transistor is electrically connected to an anode of the first light emitting device, and a cathode of the first light emitting device is electrically connected to the first signal end of the display driver. The second pixel array includes a plurality of second sub-pixels, and the pixel circuit in the second sub-pixel includes a second driving transistor and a second light emitting device. A first electrode of the second driving transistor is electrically connected to the second signal end of the display driver, a second electrode of the second driving transistor is electrically connected to an anode of the second light emitting device, and a cathode of the second light emitting device is electrically connected to the third signal end of the display driver. In this case, the first electrode of the first driving transistor is the second voltage input end of the pixel circuit in the first sub-pixel. The cathode of the first light emitting device is the first voltage input end of the pixel circuit in the first sub-pixel. The first electrode of the second driving transistor is the fourth voltage input end of the pixel circuit in the second sub-pixel. The cathode of the second light emitting device is the third voltage input end of the pixel circuit in the second sub-pixel.
Optionally, the display driver includes a power management integrated circuit. The power management integrated circuit includes a first voltage end, a second voltage end, and a third voltage end. The first voltage end of the power management integrated circuit is electrically connected to the first voltage input end of the pixel circuit in the first sub-pixel. A second output end of the power management integrated circuit is electrically connected to the second voltage input end of the pixel circuit in the first sub-pixel and the fourth voltage input end of the pixel circuit in the second sub-pixel. A third output end of the power management integrated circuit is electrically connected to the third voltage input end of the pixel circuit in the second sub-pixel. Therefore, luminance of the area in which the first pixel array is located and luminance of the area in which the second pixel array is located may be respectively controlled by using one power management integrated circuit.
Optionally, the display driver includes a first power management integrated circuit and a second power management integrated circuit. The first power management integrated circuit includes a first voltage end and a second voltage end. The second power management integrated circuit includes a third voltage end and a fourth voltage end. The first voltage end of the first power management integrated circuit is electrically connected to the first voltage input end of the pixel circuit in the first sub-pixel. The third voltage end of the second power management integrated circuit is electrically connected to the third voltage input end of the pixel circuit in the second sub-pixel. The second output end of the first power management integrated circuit is electrically connected to the second voltage input end of the pixel circuit in the first sub-pixel and the fourth voltage input end of the pixel circuit in the second sub-pixel. Alternatively, the fourth output end of the second power management integrated circuit is electrically connected to the second voltage input end of the pixel circuit in the first sub-pixel and the fourth voltage input end of the pixel circuit in the second sub-pixel. Therefore, luminance of an area in which the first pixel array is located and luminance of an area in which the second pixel array is located may be respectively controlled by using the first power management integrated circuit and the second power management integrated circuit.
Optionally, an active area includes an auxiliary display area and a main display area. A non-display side of the auxiliary display area is configured to integrate a camera lens or a sensor. The first pixel array is located in the auxiliary display area. The second pixel array is located in the main display area. Pixels per inch of the auxiliary display area are less than pixels per inch of the main display area. In this way, a sub-pixel in the auxiliary display area has a larger light transparent area, so that the camera lens or the sensor located on the non-display side of the auxiliary display area receives or sends more light that passes through the display.
Optionally, a light non-transparent area occupied by the pixel circuit in the first sub-pixel is the same as a light non-transparent area occupied by the pixel circuit in the second sub-pixel. A light transparent area of the first sub-pixel other than the pixel circuit is greater than a light transparent area of the second sub-pixel other than the pixel circuit.
Optionally, the display further includes an underlying substrate, and the first pixel array and the second pixel array are disposed on the underlying substrate. A material constituting the underlying substrate includes a flexible resin material. The display drive circuit further includes a processor, the processor is electrically connected to at least one power management integrated circuit, and the processor is configured to: when detecting that the first pixel array or the second pixel array is bent to a non-display side of the display, output a luminance control signal to the at least one power management integrated circuit. The display may be bent. When the first pixel array or the second pixel array is bent to the non-display side of the display, luminance of an area in which the pixel array bent to the non-display side of the display is located may be decreased by using the processor.
According to another aspect, a mobile terminal is provided, including any one of the foregoing displays. The mobile terminal further includes a camera lens and a sensor. The camera lens and/or the sensor are/is located on a non-display side of the display. The foregoing mobile terminal has a same technical effect as the display provided in the foregoing embodiment. Details are not described herein again.
Optionally, the display includes an auxiliary display area and a main display area, and pixels per inch of the auxiliary display area are less than pixels per inch of the main display area. The camera lens and the sensor are disposed on a non-display side of the auxiliary display area. When the camera lens and the sensor are located on the non-display side of the display, a bezel-less screen may be implemented.
Optionally, an opening is disposed on the display. The display includes auxiliary display areas located on two sides of the opening and a main display area located below the opening. Pixels per inch of the auxiliary display area are less than pixels per inch of the main display area. The camera lens is located in the opening. The sensor is disposed on a non-display side of the auxiliary display area. The foregoing display is a free-form display.
According to another aspect, a mobile terminal control method is provided. The mobile terminal includes a display. The display includes a display driver, a first pixel array, and a second pixel array. The display driver includes a first signal end, a second signal end, and a third signal end. The first pixel array includes a plurality of first sub-pixels, and a pixel circuit in the first sub-pixel includes a first voltage input end and a second voltage input end. The second pixel array includes a plurality of second sub-pixels, and a pixel circuit in the second sub-pixel includes a third voltage input end and a fourth voltage input end. The first voltage input end of the pixel circuit in the first sub-pixel is electrically connected to the first signal end of the display driver, and the second voltage input end is electrically connected to the second signal end of the display driver. The third voltage input end of the pixel circuit in the second sub-pixel is electrically connected to the third signal end of the display driver, and the fourth voltage input end is electrically connected to the second signal end of the display driver. In addition, the display further includes an underlying substrate, the first pixel array and the second pixel array are disposed on the underlying substrate, and a material constituting the underlying substrate includes a flexible resin material, so that the display is a flexible display that can be bent. Based on this, the mobile terminal control method includes: The display driver first detects that the first sub-pixel array is bent to a non-display side of the display; the first signal end of the display driver decreases a first supply voltage that is input to the first voltage input end of the pixel circuit in the first sub-pixel in the first sub-pixel array; or the second signal end of the display driver increases a second supply voltage that is output to the second voltage input end of the pixel circuit in the first sub-pixel, to decrease luminance of the first sub-pixel. The first supply voltage is greater than the second supply voltage. The foregoing mobile terminal control method has a technical effect that is the same as that of the mobile terminal provided in the foregoing embodiment. Details are not described herein again.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic structural diagram of a display according to some embodiments of this application;
FIG. 2 is a schematic structural diagram of a pixel circuit of each sub-pixel in FIG. 1;
FIG. 3 is a timing diagram of a control signal of a pixel circuit shown in FIG. 2;
FIG. 4 is an equivalent circuit diagram that is of a pixel circuit shown in FIG. 2 and that corresponds to a third phase in FIG. 3;
FIG. 5a is a curve chart of a relationship between a current flowing through an OLED and a voltage applied to a cathode and an anode of the OLED in FIG. 2;
FIG. 5b is an output characteristic curve chart of a driving transistor in FIG. 2;
FIG. 5c is a schematic structural diagram of another display according to some embodiments of this application;
FIG. 6a is a schematic structural diagram of a mobile terminal according to some embodiments of this application;
FIG. 6b is another schematic structural diagram of a mobile terminal according to some embodiments of this application;
FIG. 6c is another schematic structural diagram of a mobile terminal according to some embodiments of this application;
FIG. 7 is a schematic diagram of division of a display area around an opening in FIG. 6a or FIG. 6b;
FIG. 8 is a schematic arrangement diagram of sub-pixels around an opening in FIG. 6a or FIG. 6b;
FIG. 9 is another schematic arrangement diagram of sub-pixels around an opening in FIG. 6a or FIG. 6b;
FIG. 10 is a schematic diagram of a setting manner of a sensor in FIG. 6b;
FIG. 11a is a schematic arrangement diagram of sub-pixels around an opening in FIG. 6b;
FIG. 11b is a schematic structural diagram of a pixel circuit of some sub-pixels shown in FIG. 11a;
FIG. 11c is another schematic arrangement diagram of sub-pixels around an opening in FIG. 6b;
FIG. 12a is another schematic arrangement diagram of sub-pixels around an opening in FIG. 6b;
FIG. 12b is another schematic arrangement diagram of sub-pixels around an opening in FIG. 6b;
FIG. 12c is a schematic structural diagram of a pixel circuit of some sub-pixels shown in FIG. 12b;
FIG. 13a is a schematic structural diagram of a display according to some embodiments of this application;
FIG. 13b is another schematic structural diagram of a display according to some embodiments of this application;
FIG. 13c is a schematic output characteristic curve chart of a driving transistor in a pixel circuit of a display according to some embodiments of this application;
FIG. 14a is another schematic structural diagram of a display according to some embodiments of this application;
FIG. 14b is another schematic structural diagram of a display according to some embodiments of this application;
FIG. 15 is a schematic structural diagram of a cathode layer in a display according to some embodiments of this application;
FIG. 16 is a schematic sectional view of a display according to some embodiments of this application;
FIG. 17 is a schematic display diagram of a display according to some embodiments of this application;
FIG. 18a is a schematic diagram of a folding manner of a display according to some embodiments of this application;
FIG. 18b is a schematic diagram of a display folded in the folding manner shown in FIG. 18a;
FIG. 19 is a schematic diagram of another folding manner of a display according to some embodiments of this application;
FIG. 20 is a schematic diagram of another folding manner of a display according to some embodiments of this application;
FIG. 21a is a schematic diagram of a division manner of a display subarea of a display according to some embodiments of this application;
FIG. 21b is a schematic structural diagram of a connection between a PMIC and a pixel circuit of each sub-pixel in FIG. 21a;
FIG. 22a is a schematic diagram of another division manner of a display subarea of a display according to some embodiments of this application;
FIG. 22b is a schematic structural diagram of a connection between a PMIC and a pixel circuit of each sub-pixel in FIG. 22a;
FIG. 23 is schematic display diagram of an another display according to some embodiments of this application; and
FIG. 24 is a schematic diagram of another division manner of a display subarea of a display according to some embodiments of this application.

Reference numerals:
01: mobile terminal; 02: pixel; 03: display driver; 113: first signal end of the display driver; 123: second signal end of the display driver; 133: third signal end of the display driver; 10: display; 11: camera lens; 12: infrared radiation sensor; 13: 3D sensor; 20: sub-pixel; 20a: first sub-pixel; 112: first voltage input end of the first sub-pixel; 122: second voltage input end of the first sub-pixel; 20b: second sub-pixel; 20c: third sub-pixel; 132: third voltage input end of the second sub-pixel; 142: fourth voltage input end of the second sub-pixel; 100: AA area; 101: non-display area; 110: auxiliary display area; 120: main display area; 201: pixel circuit; 200: opening; 30: PMIC; 31: processor; 300: cathode layer; 301: first electrode block; 302: second electrode block; 21: pixel define layer; 22: anode of an OLED; 23: organic function layer; 24: cathode of the OLED; 400: TFT backplane; 41: first pixel array; and 42: second pixel array.

DESCRIPTION OF EMBODIMENTS

The following describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. It is clearly that the described embodiments are merely a part rather than all of the embodiments of the present invention.
In this specification, the terms "first" and "second" in this application are merely intended for a purpose of description, and shall not be understood as an indication or implication of relative importance or implicit indication of the number of indicated technical features. Therefore, a feature limited by "first" or "second" may explicitly or implicitly include one or more features. In the description of the present invention, unless otherwise stated, "a plurality of' means two or more than two.
In addition, in this specification, orientation terms such as "upper", "lower", "left", and "right" are defined relative to orientations of display panels in the accompanying drawings. It should be understood that these orientation terms are relative concepts, they are used for relative description and clarification, and may change correspondingly according to a change in a position in which the display panel is placed in the accompanying drawings.
This application provides a mobile terminal. The mobile terminal may be a mobile phone, a tablet computer, a notebook computer, a personal digital assistant (personal digital assistant, PDA), an in-vehicle computer, or the like. A specific form of the mobile terminal is not particularly limited in the embodiments of this application.
The mobile terminal includes a display 10 shown in FIG. 1. The display 10 is an organic light emitting diode (Organic Light Emitting Diode, OLED) display. The OLED display has features such as self-luminance, a response speed block, a large field of view, and being capable of being manufactured on a flexible substrate.
In addition, the display 10 includes an active area (active area, AA) 100 and a non-display area 101 located around the AA area 100.
The active area 100 includes a plurality of sub-pixels (sub-pixel) 20. For ease of description, in this application, descriptions are provided by using an example in which the plurality of sub-pixels 20 are arranged in a form of a matrix.
In this case, sub-pixels 20 arranged in a row in a horizontal direction X are referred to as sub-pixels in a same row, and sub-pixels 20 arranged in a row in a vertical direction Y are referred to as sub-pixels in a same column.
In addition, a pixel circuit 201 configured to control the sub-pixel 20 to perform displaying is disposed in the sub-pixel 20. As shown in FIG. 2, the pixel circuit 201 includes a capacitor C, a plurality of switching transistors (M1, M2, M3, M5, M6, and M7), and one driving transistor M4.
It should be noted that a working process of the pixel circuit 201 shown in FIG. 2 includes three phases shown in FIG. 3: a first phase ① a second phase ②, and a third phase ③.
In the first phase ①, the transistor M1 and the transistor M7 that are shown in FIG. 2 are turned on under control of a first gating signal N-1. An initial voltage Vint is separately transmitted to a gate (gate, g for short) of the driving transistor M4 and an anode (anode, a for short) of the OLED by using the transistor M1 and the transistor M7, to reset the anode a of the OLED and the gate g of the driving transistor M4.
In the second phase ②, the transistor M2 and the transistor M3 are turned on under control of a second gating signal N. When the transistor M3 is turned on, the gate g of the driving transistor M4 is electrically connected to a drain (drain, d for short), and the driving transistor M4 is in a diode forward state. In this case, a data signal Vdata is written into a source (source, s for short) of the driving transistor M4 by using the conductive transistor M2, and a threshold voltage V_th of the driving transistor M4 is compensated.
In the third phase ③, under control of an emission control signal EM, the transistor M5 and the transistor M6 are turned on, and a current path between a voltage ELVDD and a voltage ELVSS is turned on. In this case, an equivalent circuit diagram in the third phase is shown in FIG. 4. The driving transistor M4 is turned on, a first electrode (the source s) of the driving transistor M4 receives the voltage ELVDD, and a second electrode of the driving transistor M4 is electrically connected to the anode (a) of the OLED. A cathode (c) of the OLED receives the voltage ELVSS. In this case, a drive current I_sd generated by the driving transistor M4 is transmitted to the OLED through the current path, to drive the OLED to emit light.
It can be learned from FIG. 4 that a voltage difference ΔV between the voltage ELVDD and the voltage ELVSS meets the following formula (1): $Δ V = ELVDD - ELVSS = V_{sd} + V_{OLED}$
V_sd is a source voltage of the driving transistor M4. V_OLED is a voltage difference between the anode (anode, a for short) of the OLED and the cathode (cathode, c for short).
In the third phase ③, luminance of the OLED is directly proportional to a current I_OLED (which is the same as the foregoing drive current I_ds) flowing through the OLED.
In addition, as shown in FIG. 5a, the I_OLED is directly proportional to the V_OLED. In this case, when luminance of the sub-pixel 20 is larger, the V_OLED of the OLED in the sub-pixel 20 is larger. Therefore, ΔV = ELVDD - ELVSS in the formula (1) is larger. When the luminance of the sub-pixel 20 is smaller, the V_OLED of the OLED in the sub-pixel 20 is smaller, and ΔV = ELVDD - ELVSS is smaller.
In this case, the OLED display 10 provided in this embodiment of this application may adjust ΔV = ELVDD - ELVSS of different areas based on a requirement, to implement area-based luminance control.
To implement area-based luminance control, an embodiment of this application provides a display 01. As shown in FIG. 5c, the display 01 includes a display driver 03, a first pixel array 41, and a second pixel array 42.
The display driver 03 includes a first signal end 113, a second signal end 123, and a third signal end 133.
In addition, the first pixel array 41 includes a plurality of first sub-pixels 12a. A pixel circuit 201 of the first sub-pixel 12a includes a first voltage input end 112 and a second voltage input end 122.
The second pixel array 42 includes a plurality of second sub-pixels 12b. The pixel circuit 201 of the second sub-pixel 12b includes a third voltage input end 132 and a fourth voltage input end 142.
The first voltage input end 112 of the pixel circuit 201 of the first sub-pixel 12a is electrically connected to the first signal end 113 of the display driver 03, and receives a first supply voltage V1 output by the first signal end 113.
The second voltage input end 122 of the pixel circuit 21 of the first sub-pixel 12a is electrically connected to the second signal end 123 of the display driver 03, and receives a second supply voltage V2 output by the second signal end 123.
The third voltage input end 132 of the pixel circuit 201 of the second sub-pixel 12b is electrically connected to the third signal end 133 of the display driver 03, and receives a third supply voltage V3 output by the third signal end 133.
The fourth voltage input end 142 of the pixel circuit 201 of the second sub-pixel 12b is electrically connected to the second signal end 123 of the display driver 03, and receives the second supply voltage V2 output by the second signal end 123.
A voltage value of the third supply voltage V3 is different from a voltage value of the first supply voltage V1.
In some embodiments of this application, the first supply voltage V1 is greater than the second supply voltage V2, and the third supply voltage V3 is also greater than the second supply voltage V2. In this case, the second supply voltage V2 may be the voltage ELVSS. In this case, the pixel circuit 102 of the first pixel array 41 and the pixel circuit 102 of the second pixel array 42 share the voltage ELVSS.
Alternatively, in some other embodiments of this application, the first supply voltage V1 is less than the second supply voltage V2, and the third supply voltage V3 is also less than the second supply voltage V2. In this case, the second supply voltage V2 may be the voltage ELVDD. In this case, the pixel circuit 102 of the first pixel array 41 and the pixel circuit 102 of the second pixel array 42 share the voltage ELVDD.
In this way, power is separately supplied to the pixel circuit 102 of the first pixel array 41 and the pixel circuit 102 of the second pixel array 42, so that ΔV = ELVDD - ELVSS of each pixel circuit in an area in which the first pixel array 41 is located, and ΔV = ELVDD - ELVSS of each pixel circuit in an area in which the second pixel array 42 is located are separately adjusted, so as to implement area-based luminance control on the display 01.
The following describes, by using examples, processes of performing area-based luminance control on the display 01 in different scenarios.

Embodiment 1

In this embodiment, the mobile terminal 01 having the display 10 is integrated with a plurality of electronic components, such as a camera lens 11, an infrared radiation sensor (infrared radiation sensor, IR sensor) 12, and a 3D sensor (3D sensor) 13 shown in FIG. 6a, which are configured to implement different functions.
To improve a screen-to-body ratio (a ratio of an active area of the display to the entire display) of the mobile phone display 10, in some embodiments of this application, an opening 200 is provided on the display 10 of the mobile terminal 01.
In this way, the electronic components may be disposed in the opening 200. Based on this, parts of the display 10 that are located on two sides of the opening 200 can still be displayed, to improve the screen-to-body ratio of the display.
Based on this, to further improve the screen-to-body ratio of the display 10, as shown in FIG. 6b, some electronic components such as the IR sensor 12 and the 3D sensor 13 may be disposed under the display 10 (under display), that is, on a non-display side of the display 10. In other words, both a receiver and a transmitter of the IR sensor 12 and a receiver and a transmitter of the 3D sensor 13 are disposed under the display 10. The camera lens 11 is disposed in the opening 200.
Alternatively, as shown in FIG. 6c, the IR sensor 12, the 3D sensor 13, and the camera lens 11 may all be disposed under the display 10, that is, on the non-display side of the display. In this way, the screen-to-body ratio of the display 10 is further improved, and an effect of bezel-less screen is achieved.
It should be noted that in this embodiment of this application, a structure shown in FIG. 6b may be used, or a structure shown in FIG. 6c may be used. This is not limited in this application. For ease of description, the following uses a free-form display shown in FIG. 6b as an example for description.
In this case, light emitted by the transmitter of the sensor may be emergent from the display 10 through a light transparent part of the sub-pixel 20 in the display. When the light emitted by the sensor encounters an obstacle, the light is reflected, and the reflected light may be incident to the receiver of the sensor through the light transparent part of the sub-pixel 20 in the display, so that the sensor can perform a sensing operation based on the received reflected light. In this way, an area of the opening 200 can be reduced, and the screen-to-body ratio can be increased.
However, due to impact of the opening 200, the AA area 100 of the display 10 needs to bypass the opening 200. Therefore, the AA area 100 of the display 10 is no longer a complete rectangle. In this case, as shown in FIG. 7, the AA area 100 of the display 10 may be divided into auxiliary display areas 110 located on the two sides of the opening 200 and a main display area 120 that is located under the opening 200 and the auxiliary display areas 110.
In this case, the first pixel array 41 is disposed in the auxiliary display areas 110. As shown in FIG. 8, the first pixel array 41 includes a plurality of first sub-pixels 20a.
The second pixel array 42 is disposed in the main display area 120. As shown in FIG. 8, the second pixel array 42 includes a plurality of second sub-pixels 20b.
As shown in FIG. 8, the second sub-pixels 20b in the main display area 120 are arranged in entire rows in a horizontal direction X. For example, in the main display area 120, a quantity of second sub-pixels 20b in one row in the horizontal direction X is N. N ≥ 2, where N is a positive integer.
In addition, because of the opening 200, in the auxiliary display areas 110, a quantity of first sub-pixels 20a in one row in the horizontal direction X is M. 2 ≤ M ≤ N, where M is a positive integer.
However, it can be learned from the foregoing description that a pixel circuit 201 of the display 10 includes a plurality of transistors. The transistor is mainly made of an opaque metal material, so that the first sub-pixel 20a or the second sub-pixel 20b has relatively high metal density (metal density), and a transparent area of the first sub-pixel 20a or the second sub-pixel 20b is correspondingly reduced.
In this case, when the foregoing under display technology is used, the light sent by the transmitter of the IR sensor 12 and the 3D sensor 13 cannot effectively pass through the light transparent part of the first sub-pixel 20a, and the reflected light cannot effectively pass through the light transparent part of the first sub-pixel 20a, and cannot be incident to the receivers of the IR sensor 12 and the 3D sensor 13. Therefore, detection precision of the sensor is reduced.
In some embodiments of this application, to improve detection precision of the sensor, pixels per inch (pixels per inch, PPI) of the auxiliary display area 110 may be enabled to be less than a PPI of the main display area 120, as shown in FIG. 9.
In this way, an area of the first sub-pixel 20a in the auxiliary display area 110 is greater than an area of the second sub-pixel 20b in the main display area 120, so that the light transparent area of the first sub-pixel 20a in the auxiliary display area 110 is greater than the light transparent area of the second sub-pixel 20b in the main display area 120.
Based on this, as shown in FIG. 10, the first sub-pixel 20a in the auxiliary display area 110 has a sufficient light transparent part, so that the light sent by the transmitter of the IR sensor 12 and the 3D sensor 13 can be emitted by the display 10, and the reflected light can also pass through the light transparent part of the first sub-pixel 20a in the auxiliary display area 110, and can be incident to the receivers of the sensors, for example, the IR sensor 12 and the 3D sensor 13, located under the auxiliary display area 110. In this way, the sensor can send and receive more light, to improve the sensing precision of the sensor.
To enable the PPI of the auxiliary display area 110 to be less than the PPI of the main display area 120, this application provides the following solutions.

Example 1

In this example, a quantity of first sub-pixels 20a in one pixel 02 in the auxiliary display area 110 is different from a quantity of second sub-pixels 20b in one pixel 02 in the main display area 120.
For example, as shown in FIG. 11a, in the display 10, lengths L1 of any two pixels (pixel) 02 in an X direction are the same, and lengths L2 of any two pixels (pixel) 02 in a Y direction are the same.
In addition, the quantity of first sub-pixels 20a in one pixel 02 in the auxiliary display area 110 is less than the quantity of second sub-pixels 20b in one pixel 02 in the main display area 120. Therefore, an area of the first sub-pixel 20a in the auxiliary display area 110 may be greater than an area of the second sub-pixel 20b in the main display area 120.
For example, one pixel 02 in the auxiliary display area 110 includes three first sub-pixels 20a, which are respectively a first sub-pixel in red (red, R), a first sub-pixel in green (green, G), and a first sub-pixel in blue (blue, B).
One pixel 02 in the main display area 120 includes four second sub-pixels 20b, which are respectively an R second sub-pixel, a G second sub-pixel, a B second sub-pixel, and a W (white, W) second sub-pixel.
In this case, an example in which a pixel circuit in any first sub-pixel 20a and a pixel circuit in any second sub-pixel 20b in the display 10 use the structure shown in FIG. 2 is used.
As shown in FIG. 11b, in the auxiliary display area 110 in the Y direction, in pixel circuits of the first sub-pixels 20a located in the same column, a source (s) of a transistor M2 is electrically connected to a same data line (data line, DL). The DL is used to provide a data voltage Vdata.
In addition, in the main display area 120 in the Y direction, in the pixel circuit in the second sub-pixels 20b located in the same column, a source (s) of a transistor M2 is electrically connected to a same DL.
Based on this, it can be learned from FIG. 11b that, in the Y direction, a pixel circuit in a first sub-pixel 20a in a third column of the auxiliary display area 110 and a pixel circuit in a second sub-pixel 20b in a fourth column of the main display area 120 are electrically connected to a same DL.
In addition, in the Y direction, a DL electrically connected to a pixel circuit in a second sub-pixel 20b in a first column, a pixel circuit in a second sub-pixel 20b in a second column, and a pixel circuit in a second sub-pixel 20b in a third column in the main display area 120 does not need to be shared by the pixel circuit in the auxiliary display area 110.
Alternatively, for another example, as shown in FIG. 11c, a pixel 02 in the auxiliary display area 110 includes three first sub-pixels 20a, which are respectively an R first sub-pixel, a G first sub-pixel, and a B first sub-pixel.
Pixels in the main display area 120 are arranged in a pentile manner. To be specific, one pixel 02 in the main display area 120 includes two second sub-pixels 20b, which are respectively an R second sub-pixel and a G second sub-pixel, or a B second sub-pixel and a G second sub-pixel.
An area of the R second sub-pixel and an area of the B second sub-pixel in the main display area 120 each are twice as large as an area of the G second sub-pixel. Two adjacent pixels 02 share an R second sub-pixel or a B second sub-pixel.
In addition, in the display 10, a length L1b of one pixel 02 in the auxiliary display area 110 in the X direction is greater than a length L1a of one pixel 02 in the main display area 120 in the X direction. Therefore, an area of the first sub-pixel 20a in the auxiliary display area 110 is greater than an area of the first sub-pixel 20b in the main display area 120.
In the display 10 shown in FIG. 11c, for a manner of connecting a pixel circuit of each sub-pixel to the DL, refer to FIG. 11b for setting. Details are not described herein again.

Example 2

In this example, as shown in FIG. 12a or FIG. 12b, a quantity of first sub-pixels 20a in one pixel 02 in the auxiliary display area 110 is the same as a quantity of second sub-pixels 20b in one pixel 02 in the main display area 120.
For example, one pixel 02 in the auxiliary display area 110 includes three first sub-pixels 20a, which are respectively a first sub-pixel in red (red, R), a first sub-pixel in green (green, G), and a first sub-pixel in blue (blue, B).
One pixel 02 in the main display area 120 includes three second sub-pixels 20b, which are respectively the R second sub-pixel, the G second sub-pixel, and the B second sub-pixel.
In addition, as shown in FIG. 12a or FIG. 12b, in the display 10, a length L1b of the pixel 02 in the auxiliary display area 110 in an X direction is greater than a length L1a of the pixel 02 in the main display area 120 in the X direction. In FIG. 12b, L1b is approximately twice L1a. A length L2b of the pixel 02 in the auxiliary display area 110 in a Y direction may be the same as a length L2a of the pixel 02 in the main display area 120 in the Y direction. Therefore, an area of the first sub-pixel 20a in the auxiliary display area 110 is greater than an area of the second sub-pixel 20b in the main display area 120.
In this case, a structure shown in FIG. 12b is used as an example, and an example in which a pixel circuit in any sub-pixel in the display 10 uses a structure shown in FIG. 2 is used.
As shown in FIG. 12c, in the auxiliary display area 110 in the Y direction, in a pixel circuit in the first sub-pixels 20a in the same column, a source (s) of a transistor M2 is electrically connected to a same DL. The DL is used to provide a data voltage Vdata.
In addition, in the main display area 120 in the Y direction, in the pixel circuit in the second sub-pixels 20b located in the same column, a source (s) of a transistor M2 is electrically connected to a same DL.
Based on this, it can be learned from FIG. 12c that a pixel circuit in a first sub-pixel 20a in a first column of the auxiliary display area 110 and a pixel circuit in a second sub-pixel 20b in a second column of the main display area 120 are electrically connected to a same DL in the Y direction.
A pixel circuit in a first sub-pixel 20a in a second column of the auxiliary display area 110 and a pixel circuit in a second sub-pixel 20b in a fourth column of the main display area 120 are electrically connected to a same DL.
A pixel circuit in a first sub-pixel 20a in a third column of the auxiliary display area 110 and a pixel circuit in a second sub-pixel 20b in a sixth column of the main display area 120 are electrically connected to a same DL.
In addition, in the Y direction, a DL electrically connected to a pixel circuit in a second sub-pixel 20b in a first column, a pixel circuit in a second sub-pixel 20b in a third column, and a pixel circuit in a second sub-pixel 20b in a fifth column in the main display area 120 does not need to be shared by the pixel circuit in the auxiliary display area 110. Therefore, the DL that may be electrically connected to the pixel circuit in the second sub-pixel 20b in the first column, the pixel circuit in the second sub-pixel 20b in the third column, and the pixel circuit in the second sub-pixel 20b in the fifth column in the main display area 120 may be disposed only in the main display area 120.
In this case, in the foregoing plurality of setting manners, the PPI of the auxiliary display area 110 may be less than the PPI of the main display area 120. For ease of description, the following uses the structure shown in FIG. 12b as an example for description.
When the display 10 displays a picture, luminance S1_a of a single pixel 02 in the auxiliary display area 110 is directly proportional to a ratio of luminance S1 of the auxiliary display area 110 to an opening rate A_a of the auxiliary display area 110. In other words, S1_a ∝ (S1/A_a).
Luminance S2_b of a single pixel 02 in the main display area 120 is directly proportional to a ratio of luminance S2 of the main display area 120 to an opening rate A_b of the main display area 120. In other words, S2_b ∝ (S2/A_b).
The opening rate is a ratio of an area of a light emitting area of a sub-pixel to an area of the sub-pixel.
Based on this, in a manufacturing process, it is set that an area of a light emitting area of the first sub-pixel 20a in the auxiliary display area 110 is the same as an area of a light emitting area of the second sub-pixel 20b in the main display area 120. It can be learned from the foregoing description that an area of the first sub-pixel 20a in the auxiliary display area 110 is greater than an area of the second sub-pixel 20b in the main display area 120. Therefore, the opening rate A_a of the auxiliary display area 110 is less than A_b of the main display area 120.
In this case, when the auxiliary display area 110 and the main display area 120 display a same gray-scale picture, for example, a gray-scale picture of G255, the luminance S1 of the auxiliary display area 110 needs to be the same as the luminance S2 of the main display area 120. Therefore, it can be learned from the foregoing relational expressions S1_a ∝ (S1/A_a) and S2_b ∝ (S2/A_b) that the luminance S1_a of the single pixel 02 in the auxiliary display area 110 is greater than the luminance S2_b of the single pixel 02 in the main display area 120. In other words, luminance of an OLED in any first sub-pixel 20a in the auxiliary display area 110 is greater than luminance of an OLED in any second sub-pixel 20b in the main display area 120.
It can be learned from the foregoing description that the luminance of the OLED is directly proportional to a current I_OLED (namely, the foregoing drive current I_ds) flowing through the OLED. The current I_OLED is proportional to a voltage difference V_OLED between an anode (a) of the OLED and a cathode (c).
In addition, a voltage difference between a voltage ELVDD and a voltage ELVSS in a pixel circuit in any first sub-pixel 20a in the auxiliary display area 110 may be ΔV₁ = ELVDD - ELVSS = V_sd1 + V_OLED = V_sd1 + V₁ obtained according to the foregoing formula (1).
In a pixel circuit in any second sub-pixel 20b in the main display area 120, a voltage difference between a voltage ELVDD and a voltage ELVSS is ΔV₀ = ELVDD - ELVSS = V_sd0 + V_OLED = V_sd0 + V₀.
In this case, as shown in FIG. 5a, the voltage difference V_OLED (V₁ shown in FIG. 5a) between the anode (a) and the cathode (c) of the OLED in the pixel circuit in the auxiliary display area 110 is greater than the voltage difference V_OLED (V₀ shown in FIG. 5a) between the anode (a) and the cathode (c) of the OLED in the pixel circuit in the main display area 120.
In addition, a source voltage V_sd1 of a driving transistor M4 in the pixel circuit 201 in the auxiliary display area 110 is greater than a source voltage V_sd0 of a driving transistor M4 in the pixel circuit 201 in the main display area 120.
Therefore, ΔV₁ is greater than ΔV₀.
In this case, when the pixel circuit 201 in the auxiliary display area 110 and the pixel circuit 201 in the main display area 120 share the voltage ELVDD and the voltage ELVSS, to meet a requirement that the auxiliary display area 110 needs higher luminance, the voltage ELVDD and the voltage ELVSS are applied to the pixel circuit in the main display area 120, and an actual source voltage V_sd of the driving transistor M4 is located near a point A2 of a characteristic curve S_120 shown in FIG. 5b.
However, in the pixel circuit 201 in the main display area 120, when the source voltage V_sd of the driving transistor M4 is located near a saturation point A1 (a junction point at which the characteristic curve of the transistor changes from a curved line to a straight line) of the characteristic curve S_120, the driving transistor M4 may be completely turned on, so that the main display area 120 displays the gray-scale picture of G255. Because a voltage at the point A2 is greater than a voltage at the saturation point A1, power waste is caused.
To resolve the foregoing problems, the embodiments of this application provide the following solutions.

Example 3

In this example, the first supply voltage V1 is greater than the second supply voltage V2, and the third supply voltage V3 is also greater than the second supply voltage V2. In this case, the second supply voltage V2 may be the voltage ELVSS. In this case, the pixel circuit 102 in the auxiliary display area 110 and the pixel circuit 102 in the main display area 120 share the voltage ELVSS.
The first supply voltage V1 is greater than the third supply voltage V3.
For example, in an example in which both the auxiliary display area 110 and the main display area 120 display the gray-scale image of G255, the first supply voltage V1 may be approximately 5.6 V. In this case, in the pixel circuit 201 in the auxiliary display area 110, a source voltage V_sd of a first driving transistor M4a is located at a saturation point C1 (as shown in FIG. 13c) of a characteristic curve of the driving transistor M4a.
The third supply voltage V3 may be approximately 4.6 V. In this case, in the pixel circuit 201 in the main display area 120, the source voltage V_sd of the second driving transistor M4b is located at a saturation point C2 (as shown in FIG. 13c) of a characteristic curve of the driving transistor M4b.
In this case, the display drive circuit 03 includes a power management integrated circuit (Power Management IC, PMIC) 30 shown in FIG. 13a. The PMIC 30 includes a first voltage end B1, a second voltage end B2, and a third voltage end B3.
The first voltage end B1 of the PMIC 30 serves as the first signal end 113 of the display driver 03.
The second voltage end B2 of the PMIC 30 serves as the second signal end 123 of the display driver 03.
The third voltage end B3 of the PMIC 30 serves as the third signal end 133 of the display driver 03.
Based on this, it can be learned from the equivalent circuit diagram of the pixel circuit 201 shown in FIG. 4 that, as shown in FIG. 13a, in the pixel circuit 201 in the auxiliary display area 110, a first electrode (a source s) of the first driving transistor M4a serves as the first voltage input end 112 of the pixel circuit 201 in the first sub-pixel 20a, and is electrically connected to the first voltage end B1 of the PMIC 30. The first voltage end B1 of the PMIC 30 provides the first supply voltage V1 to the first electrode (the source s) of the first driving transistor M4a.
In addition, a second electrode (a drain d) of the first driving transistor M4a is electrically connected to an anode (a) of a first light emitting device D1 in the first sub-pixel 20a.
A cathode (c) of the first light emitting device D1 serves as the second voltage input end 122 of the pixel circuit 201 in the first sub-pixel 20a, and is electrically connected to the second voltage end B2 of the PMIC 30. The second voltage end B2 of the PMIC 30 provides the second supply voltage V2, namely, the voltage ELVSS, to the cathode (c) of the first light emitting device D1.
Likewise, it can be learned from the equivalent circuit diagram of the pixel circuit 201 shown in FIG. 4 that, as shown in FIG. 13a, a first electrode (a source s) of the second driving transistor M4b in the main display area 120 serves as the third voltage input end 132 of the pixel circuit 201 in the second sub-pixel 20b, and is electrically connected to the third voltage end B3 of the PMIC 30. The third voltage end B3 of the PMIC 30 provides the third supply voltage V3 to the first electrode (the source s) of the second driving transistor M4b.
In addition, a second electrode (a drain d) of the second driving transistor M4b is electrically connected to an anode (a) of a second light emitting device D2 in the second sub-pixel 20b.
A cathode (c) of the second light emitting device D2 serves as the fourth voltage input end 142 of the pixel circuit 201 in the second sub-pixel 20b, and is electrically connected to the second voltage end B2 of the PMIC 30. The second voltage end B2 of the PMIC 30 provides the second supply voltage V2, namely, the voltage ELVSS, to the cathode (c) of the second light emitting device D2. In this way, the first sub-pixel 20a and the second sub-pixel 20b can share the ELVSS.
It should be noted that, it can be learned from the foregoing description that the pixel circuit 201 in the auxiliary display area 110 and the pixel circuit 201 in the main display area 120 share the second supply voltage V2, namely, the voltage ELVSS, output by the second voltage end B2 of the PMIC 30. In this case, a current sink (current sink) capability of the second voltage end B2 of the PMIC 30 is a sum of a current I_B1 provided by the first voltage end B1 of the PMIC 30 and a current I_B2 provided by the third voltage end B3.
For example, the first voltage supply voltage V1 provided by the first voltage end B1 of the PMIC 30 to the pixel circuit 201 in the auxiliary display area 110 is 5.6 V, and the provided current is I_B1 = 400 mA.
The third voltage supply voltage V3 provided by the third voltage end B3 of the PMIC 30 to the pixel circuit 201 in the main display area 120 is 4.6 V, and the provided current is I_B2 = 50 mA
In this case, the current sink capability of the second voltage end B2 of the PMIC 30 is greater than or equal to I_B1 + I_B2 = 400 mA + 50 mA = 450 mA.

Example 4

In this example, the first supply voltage V1 is greater than the second supply voltage V2, and the third supply voltage V3 is also greater than the second supply voltage V2. In this case, the second supply voltage V2 may be the voltage ELVSS. In this case, the pixel circuit 102 in the auxiliary display area 110 and the pixel circuit 102 in the main display area 120 share the voltage ELVSS.
The first supply voltage V1 is greater than the third supply voltage V3.
A difference from Example 3 lies in that the display drive circuit 03 includes two PMICs 30 shown in FIG. 13b: a first PMIC 30_a and a second PMIC 30_b.
The first PMIC 30_a includes a first voltage end B1 and a second voltage end B2.
The second PMIC 30_a includes a third voltage end B3 and a fourth voltage end B4.
The first voltage end B1 of the first PMIC 30_a serves as the first signal end 113 of the display driver 03.
The third voltage end B3 of the second PMIC 30_b serves as the third signal end 133 of the display driver 03.
The second voltage end B2 of the first PMIC 30_a serves as the second signal end 123 of the display driver 03.
Alternatively, the fourth voltage end B4 of the second PMIC 30_b serves as the second signal end 123 of the display driver 03.
Based on this, likewise, it can be learned from the equivalent circuit diagram of the pixel circuit 201 shown in FIG. 4 that, as shown in FIG. 13b, in each pixel circuit 201 in the auxiliary display area 110, the first electrode (the source s) of the first driving transistor M4a serves as the first voltage input end 112 of the pixel circuit 201 in the first sub-pixel 20a, and is electrically connected to the first voltage end B1 of the first PMIC 30_a. The first voltage end B1 of the first PMIC 30_a provides the first supply voltage V1 to the first electrode (the source s) of the first driving transistor M4a.
In addition, the second electrode (the drain d) of the first driving transistor M4a is electrically connected to the anode (a) of the first light emitting device D1 in the first sub-pixel 20a.
The cathode (c) of the first light emitting device D1 serves as the second voltage input end 122 of the pixel circuit 201 in the first sub-pixel 20a, and is electrically connected to the second voltage end B2 of the first PMIC 30_a. The second voltage end B2 of the first PMIC 30_a provides the second supply voltage V2, namely, the voltage ELVSS, to the cathode (c) of the first light emitting device D1.
Likewise, it can be learned from the equivalent circuit diagram of the pixel circuit 201 shown in FIG. 4 that, as shown in FIG. 13b, a first electrode (a source s) of the second driving transistor M4b in the main display area 120 serves as the third voltage input end 132 of the pixel circuit 201 in the second sub-pixel 20b, and is electrically connected to the third voltage end B3 of the second PMIC 30_b. The third voltage end B3 of second the PMIC 30_b provides the third supply voltage V3 to the first electrode (the source s) of the second driving transistor M4b.
In addition, a second electrode (a drain d) of the second driving transistor M4b is electrically connected to an anode (a) of a second light emitting device D2 in the second sub-pixel 20b.
A cathode (c) of the second light emitting device D2 serves as the fourth voltage input end 142 of the pixel circuit 201 in the second sub-pixel 20b, and is electrically connected to the second voltage end B2 of the first PMIC 30_a. The second voltage end B2 of the first PMIC 30_a provides the second supply voltage V2, namely, the voltage ELVSS, to the cathode (c) of the second light emitting device D2, so that the first sub-pixel 20a and the second sub-pixel 20b share the ELVSS. In this case, the fourth voltage end B4 of the second PMIC 30_b is vacant.
Alternatively, both the cathode (c) of the first light emitting device D1 and the cathode (c) of the second light emitting device D2 are electrically connected to the fourth voltage end B4 of the second PMIC 30_b. The fourth voltage end B4 of the second PMIC 30_b provides the second supply voltage V2, namely, the voltage ELVSS, to the cathode (c) of the first light emitting device D1 and the cathode (c) of the second light emitting device D2. In this case, the second voltage end B2 of the first PMIC 30_a is vacant.
It should be noted that, it can be learned from the foregoing description that the pixel circuit 201 in the auxiliary display area 110 and the pixel circuit 201 in the main display area 120 share the second voltage end B2 of the first PMIC 30_a or the fourth voltage end B4 of the second PMIC 30_a. In this case, the current sink capability of the second voltage end B2 of the first PMIC 30_a or the fourth voltage end B4 of the second PMIC 30_a is a sum of the current I_B1 provided by the first voltage end B1 of the first PMIC 30_a and a current I_B3 provided by the third voltage end B3 of the second PMIC 30_a.
For example, the first voltage supply voltage V1 provided by the first voltage end B1 of the first PMIC 30_a to the pixel circuit 201 in the auxiliary display area 110 is 5.6 V, and the provided current is I_B1 = 400 mA.
The third voltage supply voltage V3 provided by the third voltage end B3 of the second PMIC 30_a to the pixel circuit 201 in the main display area 120 is 4.6 V, and the provided current is I_B3 = 50 mA.
In this case, the current sink capability of the second voltage end B2 of the first PMIC 30_a or the fourth voltage end B4 of the second PMIC 30_a is greater than or equal to I_B1 + I_B3 = 400 mA + 50 mA = 450 mA.
In conclusion, in Example 3 and Example 4, the first supply voltage V1 is provided to the pixel circuit 201 in the auxiliary display area 110. The third supply voltage V3 is provided to the pixel circuit 201 in the main display area 120. The first supply voltage V1 is greater than the third supply voltage V3.
In this way, when both the auxiliary display area 110 and the main display area 120 display the gray-scale picture of G255, in the pixel circuit 201 in the auxiliary display area 110, under an action of the first supply voltage V1, the actual source voltage V_sd of the first driving transistor M4a is located near the saturation point C1 of the characteristic curve S_110 shown in FIG. 13c.
In addition, in the pixel circuit 201 in the main display area 120, under an action of the third supply voltage V3, the actual source voltage V_sd of the second driving transistor M4b is located near the saturation point C2 of the characteristic curve S_120 shown in FIG. 13c.
In this case, when the display 10 displays a picture, both the source voltage V_sd of the first driving transistor M4a in the pixel circuit 201 in the auxiliary display area 110 and the source voltage V_sd of the second driving transistor M4b in the pixel circuit 201 in the main display area 120 are located near the saturation point. In addition, the first driving transistor M4a and the second driving transistor M4b are exactly in a completely on-state. Therefore, there is no need to provide a higher voltage to completely turn on the first driving transistor M4a and the second driving transistor M4b, so as to reduce power consumption.

Example 5

In this example, the first supply voltage V1 is less than the second supply voltage V2, and the third supply voltage V3 is also less than the second supply voltage V2. In this case, the second supply voltage V2 may be the voltage ELVDD. In this case, the pixel circuit 102 in the auxiliary display area 110 and the pixel circuit 102 in the main display area 120 share the voltage ELVDD.
The first supply voltage V1 is less than the third supply voltage V3.
In this case, the display drive circuit 03 includes a PMIC 30 shown in FIG. 14a. The PMIC 30 includes a first voltage end B1, a second voltage end B2, and a third voltage end B3.
The first voltage end B1 of the PMIC 30 serves as the first signal end 113 of the display driver 03.
The second voltage end B2 of the PMIC 30 serves as the second signal end 123 of the display driver 03.
The third voltage end B3 of the PMIC 30 serves as the third signal end 133 of the display driver 03.
Based on this, it can be learned from the equivalent circuit diagram of the pixel circuit 201 shown in FIG. 4 that, as shown in FIG. 14a, in the auxiliary display area 110, the first electrode (the source s) of the first driving transistor M4a serves as the second voltage input end 122 of the pixel circuit 201 in the first sub-pixel 20a, and is electrically connected to the second voltage end B2 of the PMIC 30. The second voltage end B2 of the PMIC 30 is configured to provide the second supply voltage V2, namely, the ELVDD, to the first electrode (the source s) of the first driving transistor M4a.
In addition, the second electrode (the drain s) of the first driving transistor M4a is electrically connected to the anode (a) of the first light emitting device D1.
The cathode (c) of the first light emitting device D1 serves as the first voltage input end 112 of the pixel circuit 201 in the first sub-pixel 20a, and is electrically connected to the first voltage end B1 of the PMIC 30. The first voltage end B1 of the PMIC 30 is configured to provide the first supply voltage V1 to the cathode (c) of the first light emitting device D1.
In addition, it can be learned from the equivalent circuit diagram of the pixel circuit 201 shown in FIG. 4 that, as shown in FIG. 14a, in the main display area 120, the first electrode (the source s) of the second driving transistor M4b serves as the fourth voltage input end 142 of the pixel circuit 201 in the second sub-pixel 20b, and is electrically connected to the second voltage end B2 of the PMIC 30. The second end B of the PMIC 30 is configured to provide the second supply voltage V2, namely, the ELVDD, to the first electrode (the source s) of the second driving transistor M4b.
In addition, the second electrode of the second driving transistor M4b is electrically connected to the anode (a) of the second light emitting device D2.
The cathode (c) of the second light emitting device D2 serves as the third voltage input end 132 of the pixel circuit 201 in the second sub-pixel 20b, and is electrically connected to the third voltage end B3 of the PMIC 30. The third end B of the PMIC 30 provides the third supply voltage V3 to the cathode (c) of the second light emitting device D2.
Likewise, it can be learned that the current sink capability of the first voltage end B1 of the PMIC 30 and the current sink capability of the third voltage end B3 of the PMIC 30 are greater than the current provided by the second voltage end B2 of the PMIC 30.

Example 6

In this example, the first supply voltage V1 is less than the second supply voltage V2, and the third supply voltage V3 is also less than the second supply voltage V2. In this case, the second supply voltage V2 may be the voltage ELVDD. In this case, the pixel circuit 102 in the auxiliary display area 110 and the pixel circuit 102 in the main display area 120 share the voltage ELVDD.
The first supply voltage V1 is less than the third supply voltage V3.
A difference from Example 5 lies in that the display drive circuit 03 includes two PMICs 30 shown in FIG. 14b: a first PMIC 30_a and a second PMIC 30_b.
The first PMIC 30_a includes a first voltage end B1 and a second voltage end B2.
The second PMIC 30_a includes a third voltage end B3 and a fourth voltage end B4.
The first voltage end B1 of the first PMIC 30_a serves as the first signal end 113 of the display driver 03.
The third voltage end B3 of the second PMIC 30_b serves as the third signal end 133 of the display driver 03.
The second voltage end B2 of the first PMIC 30_a serves as the second signal end 123 of the display driver 03.
Alternatively, the fourth voltage end B4 of the second PMIC 30_b serves as the second signal end 123 of the display driver 03.
Based on this, likewise, it can be learned from the equivalent circuit diagram of the pixel circuit 201 shown in FIG. 4 that, as shown in FIG. 14b, in each pixel circuit 201 in the auxiliary display area 110, the first electrode (the source s) of the first driving transistor M4a serves as the second voltage input end 122 of the pixel circuit 201 in the first sub-pixel 20a, and is electrically connected to the second voltage end B2 of the first PMIC 30_a.
The second voltage end B2 of the first PMIC 30_a provides the second supply voltage V2, namely, the ELVDD, to the first electrode (the source s) of the first driving transistor M4a.
In addition, the second electrode (the drain d) of the first driving transistor M4a is electrically connected to the anode (a) of the first light emitting device D1 in the first sub-pixel 20a.
The cathode (c) of the first light emitting device D1 serves as the first voltage input end 112 of the pixel circuit 201 in the first sub-pixel 20a, and is electrically connected to the first voltage end B1 of the first PMIC 30_a. The first voltage end B1 of the first PMIC 30_a provides the first supply voltage V1 to the cathode (c) of the first light emitting device D1.
Likewise, it can be learned from the equivalent circuit diagram of the pixel circuit 201 shown in FIG. 4 that, as shown in FIG. 14b, in the main display area 120, the first electrode (the source s) of the second driving transistor M4b serves as the fourth voltage input end 142 of the pixel circuit 201 in the second sub-pixel 20b, and is electrically connected to the second voltage end B2 of the first PMIC30_a.
The second voltage end B2 of the first PMIC 30_a provides the second supply voltage V2, namely, the ELVDD, to the first electrode (the source s) of the second driving transistor M4b. In this way, the first sub-pixel 20a and the second sub-pixel 20b share the ELVDD. In this case, the fourth voltage end B4 of the second PMIC 30_b is vacant.
In addition, a second electrode (a drain d) of the second driving transistor M4b is electrically connected to an anode (a) of a second light emitting device D2 in the second sub-pixel 20b.
The cathode (c) of the second light emitting device D2 serves as the third voltage input end 132 of the pixel circuit 201 in the second sub-pixel 20b, and is electrically connected to the third voltage end B3 of the second PMIC 30_b. The third voltage end B3 of the second PMIC 30_b provides the third supply voltage V3, namely, the voltage ELVSS, to the cathode (c) of the second light emitting device D2.
Alternatively, the first electrode (the source s) of the first driving transistor M4a and the first electrode (the source s) of the second driving transistor M4b may be electrically connected to the fourth voltage end B4 of the second PMIC 30_b. The fourth voltage end B4 of the second PMIC 30_b provides the third supply voltage V3, namely, the voltage ELVSS, to the first electrode (the source s) of the first driving transistor M4a and the first electrode (the source s) of the second driving transistor M4b. In this case, the second voltage end B2 of the first PMIC 30_a is vacant.
Likewise, it can be learned that the current sink capability of the first voltage end B1 of the first PMIC 30_a and the third voltage end B3 of the second PMIC 30_a is greater than the current provided by the second voltage end B2 of the first PMIC 30_a or the second voltage end B2 of the second PMIC 30_a.
It can be learned from Example 5 and Example 6 that, in the auxiliary display area 110, a same voltage is applied to cathodes of light emitting devices, for example, OLEDs. In the main display area 120, a same voltage needs to be applied to cathodes of all OLEDs. In addition, the voltage applied to a cathode of any OLED in the auxiliary display area 110 is different from the voltage applied to a cathode of any OLED in the main display area 120.
In this case, a structure of the display 10 is shown in FIG. 15, and the display 10 includes a cathode layer 300. The cathode layer 300 is disposed in the AA area 100. The cathode layer 300 includes a first electrode block 301 located in the auxiliary display area 110 and a second electrode block 302 located in the main display area 120.
As shown in FIG. 16, the first electrode block 301 serves as a cathode 24 of each OLED in the auxiliary display area 110. The second electrode block 302 serves as a cathode 24 of each OLED in the main display area 120.
In this case, when a PMIC power supply manner described in Example 5 is used, as shown in FIG. 15, the first electrode block 301 is electrically connected to the first voltage end B1 of the PMIC 30, to receive the first supply voltage V1 provided by the first voltage end B1 of the PMIC 30.
The second electrode block 302 is electrically connected to the third voltage end B3 of the PMIC 30, to receive the third supply voltage V3 provided by the third voltage end B3 of the PMIC 30.
To implement independent power supply for the first electrode block 301 and the second electrode block 302, as shown in FIG. 16, there is a gap H between the first electrode block 301 and the second electrode block 302. When the display 10 is manufactured, if manufacturing precision permits, a size of the gap H may be maximally reduced. This may avoid a case in which the sub-pixel 20 having an OLED cannot perform displaying because the cathode 24 cannot be disposed for the OLED located in the gap H.
As shown in FIG. 1, the display 10 includes a thin film transistor (thin film transistor, TFT) backplane 400. A plurality of transistors, that is, TFTs, in the pixel circuit 201 are formed on the TFT backplane 400.
In addition, the display 10 further includes a pixel define layer (pixel define layer, PDL) 21 located above the TFT backplane 400 and a plurality of OLEDs.
A plurality of through holes are disposed on the pixel define layer 21, and one through hole is disposed in each sub-pixel 20. The through hole is filled with an anode (anode) 22 of the OLED and an organic function layer 23. Along a direction away from the anode 22, the organic function layer 23 may sequentially include a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and an electron injection layer.
In addition, in the auxiliary display area 110, the cathodes 24 of OLEDs are connected to each other to become an integrated structure and form the first electrode block 301. In the main display area 120, the cathodes 24 of OLEDs are connected to each other to become an integrated structure and form the second electrode block 302.

Embodiment 2

In this embodiment, the mobile terminal 01 having the display 10, for example, the mobile phone, may be divided into at least two display subareas.
As shown in FIG. 17, the AA area 100 of the display 10 may be divided into a display subarea A, a display subarea B, and a display subarea C.
In some embodiments of this application, as shown in FIG. 18a, the display subarea C may be bent to a back side (namely, a non-display side) of the display 10. In this case, as shown in FIG. 18b, a user only needs to view images displayed in the display subarea A and the display subarea B.
In this case, because the user does not need to watch the display subarea C, display luminance of the display subarea C may be decreased. In other words, luminance of an OLED in each pixel circuit 20 in the display subarea C may be decreased.
Alternatively, as shown in FIG. 19, when the display subarea A is bent to the back side of the display 10, luminance of an OLED in each pixel circuit 20 in the display subarea A may be decreased.
Alternatively, as shown in FIG. 20, when both the display subarea A and the display subarea C are bent to the back side of the display 10, the luminance of the OLED in each pixel circuit 20 in the display subarea A and the luminance of the OLED in each pixel circuit 20 in the display subarea C may be decreased.
In this way, area-based luminance control is performed on each display subarea, so that luminance of the display subarea that does not need to be watched by the user is decreased, so as to reduce power consumption.
Based on this, to perform area-based luminance control on each display subarea in the display 10, as shown in FIG. 21a, the display 10 includes at least one PMIC 30 and a processor 31 that is electrically connected to the PMIC 30. In FIG. 21a, an example in which the display 10 has one PMIC 30 is used for description.
As shown in FIG. 21a, an active area 100 has 1080 rows of sub-pixels 20 in a horizontal direction X and has 1920 columns of sub-pixels in a vertical direction Y.
In this case, a display subarea A includes sub-pixels 20 in a column 1 to a column 640 in the vertical direction Y. A display subarea B includes sub-pixels 20 in a column 641 to a column 1280 in the vertical direction Y. A display subarea C includes sub-pixels 20 in a column 1281 to a column 1920 in the vertical direction Y.
The display subarea A, the display subarea B, and the display subarea C each have 1080 rows of sub-pixels in the horizontal direction X. For ease of description, as shown in FIG. 21b, a sub-pixel in the display subarea A is referred to as a first sub-pixel 20a, and a plurality of first sub-pixels 20a form a first pixel array. A sub-pixel in the display subarea B is referred to as a second sub-pixel 20b, and a plurality of second sub-pixels 20b form a second sub-pixel array. A sub-pixel in the display subarea C is referred to as a third sub-pixel 20c, and a plurality of third sub-pixels 20c form a third sub-pixel array.
The PMIC 30 has a first voltage end B1, a second voltage end B2, a third voltage end B3, and a fourth voltage end B4.
As shown in FIG. 21b, in each pixel circuit 201 in the display subarea A, a first driving transistor M4a is electrically connected to the first voltage end B1 of the PMIC 30.
The first voltage end B1 of the PMIC 30 is configured to separately provide the first supply voltage V1 to each pixel circuit 201 in the display subarea A.
In each pixel circuit 201 in the display subarea B, a second driving transistor M4b is electrically connected to the third voltage end B3 of the PMIC 30.
The third voltage end B2 of the PMIC 30 is configured to separately provide the third supply voltage V3 to each pixel circuit 201 in the display subarea B.
In each pixel circuit 201 in the display subarea C, a third driving transistor M4c is electrically connected to the fourth voltage end B4 of the PMIC 30.
The fourth voltage end B4 of the PMIC 30 is configured to separately provide a fourth supply voltage V4 to each pixel circuit 201 in the display subarea C.
In addition, cathodes (c) of a first light emitting device D1 in the display subarea A, a second light emitting device D2 in the display subarea B, and a third light emitting device D3 in the display subarea C are electrically connected to the fourth voltage end B4 of the PMIC 30.
The second voltage end B2 of the PMIC 30 is configured to provide the second supply voltage V2, namely, the ELVSS, to the cathodes (c) of the first light emitting device D1 in the display subarea A, the second light emitting device D2 in the display subarea B, and the first light emitting device D1 in the display subarea C at the same time. In this way, the pixel circuits in the display subarea A, the display subarea B, and the display subarea C can share the voltage ELVSS.
The first supply voltage V1, the third supply voltage V3, and the fourth supply voltage V4 have different voltage values. In addition, V1 is greater than V2, V3 is greater than V2, and V4 is greater than V2.
As described above, a current sink capability of the second voltage terminal B2 of the PMIC 30 is greater than or equal to a sum of currents output by the first voltage terminal B1 of the PMIC 30, the third voltage terminal B3 of the PMIC 30, and the fourth voltage terminal B4 of the PMIC 30.
On this basis, based on a structure in FIG. 21b, the display 01 further includes an underlying substrate. The first pixel array in the display subarea A, the second pixel array in the display subarea B, and the third pixel array in the display subarea C are disposed on the underlying substrate. In addition, a material constituting the underlying substrate includes a flexible resin material.
Based on this, this application provides a method for controlling a mobile terminal having the display shown in FIG. 21b, including:
First, the display driver 03 detects that the display subarea A having the first sub-pixel array is bent to the non-display side of the display 01.
Specifically, the display driver 03 includes the processor 31 connected to the PMIC 30 shown in FIG. 21a. The processor 31 is configured to detect whether each display subarea is bent to the back side of the display 10, and send a luminance control signal to the PMIC 30 based on a detection result.
Next, the foregoing method further includes: The first signal end 113 of the display driver 03, namely, the first voltage end B1 of the PMIC 30, decreases the first supply voltage V1 that is input to the first voltage input end 112 (namely, a first electrode of the first driving transistor M4a) of the pixel circuit in the first sub-pixel 20a in the display subarea A having the first sub-pixel array.
Alternatively, the second signal end 123 of the display driver 03, namely, the second voltage end B2 of the PMIC 30, increases the second supply voltage V2 that is input to the second voltage input end 122 (namely, the cathode of the first light emitting device D1) of the pixel circuit in the first sub-pixel 20a, to decrease luminance of the first sub-pixel 20a.
Specifically, when detecting that the display subarea A having the first sub-pixel array is bent to the back side of the display 10, the processor 31 sends the luminance control signal to the PMIC 30. The PMIC 30 may decrease, based on the luminance control signal, the first supply voltage V1 that is input to the first voltage end B1 of the PMIC 30, or increase the first supply voltage V1 that is input to the second voltage end B2 of the PMIC 30, to decrease luminance of the display subarea A.
The foregoing is described by using an example in which the display subarea A is bent to the back side of the display 10. When the processor 31 detects that another display subarea is bent to the back side of the display 10, a manner of decreasing luminance of the another display subarea may be similar. Details are not described herein again.
Based on this, to enable the processor 31 to detect whether each display subarea is bent to the back side of the display 10, in some embodiments of this application, a compressive resistor (not shown in the figure) may be disposed on the flexible substrate of the display 10 and at a junction position between two adjacent display subareas, for example, the display subarea B and the display subarea C.
The compressive resistor is connected to the processor 31. After the display subarea A is bent to the back side of the display 10, a resistance of the compressive resistor changes because the compressive resistor is pressed. The processor 31 may send a luminance control signal to the PMIC 30 based on a detected change in a resistance value of the compressive resistor.
Alternatively, in some other embodiments of this application, to perform area-based luminance control on each display subarea in the display 10, the display 10, as shown in FIG. 22a, includes three PMICs, for example, a first PMIC 30_a, a second PMIC 30_b, and a third PMIC 30_c. In addition, the display 10 further includes a processor 31 that is electrically connected to the foregoing three PMICs.
The first PMIC 30_a has a first voltage end B1 and a second voltage end B2.
The second PMIC 30_b has a third voltage end B3 and a fourth voltage end B4.
The third PMIC 30_c has a fifth voltage end B5 and a sixth voltage end B6.
As shown in FIG. 22b, in each pixel circuit 201 in a display subarea A, a first electrode (a source s) of a first driving transistor M4a is electrically connected to the first voltage end B1 of the first PMIC 30_a.
The first voltage end B1 of the first PMIC 30_a is configured to separately provide the first supply voltage V1 to each pixel circuit 201 in the display subarea A.
In each pixel circuit 201 in a display subarea B, a first electrode (a source s) of a second driving transistor M4b is electrically connected to the third voltage end B3 of the second PMIC 30_b.
The third voltage end B3 of the second PMIC 30_b is configured to separately provide the third supply voltage V3 to each pixel circuit 201 in the display subarea B.
In each pixel circuit 201 in the display subarea C, a first electrode (a source s) of a third driving transistor M4c is electrically connected to the fifth voltage end B5 of the third PMIC 30_c.
The fifth voltage end B5 of the third PMIC 30_c is configured to separately provide a fifth supply voltage V5 to each pixel circuit 201 in the display subarea C.
In addition, a cathode (c) of a first light emitting device D1 in the display subarea A, a cathode (c) of a second light emitting device D2 in the display subarea B, and a cathode (c) of a third light emitting device D3 in the display subarea C are electrically connected to the second voltage end B2 of the first PMIC 30_a. In this case, the fourth voltage end B4 of the second PMIC 30_b and the sixth voltage end B6 of the third PMIC 30_c are vacant.
The second voltage end B2 of the first PMIC 30_a is configured to provide a second supply voltage V2, namely, the voltage ELVSS, for cathodes of light emitting devices in the pixel circuits 201 in the display subarea A, the display subarea B, and the display subarea C at the same time. Therefore, the pixel circuits 201 in the display subarea A, the display subarea B, and the display subarea C share the voltage ELVSS.
The first supply voltage V1, the third supply voltage V3, and the fifth supply voltage V5 have different voltage values. In addition, V1 is greater than V2, V3 is greater than V2, and V5 is greater than V2.
As described above, a current sink capability of the second voltage end B2 of the first PMIC 30_a is greater than or equal to a sum of currents output by the first voltage end B1 of the first PMIC 30_a, the third voltage end B3 of the second PMIC 30_b, and the fifth voltage end B5 of the third PMIC 30_c.
Alternatively, in some other embodiments of this application, the cathode (c) of the first light emitting device D1 in the pixel circuit in the display subarea A, the cathode (c) of the second light emitting device D2 in the pixel circuit in the display subarea B, and the cathode (c) of the third light emitting device D3 in the pixel circuit in the display subarea C are electrically connected to the fourth voltage end B4 of the second PMIC 30_b or the sixth voltage end B6 of the third PMIC 30_c.
In this case, the fourth voltage end B4 or the sixth voltage end B6 of the third PMIC 30_c is configured to provide the voltage ELVSS to the cathodes of the light emitting devices in the pixel circuits 201 in the display subarea A, the display subarea B, and the display subarea C at the same time.
In this case, the processor 31 detects whether each display subarea is bent to the back side of the display 10. When detecting that a display subarea, for example, the display subarea C is bent to the back side of the display 10, the processor 31 sends a luminance control signal to the third PMIC 30_c.
The third PMIC 30_c decreases, based on the luminance control signal, the fifth supply voltage V5 output by the fifth voltage end B5 of the third PMIC 30_c. Therefore, luminance of the display subarea C is decreased.
The foregoing is described by using an example in which the display subarea C is bent to the back side of the display 10. When the processor 31 detects that another display subarea C is bent to the back side of the display 10, a manner of decreasing luminance of the another display subarea may be similar. Details are not described herein again.
It should be noted that the foregoing describes independent control of luminance in each display subarea by using an example in which the pixel circuits 201 in the display subarea A, the display subarea B, and the display subarea C receive the same voltage ELVSS. Certainly, to implement independent control of luminance in each display subarea, the pixel circuit 201 in each display subarea may alternatively receive a same voltage ELVDD. In this case, settings of the PMIC and a cathode layer 300 in the display 10 are the same as those in Embodiment 1. Details are not described herein again.

Embodiment 3

In this embodiment, the mobile terminal 01 having the display 10, for example, a mobile phone, may be divided into at least two display subareas.
As shown in FIG. 23, the AA area 100 of the display 10 may be divided into a display subarea A and a display subarea B. The display subarea A and the display subarea B display different content.
For example, in some embodiments of this disclosure, the display subarea B plays a movie.
When the mobile terminal 01 receives dialog information, for example, WeChat content, the display subarea A displays the dialog information. When the mobile terminal 01 does not receive the dialog information, a same image is displayed dividedly by both the display subarea A and the display subarea B.
In this case, the display subarea B which usually plays the movie has relatively low luminance. The display subarea A which displays the dialog information has relatively bright luminance. In this case, the dialog information displayed by the display subarea A is excessively dazzling. Consequently, movie watching experience of a user is reduced. In this case, the luminance of the display subarea A and the luminance of the display subarea B need to be separately controlled, to decrease the luminance of the display subarea A.
Based on this, to perform area-based luminance control on each display subarea in the display 10, as shown in FIG. 24, the display 10 includes at least one PMIC 30 and a processor 31 that is electrically connected to the PMIC 30. In FIG. 24, an example in which the display 10 has one PMIC 30 is used for description.
As shown in FIG. 24, an active area 100 has 1920 rows of sub-pixels 20 in a horizontal direction X and has 1080 columns of sub-pixels in a vertical direction Y.
In this case, the display subarea A includes sub-pixels 20 in a row 1 to a row 640 in the horizontal direction X. The display subarea B includes sub-pixels 20 in a row 641 to a row 1920 in the horizontal direction.
The display subarea A and the display subarea B each have 1080 columns of sub-pixels in the vertical direction Y.
The PMIC 30 has a first voltage end B1, a second voltage end B2, and a third voltage end B3.
Likewise, it can be learned from Embodiment 2 that, in each pixel circuit 201 in the display subarea A, a first electrode (a source s) of a first driving transistor M4a is electrically connected to the first voltage end B1 of the PMIC 30.
The first voltage end B1 of the PMIC 30 is configured to separately provide the first supply voltage V1 to each pixel circuit 201 in the display subarea A.
In each pixel circuit 201 in the display subarea B, a first electrode (a source s) of a second driving transistor M4a is electrically connected to the second voltage end B2 of the PMIC 30.
The third voltage end B3 of the PMIC 30 is configured to separately provide the third supply voltage V3 to each pixel circuit 201 in the display subarea B.
In addition, both a cathode (c) of a first light emitting device D1 in the pixel circuit 201 in the display subarea A and a cathode (c) of a second light emitting device D2 in the pixel circuit 201 in the display subarea B are electrically connected to the second voltage end B2 of the PMIC 30.
The second voltage end B2 of the PMIC 30 is configured to provide the second supply voltage V2, namely, the voltage ELVSS, to the pixel circuits 201 in the display subarea A and the display subarea B at the same time.
The first supply voltage V1 and the third supply voltage V3 have different voltage values. In addition, V1 is greater than V2, and V3 is greater than V2.
In addition, when the display has two PMICs, the two PMICs are respectively configured to provide different first supply voltages V1 and the third supply voltages V3 to the display subarea A and the display subarea B. Manners of setting the two PMIC are the same as the principle in Embodiment 2. Details are not described herein again.
On this basis, as shown in FIG. 24, the processor 31 is electrically connected to the PMIC. When detecting that the dialog information is displayed in the display subarea A and the movie is played in the display subarea B, the processor 31 sends a luminance control signal to the PMIC 30.
The PMIC 30 may decrease, based on the luminance control signal, the first supply voltage V1 output by the first voltage end B1 of the PMIC 30. Therefore, the luminance of the display subarea A is decreased. This prevents the dialog information displayed in the display subarea A from being excessively dazzling and affecting a display effect.
Alternatively, in some other embodiments of this application, the display subarea B displays a background image.
When the mobile terminal 01 receives the dialog information, the dialog information is displayed in the subarea A. When the mobile terminal 01 does not receive the dialog information, a same image is displayed in both the display subarea A and the display subarea B.
In this case, if the luminance of the display subarea B in which the background image is displayed is equivalent to the luminance of the display subarea A in which the dialog information is displayed, the user may ignore important information. In this case, the luminance of the display subarea A and the luminance of the display subarea B need to be separately controlled, so as to increase the luminance of the display subarea A.
Based on this, when detecting that the dialog information is displayed in the display subarea A and the background image is displayed in the display subarea B, the processor 31 sends the luminance control signal to the PMIC 30.
The PMIC 30 may increase, based on the luminance control signal, the first supply voltage V1 output by the first voltage end B1 of the PMIC 30. Therefore, the luminance of the display subarea A is increased. This prevents the dialog information displayed in subarea A from being ignored.
The foregoing descriptions are merely specific implementations of the present invention, but are not intended to limit the protection scope of the present invention. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the present invention shall fall within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

A display, wherein the display comprises a display driver, a first pixel array, and a second pixel array, wherein
the display driver comprises a first signal end, a second signal end, and a third signal end;

the first pixel array comprises a plurality of first sub-pixels, and a pixel circuit in the first sub-pixel comprises a first voltage input end and a second voltage input end;

the second pixel array comprises a plurality of second sub-pixels, and a pixel circuit in the second sub-pixel comprises a third voltage input end and a fourth voltage input end;

the first voltage input end of the pixel circuit in the first sub-pixel is electrically connected to the first signal end of the display driver, to receive a first supply voltage output by the first signal end, and the second voltage input end is electrically connected to the second signal end of the display driver, to receive a second supply voltage output by the second signal end;

the third voltage input end of the pixel circuit in the second sub-pixel is electrically connected to the third signal end of the display driver, to receive a third supply voltage output by the third signal end, and the fourth voltage input end is electrically connected to the second signal end of the display driver, to receive the second supply voltage output by the second signal end; and

a voltage value of the third supply voltage is different from a voltage value of the first supply voltage.
The display according to claim 1, wherein the first supply voltage output by the first signal end of the display driver is greater than the second supply voltage output by the second signal end of the display driver; and
the third supply voltage output by the third signal end of the display driver is greater than the second supply voltage output by the second signal end of the display driver.
The display according to claim 2, wherein the pixel circuit in the first sub-pixel in the first pixel array comprises a first driving transistor and a first light emitting device, wherein a first electrode of the first driving transistor is electrically connected to the first signal end of the display driver, a second electrode of the first driving transistor is electrically connected to an anode of the first light emitting device, and a cathode of the first light emitting device is electrically connected to the second signal end of the display driver; and
the second pixel array comprises a plurality of second sub-pixels, and the pixel circuit in the second sub-pixel comprises a second driving transistor and a second light emitting device, wherein

a first electrode of the second driving transistor is electrically connected to the third signal end of the display driver, a second electrode of the second driving transistor is electrically connected to an anode of the second light emitting device, and a cathode of the second light emitting device is electrically connected to the second signal end of the display driver.
The display according to claim 1, wherein the first supply voltage output by the first signal end of the display driver is less than the second supply voltage output by the second signal end of the display driver; and
the third supply voltage output by the third signal end of the display driver is less than the second supply voltage output by the second signal end of the display driver.
The display according to claim 4, wherein the pixel circuit in the first sub-pixel in the first pixel array comprises a first driving transistor and a first light emitting device, wherein
a first electrode of the first driving transistor is electrically connected to the second signal end of the display driver, a second electrode of the first driving transistor is electrically connected to an anode of the first light emitting device, and a cathode of the first light emitting device is electrically connected to the first signal end of the display driver; and

the second pixel array comprises the plurality of second sub-pixels, and the pixel circuit in the second sub-pixel comprises a second driving transistor and a second light emitting device, wherein

a first electrode of the second driving transistor is electrically connected to the second signal end of the display driver, a second electrode of the second driving transistor is electrically connected to an anode of the second light emitting device, and a cathode of the second light emitting device is electrically connected to the third signal end of the display driver.
The display according to claim 1, wherein the display driver comprises a power management integrated circuit, and the power management integrated circuit comprises a first voltage end, a second voltage end, and a third voltage end, wherein
the first voltage end of the power management integrated circuit is electrically connected to the first voltage input end of the pixel circuit in the first sub-pixel;

a second output end of the power management integrated circuit is electrically connected to the second voltage input end of the pixel circuit in the first sub-pixel and the fourth voltage input end of the pixel circuit in the second sub-pixel; and

a third output end of the power management integrated circuit is electrically connected to the third voltage input end of the pixel circuit in the second sub-pixel.
The display according to claim 1, wherein the display driver comprises a first power management integrated circuit and a second power management integrated circuit, wherein
the first power management integrated circuit comprises a first voltage end and a second voltage end;

the second power management integrated circuit comprises a third voltage end and a fourth voltage end;

the first voltage end of the first power management integrated circuit is electrically connected to the first voltage input end of the pixel circuit in the first sub-pixel;

the third voltage end of the second power management integrated circuit is electrically connected to the third voltage input end of the pixel circuit in the second sub-pixel; and

the second voltage end of the first power management integrated circuit is electrically connected to the second voltage input end of the pixel circuit in the first sub-pixel and the fourth voltage input end of the pixel circuit in the second sub-pixel; or

the fourth voltage end of the second power management integrated circuit is electrically connected to the second voltage input end of the pixel circuit in the first sub-pixel and the fourth voltage input end of the pixel circuit in the second sub-pixel.
The display according to any one of claims 1 to 7, wherein
the active area comprises an auxiliary display area and a main display area, and a non-display side of the auxiliary display area is configured to integrate a camera lens or a sensor;

the first pixel array is located in the auxiliary display area, and the second pixel array is located in the main display area; and

pixels per inch of the auxiliary display area are less than pixels per inch of the main display area.
The display according to claim 7, wherein a light non-transparent area occupied by the pixel circuit in the first sub-pixel is the same as a light non-transparent area occupied by the pixel circuit in the second sub-pixel; and
a light transparent area of the first sub-pixel other than the pixel circuit is greater than a light transparent area of the second sub-pixel other than the pixel circuit.
The display according to claim 6 or 7, wherein
the display further comprises an underlying substrate, and the first pixel array and the second pixel array are disposed on the underlying substrate;

a material constituting the underlying substrate comprises a flexible resin material; and

the display drive circuit further comprises a processor, the processor is electrically connected to at least one power management integrated circuit, and the processor is configured to: when detecting that the first pixel array or the second pixel array is bent to a non-display side of the display, output a luminance control signal to the at least one power management integrated circuit.
A mobile terminal, comprising the display according to any one of claims 1 to 10, wherein
the mobile terminal further comprises a camera lens and a sensor, and the camera lens and/or the sensor are/is located on a non-display side of the display.
The mobile terminal according to claim 11, wherein the display comprises an auxiliary display area and a main display area, and pixels per inch of the auxiliary display area are less than pixels per inch of the main display area; and
the camera lens and the sensor are disposed on a non-display side of the auxiliary display area.
The mobile terminal according to claim 11, wherein an opening is disposed on the display, and the display comprises auxiliary display areas located on two sides of the opening and a main display area located under the opening;
pixels per inch of the auxiliary display area are less than pixels per inch of the main display area; and

the camera lens is located in the opening, and the sensor is disposed on a non-display side of the auxiliary display area.
A mobile terminal control method, wherein the mobile terminal comprises a display, and the display comprises a display driver, a first pixel array, and a second pixel array, wherein the display driver comprises a first signal end, a second signal end, and a third signal end; the first pixel array comprises a plurality of first sub-pixels, and a pixel circuit in the first sub-pixel comprises a first voltage input end and a second voltage input end; the second pixel array comprises a plurality of second sub-pixels, and a pixel circuit in the second sub-pixel comprises a third voltage input end and a fourth voltage input end; the first voltage input end of the pixel circuit in the first sub-pixel is electrically connected to the first signal end of the display driver, and the second voltage input end is electrically connected to the second signal end of the display driver; and the third voltage input end of the pixel circuit in the second sub-pixel is electrically connected to the third signal end of the display driver, and the fourth voltage input end is electrically connected to the second signal end of the display driver;
the display further comprises an underlying substrate, the first pixel array and the second pixel array are disposed on the underlying substrate, and a material constituting the underlying substrate comprises a flexible resin material; and

the mobile terminal control method comprises the following steps:
detecting, by the display driver, that the first sub-pixel array is bent to a non-display side of the display; and

decreasing, by the first signal end of the display driver, a first supply voltage that is input to the first voltage input end of the pixel circuit in the first sub-pixel in the first sub-pixel array, or increasing, by the second signal end of the display driver, a second supply voltage that is output to the second voltage input end of the pixel circuit in the first sub-pixel, to decrease luminance of the first sub-pixel, wherein

the first supply voltage is greater than the second supply voltage.