CN105552073A - Chip layout structure and method for preventing latch up effects and noise interference - Google Patents
Chip layout structure and method for preventing latch up effects and noise interference Download PDFInfo
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- CN105552073A CN105552073A CN201510921612.9A CN201510921612A CN105552073A CN 105552073 A CN105552073 A CN 105552073A CN 201510921612 A CN201510921612 A CN 201510921612A CN 105552073 A CN105552073 A CN 105552073A
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000000694 effects Effects 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 16
- 238000002955 isolation Methods 0.000 abstract description 2
- 238000012913 prioritisation Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a chip layout structure and a method for preventing latch up effects and noise interference. Dual-ring protection is adopted, an analog module of the chip is wrapped by firstly using a P+ring (is grounded) and then using an N+ring (is connected with a power supply); a power module is protected by using the dual-ring structure which is the same as the analog module; and a digital module is wrapped by firstly using the N+ring (is connected with the power supply) and then using the P+ring (is grounded). A certain distance is kept between the analog module and the digital module for preventing the analog module from being disturbed by digital noise. An N+ (minority carrier) protection ring is added between the power module and other modules, the N+ring is connected with a ground potential, the concentration of a substrate close to the minority carrier ring is reduced, substrate resistance is added, the latch up effects can be prevented from happening to the chip, and noise of the digital module can be prevented from disturbing the power module. Effects of good anti-latch up effects and noise isolation can be generated, and the working performance of the chip is improved.
Description
Technical field
The present invention relates to a kind of the chip layout structure and the method that prevent latch-up latchup and noise jamming, belong to technical field of integrated circuits.
Background technology
Along with the development of IC manufacturing process, the size of chip is more and more less, chip package density and integrated level more and more higher, producing the possibility of latchup will be increasing, and the possibility interfered with each other between module also can be increasing.In general, the condition producing latchup is: loop current gain is greater than 1, β npn* β pnp >=1; Two BJT emitters are all in positively biased; One can be formed at emitter and maintain the large electric current of electric current than PNPN device.Power model owing to being big current in output stage, certain displacement current can be produced in the substrate near power device, this electric current flows through low-pressure section, dead resistance R2 just has drop of potential, as shown in (a) He (b) in Fig. 1, when this electromotive force reaches certain value, the horizontal triode Qn of this part parasitism will be made to open.Substrate current can amplify by the transistor opened, electric current on Qn pipe collector is flowed in trap, and opened by entozoic for trap longitudinal triode Qp again, latchup structure is triggered, once form this positive feedback path, the big current between power supply to ground can make the heating of monoblock chip lose efficacy.For overcoming this problem; people generally adopt and add the how sub-guard ring of majority carrier (this guard ring ground connection) in power models and other modules; increase the methods such as the distance of power model and other intermodules, as shown in Figure 2, but this method can increase chip area.For noise; mainly digital module and high-frequency model can produce noise jamming to analog module; for overcoming this problem; people generally adopt and add P+ and the how sub-guard ring of majority carrier (this guard ring ground connection) in digital modules and other modules; and the distance increased between digital module and other modules is to prevent noise jamming, does like this and also can increase chip area.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of the chip layout structure and the method that prevent latch-up and noise jamming; employing dicyclo is protected; and between power model and other modules, add N+ ring and minority carrier guard ring is kept apart; and this N+ articulating earth potential; substrate concentration near minority carrier subring is reduced; and increase resistance substrate, thus prevent from, in chip, latch-up occurs, and prevent the noise jamming of digital module to analog module and power model.
The present invention is for solving the problems of the technologies described above by the following technical solutions:
On the one hand; the invention provides a kind of chip layout structure preventing latch-up and noise jamming; described chip layout comprises analog module, power model, digital module; analog module, power model, digital module all adopt dicyclo operator guards; wherein; the dicyclo operator guards of analog module and power model is interior P+ ring, outer N+ ring, and the dicyclo operator guards of digital module is interior N+ ring, outer P+ ring, and keeps a determining deviation between analog module and digital module.
As further prioritization scheme of the present invention, described P+ articulating ground.
As further prioritization scheme of the present invention, described N+ articulating power supply.
As further prioritization scheme of the present invention, between described power model and all the other each modules, be also provided with N+ minority carrier guard ring, and this N+ minority carrier guard ring earthing potential.
On the other hand; the invention provides a kind of chip layout building method preventing latch-up and noise jamming; described chip layout comprises analog module, power model, digital module; the dicyclo protection of P+ ring, outer N+ ring in right analog module, power model adopt; the dicyclo protection of N+ ring, outer P+ ring in the digital module of chip is adopted, and between analog module and digital module, keep a determining deviation.
As further prioritization scheme of the present invention, the method also arranges N+ minority carrier guard ring between power model and all the other each modules, and this N+ minority carrier guard ring earthing potential.
As further prioritization scheme of the present invention, described P+ articulating ground.
As further prioritization scheme of the present invention, described N+ articulating power supply.
The present invention adopts above technical scheme compared with prior art, has following technique effect: the present invention adopts dicyclo to protect, and first uses P+ ring (ground connection) to wrap the analog module of chip, then uses N+ ring (connecing power supply) to wrap; Power model protects with the same twin nuclei of analog module; Digital module first uses N+ ring (connecing power supply) ring to wrap, and then uses P+ ring (ground connection) to wrap.A determining deviation is kept, to prevent digital noise interference simulation module between analog module and digital module.N+ minority carrier guard ring is added between power model and other modules; and this N+ articulating earth potential, makes the substrate concentration near minority carrier subring reduce, and increases resistance substrate; thus prevent from, in chip, latch-up occurs, and prevent the noise jamming of digital module to power model.This chip structure, primarily of analog module, power model and digital module composition.The present invention can produce effect and the noise isolation of good anti-latch-up, improves the service behaviour of chip.
Accompanying drawing explanation
Fig. 1 is generation structural representation and the circuit diagram of latchup, and wherein, (a) is structural representation, and (b) is circuit diagram.
Fig. 2 is the chip layout structural representation preventing latchup and noise jamming in general domain.
Fig. 3 is chip layout structural representation of the present invention.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail:
As shown in Figure 3, the invention provides a kind of chip layout structure preventing latch-up and noise jamming, described chip layout comprises analog module, power model, digital module, analog module, power model, digital module all adopts dicyclo operator guards, wherein, the dicyclo operator guards of analog module and power model is interior P+ ring (ground connection), outer N+ ring (connecing power supply), the dicyclo operator guards of digital module is interior N+ ring (connecing power supply), outer P+ ring (ground connection), and between analog module and digital module, keep a determining deviation, , to prevent digital noise interference simulation module.N+ minority carrier guard ring is also provided with between power model and all the other each modules; and this N+ minority carrier guard ring earthing potential; substrate concentration near minority carrier subring is reduced; and increase resistance substrate; thus prevent from, in chip, latch-up occurs, and prevent the noise jamming of digital module to power model.
Because minority carrier guard ring is exactly the collection carrying out electronics in advance, and the minority carrier guard ring degree of depth is comparatively dark, and effect is also suitable obvious, and it can reduce the current gain of parasitic horizontal triode Qn, i.e. β npn.
And majority carrier is corresponding, collect hole.But because being P type substrate, hole must enter into substrate, majority carrier guard ring reduces the resistance of local in essence.After having added minority carrier guard ring, P+ type majority carrier guard ring is close to nwell, and be more conducive to collect in advance, effect will be more obviously.
For analog module and power model, in adopting, the dicyclo protection of the outer N+ of P+, can effectively prevent external noise from disturbing; For digital module, in adopting, the dicyclo protection of the outer P+ of N+, effectively can absorb the noise that digital module inside produces.
N+ minority carrier guard ring is added between power model and other modules; substrate concentration near minority carrier subring is reduced; equally with distance method between increasing power module with other modules resistance substrate can be increased; serve the effect of anti-latchup, and the present invention does not increase chip area.As shown in Figure 3, N+ minority carrier articulating earth potential, can not only avoid the mutual interference between module further, and power model substrate current also can be avoided to flow to digital module power supply, do not affect the reliability of digital-to-analog circuit, the effect absorbing substrate current can be played simultaneously.
The above; be only the embodiment in the present invention; but protection scope of the present invention is not limited thereto; any people being familiar with this technology is in the technical scope disclosed by the present invention; the conversion or replacement expected can be understood; all should be encompassed in and of the present inventionly comprise within scope, therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (8)
1. one kind prevents the chip layout structure of latch-up and noise jamming; described chip layout comprises analog module, power model, digital module; it is characterized in that; analog module, power model, digital module all adopt dicyclo operator guards; wherein; the dicyclo operator guards of analog module and power model is interior P+ ring, outer N+ ring, and the dicyclo operator guards of digital module is interior N+ ring, outer P+ ring, and keeps a determining deviation between analog module and digital module.
2. a kind of chip layout structure preventing latch-up and noise jamming according to claim 1, is characterized in that, described P+ articulating ground.
3. a kind of chip layout structure preventing latch-up and noise jamming according to claim 1, is characterized in that, described N+ articulating power supply.
4. a kind of chip layout structure preventing latch-up and noise jamming according to claim 1; it is characterized in that; N+ minority carrier guard ring is also provided with between described power model and all the other each modules, and this N+ minority carrier guard ring earthing potential.
5. one kind prevents the chip layout building method of latch-up and noise jamming; described chip layout comprises analog module, power model, digital module; it is characterized in that; the dicyclo protection of P+ ring, outer N+ ring in analog module, power model are adopted; the dicyclo protection of N+ ring, outer P+ ring in the digital module of chip is adopted, and between analog module and digital module, keep a determining deviation.
6. a kind of chip layout building method preventing latch-up and noise jamming according to claim 1; it is characterized in that; the method also arranges N+ minority carrier guard ring between power model and all the other each modules, and this N+ minority carrier guard ring earthing potential.
7. a kind of chip layout building method preventing latch-up and noise jamming according to claim 1, is characterized in that, described P+ articulating ground.
8. a kind of chip layout building method preventing latch-up and noise jamming according to claim 1, is characterized in that, described N+ articulating power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510921612.9A CN105552073A (en) | 2015-12-14 | 2015-12-14 | Chip layout structure and method for preventing latch up effects and noise interference |
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| CN201510921612.9A CN105552073A (en) | 2015-12-14 | 2015-12-14 | Chip layout structure and method for preventing latch up effects and noise interference |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653748A (en) * | 2016-12-30 | 2017-05-10 | 合肥恒烁半导体有限公司 | Method for using integrated circuit corner |
| CN106783731A (en) * | 2016-12-30 | 2017-05-31 | 合肥恒烁半导体有限公司 | The method for lifting integrated circuit corner silicon chip service efficiency |
| CN110571217A (en) * | 2019-11-06 | 2019-12-13 | 南京华瑞微集成电路有限公司 | Integrated power device and manufacturing method thereof |
| CN114068517A (en) * | 2020-08-05 | 2022-02-18 | 圣邦微电子（北京）股份有限公司 | Semiconductor chip |
| CN115548118A (en) * | 2021-06-29 | 2022-12-30 | 苏州华太电子技术股份有限公司 | Isolation structure and isolation method of high-integration-level radio frequency front-end module |
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| US7167350B2 (en) * | 2003-11-14 | 2007-01-23 | Texas Instruments Incorporated | Design implementation to suppress latchup in voltage tolerant circuits |
| CN101022106A (en) * | 2006-02-15 | 2007-08-22 | 冲电气工业株式会社 | Semiconductor device |
| CN102130124A (en) * | 2010-12-24 | 2011-07-20 | 苏州华芯微电子股份有限公司 | Chip structure for preventing latch-up effect and method thereof |
| CN102903713A (en) * | 2011-07-29 | 2013-01-30 | 上海华虹Nec电子有限公司 | Protection ring structure for inhibiting latch-up effect and verification method thereof |
| CN203707130U (en) * | 2013-12-18 | 2014-07-09 | 湘潭大学 | A latch-up protection structure of an integrated circuit chip |
-
2015
- 2015-12-14 CN CN201510921612.9A patent/CN105552073A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7167350B2 (en) * | 2003-11-14 | 2007-01-23 | Texas Instruments Incorporated | Design implementation to suppress latchup in voltage tolerant circuits |
| CN101022106A (en) * | 2006-02-15 | 2007-08-22 | 冲电气工业株式会社 | Semiconductor device |
| CN102130124A (en) * | 2010-12-24 | 2011-07-20 | 苏州华芯微电子股份有限公司 | Chip structure for preventing latch-up effect and method thereof |
| CN102903713A (en) * | 2011-07-29 | 2013-01-30 | 上海华虹Nec电子有限公司 | Protection ring structure for inhibiting latch-up effect and verification method thereof |
| CN203707130U (en) * | 2013-12-18 | 2014-07-09 | 湘潭大学 | A latch-up protection structure of an integrated circuit chip |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653748A (en) * | 2016-12-30 | 2017-05-10 | 合肥恒烁半导体有限公司 | Method for using integrated circuit corner |
| CN106783731A (en) * | 2016-12-30 | 2017-05-31 | 合肥恒烁半导体有限公司 | The method for lifting integrated circuit corner silicon chip service efficiency |
| CN106653748B (en) * | 2016-12-30 | 2019-09-06 | 合肥恒烁半导体有限公司 | The application method in integrated circuit corner |
| CN110571217A (en) * | 2019-11-06 | 2019-12-13 | 南京华瑞微集成电路有限公司 | Integrated power device and manufacturing method thereof |
| CN114068517A (en) * | 2020-08-05 | 2022-02-18 | 圣邦微电子（北京）股份有限公司 | Semiconductor chip |
| CN115548118A (en) * | 2021-06-29 | 2022-12-30 | 苏州华太电子技术股份有限公司 | Isolation structure and isolation method of high-integration-level radio frequency front-end module |
| CN115548118B (en) * | 2021-06-29 | 2024-05-14 | 苏州华太电子技术股份有限公司 | Isolation structure and isolation method of high-integration radio frequency front end module |
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