CN105390490A - Electrostatic protection circuit and integrated circuit - Google Patents
Electrostatic protection circuit and integrated circuit Download PDFInfo
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- CN105390490A CN105390490A CN201510900703.4A CN201510900703A CN105390490A CN 105390490 A CN105390490 A CN 105390490A CN 201510900703 A CN201510900703 A CN 201510900703A CN 105390490 A CN105390490 A CN 105390490A
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- active area
- well region
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- substrate contact
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- 239000000758 substrate Substances 0.000 claims abstract description 67
- 230000001681 protective effect Effects 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000002347 injection Methods 0.000 abstract 2
- 239000007924 injection Substances 0.000 abstract 2
- 230000003071 parasitic effect Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000001960 triggered effect Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an electrostatic protection circuit. The electrostatic protection circuit comprises: a substrate; a well region consisting of a first well region and a second well region; an active region consisting of a first active region, a second active region and a third active region; a substrate contact region consisting of a first substrate contact region and a second substrate contact region; and a first gate consisting of a first gate oxide layer. According to the electrostatic protection circuit, a silicon-controlled-rectifier structure is realized by increasing the injection of N wells in the drain electrode of an NMOS transistor and by performing P+ injection in the N wells, in a GGNMOS structure; the connection between the second active region in the drain terminal of the NMOS transistor and input and output pins of a protected chip is removed; a buried layer is added for completely isolating a P well from the substrate; and the voltage drop on a device after an ESD access is trigged is lowered to further improve the discharge capability of the ESD device and to improve the anti-static level.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field in microelectronic, particularly a kind of electrostatic discharge protective circuit and integrated circuit.
Background technology
In a chip design, electrostatic defending is related to the reliability of chip is the problem that must solve; Along with electrostatic defending requires to improve, ESD (Electro-Staticdischarge) protection device to chip being responsible for static discharge is needed to continue to optimize.
ESD structure classical in prior art is grounded-grid or the grid large scale nmos device GGNMOS (Gate-groundedNMOS) by resistance R ground connection, when its principle is electrostatic generation, trigger parasitic NPN triode, the electrostatic big current of safe bleed off moment.G is for be connected with protected chip earth potential pin as shown in Figure 1 for its sectional view, and the input and output pin IO (Input-Output) of protected chip, IO are the pin of chip operating voltage higher than G.Grid passes through resistance R ground connection, P type substrate P-sub; P type trap zone is PWELL, and drain electrode N+ region is connected with pin IO, and the N+ region of grid, source electrode is connected with pin G with P+ region.
Fig. 2 is the equivalent circuit diagram of Fig. 1, show this structure when ESD triggers to release the path of ESD electric current, wherein Q1 is parasitic NPN triode, the N+ region of NMOS drain electrode is transistor collector, P trap is transistor base, the N+ region of nmos source is three machine pipe emitters, and it is R_PWELL that the path between the P+ that Q1 base stage is connected with G to P trap is equivalent to dead resistance.When ESD electric current comes interim, between Q1 collector electrode to base stage, the N+ region of the drain electrode of NMOS tube and the N+/PWELL junction breakdown of substrate PWELL, breakdown current flows to G through R_PWELL; Now accumulated voltage on dead resistance R_PWELL, when the base voltage of parasitic NPN triode is elevated, its collector electrode is triggered to the big current path of emitter, realizes releasing of ESD electric current.
Due to the device of GGNMOS way, during esd discharge, the base stage of the parasitic NPN triode voltage (Foldbackvoltage) that turns back is higher, and the pressure drop V namely between left side NMOS drain electrode and source electrode is higher; From generating heat, formula is I*V, and for the efficient heat that ESD device can be born, pressure drop V is less, and esd discharge electric current I just can be larger, and opposing electrostatic capacity is stronger.Therefore in prior art, because pressure drop V is higher, opposing electrostatic capacity is more weak.
Summary of the invention
The object of the invention is the defect for prior art, provide a kind of electrostatic discharge protective circuit and integrated circuit, the pressure drop V after being triggered by reduction ESD path on device improves ESD device electrostatic leakage ability, improves antistatic level.
First aspect present invention provides a kind of electrostatic discharge protective circuit, comprising: substrate; The well region be made up of the first well region and the second well region; From the upper surface of described first well region to the first active area of downward-extension, and and described first interval, active area the second active area is set; From the upper surface of described first well region to the first substrate contact region of downward-extension, between described first active area and described second active area; From the upper surface of described second well region to the second active area of downward-extension, and and described second interval, active area the 3rd active area is set; From the upper surface of described second well region to the second substrate contact region of downward-extension, and arrange on the position adjacent with described 3rd active area; To be formed on described second well region upper surface and grid oxic horizon between described second active area and described 3rd active area; Be formed at the grid on described grid oxic horizon.
Preferably, the doping content of described substrate and described well region is lower than described first substrate contact region, described second substrate contact region and described first active area, described second active area and described 3rd active area doping content.
Preferably, described first well region and described first active area, described second active area and described 3rd active area are N-type doping; Described second well region and described first substrate contact region, described second substrate contact region and described substrate are the doping of P type.
Preferably, described first active area, described first substrate contact region and described second active area are connected with the first link; Described grid, described 3rd active area and described second substrate contact region are connected with the second link.
Preferably, described first link is connected with the input and output pin of protected chip; Described second link is connected with the ground pin of protected chip.
Preferably, described first active area and described first substrate contact region are connected with the 3rd link; Described first grid, described 3rd active area and described second substrate contact region are connected with the 4th link.
Preferably, described 3rd link is connected with the input and output pin of protected chip; Described 4th link is connected with the ground pin of protected chip.
Preferably, between described substrate and described well region, buried regions is set, described second well region and described substrate are separated.
Second aspect present invention provides a kind of integrated circuit, comprises protected chip and above-mentioned arbitrary described electrostatic discharge protective circuit.
The present invention by GGNMOS structure, takes to increase N trap in the drain electrode of NMOS tube and injects, and injects at N trap and carry out P+ and inject and realize SCR structure; And remove the connection of the input and output pin of the second active area and protected chip in NMOS tube drain terminal; And increase buried regions, P trap and substrate are thoroughly kept apart; Reduce the pressure drop on the later device of ESD path triggering, and then improve the relieving capacity of ESD device, improve antistatic level.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the electrostatic discharge protection circuit structural representation using GGNMOS in prior art;
Fig. 2 is the electrostatic discharge protection circuit structural principle schematic diagram using GGNMOS in prior art;
A kind of electrostatic discharge protection circuit structural representation that Fig. 3 provides for the embodiment of the present invention;
A kind of electrostatic discharge protection circuit structural principle schematic diagram that Fig. 4 provides for the embodiment of the present invention;
Another electrostatic discharge protection circuit structural representation that Fig. 5 provides for the embodiment of the present invention;
The another kind of electrostatic discharge protection circuit structural representation that Fig. 6 provides for the embodiment of the present invention;
The another kind of electrostatic discharge protection circuit structural principle schematic diagram that Fig. 7 provides for the embodiment of the present invention;
Another electrostatic discharge protection circuit structural representation that Fig. 8 provides for the embodiment of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.
The embodiment of the present invention by GGNMOS structure, is taked to increase N trap in the drain electrode of NMOS tube and is injected, and injects at N trap and carry out P+ and inject and realize SCR structure; And remove the connection of the input and output pin of NMOS tube drain terminal second active area and protected chip; And increase buried regions, P trap and substrate are thoroughly kept apart; Reduce the pressure drop on the later device of ESD path triggering, and then improve the relieving capacity of ESD device, improve antistatic level.
A kind of electrostatic discharge protection circuit structural representation that Fig. 3 provides for the embodiment of the present invention.As shown in Figure 3, this circuit comprises: substrate; The well region be made up of the first well region and the second well region; From the upper surface of described first well region to the first active area of downward-extension, and and described first interval, active area the second active area is set; From the upper surface of described first well region to the first substrate contact region of downward-extension, between described first active area and described second active area; From the upper surface of described second well region to the second active area of downward-extension, and and described second interval, active area the 3rd active area is set; From the upper surface of described second well region to the second substrate contact region of downward-extension, and arrange on the position adjacent with described 3rd active area; To be formed on described second well region upper surface and grid oxic horizon between described second active area and described 3rd active area; Be formed at the grid on described grid oxic horizon.
Particularly, the doping content of described substrate and described well region is lower than described first substrate contact region, described second substrate contact region and described first active area, described second active area and described 3rd active area doping content.
Particularly, described first well region and described first active area, described second active area and described 3rd active area are N-type doping; Described second well region and described first substrate contact region, described second substrate contact region and described substrate are the doping of P type.
Particularly, described first active area, described first substrate contact region and described second active area are connected with the first link; Described grid, described 3rd active area and described second substrate contact region are connected with the second link.
Particularly, described first link is connected with the input and output pin of protected chip; Described second link is connected with the ground pin of protected chip.Grid, also can direct ground connection by resistance R ground connection.
A kind of electrostatic discharge protection circuit structural principle schematic diagram that Fig. 4 provides for the embodiment of the present invention.As shown in Figure 4, the input and output pin of substrate to be P-sub, IO be protected chip, G is connected with protected chip earth potential pin.The parasitic PNP triode of Q2 for being made up of the first substrate contact region P+, the first well region NWELL (N trap) and the second well region PWELL (P trap), first substrate contact region P+ is its emitter, first well region NWELL is its base stage, and the second well region PWELL is collector electrode.Q1 is the primary parasitic NPN triode of NMOS, and the second well region PWELL is its base stage, and the second active area N+ is its collector electrode, and the 3rd active area N+ is its emitter.The dead resistance R_NWELL of equivalence, one end is connected with parasitic triode Q2, and the other end is connected with the base stage of parasitic triode Q2; Dead resistance R_PWELL, its one end is connected with the base stage of Q1, and its other end is connected with the second substrate contact region.First grid in figure above Q1 is connected with G by resistance.
First substrate contact region P+, the first well region N trap, the second well region P trap and the 3rd active area N+ form controllable silicon SCR (Siliconcontrolledrectifier) structure of P+/NWELL/PWELL/N+.
ESD principle of releasing is, between the collector electrode of parasitic triode Q1 to the second well region PWELL, PN junction punctures, and electric current flows to the base stage of Q1 from the collector electrode of Q1; When dead resistance R-PWEL upper reaches overcurrent produces voltage, after being raised by the base voltage of Q1, and then trigger the big current path of Q1 collector electrode to emitter.
When enough large electric current flows through the first active area N+ and the second N+ region, active area of NMOS tube drain electrode, Q2 base potential step-down makes PNP triode Q2 conducting, produces the path from drain electrode first substrate contact region P+ to the second well region PWELL leakage current.
After this current direction dead resistance R-PWELL, raise parasitic triode Q1 base stage further, make Q1 On current larger; Larger Q1 On current drags down the voltage of Q2 base stage further, makes Q2 conducting more big current; Form the similar bolt-lock effect being of value to esd protection thus.Therefore, larger electric current of can releasing, opposing electrostatic capacity is stronger.
Another electrostatic discharge protection circuit structural representation that Fig. 5 provides for the embodiment of the present invention.As shown in the figure, between described substrate and described well region, buried regions is set, the substrate of the second well region and protected chip is separated.
Particularly, by increasing n type buried layer DN, the second well region PWELL and substrate P-sub is kept apart.Before buried regions is set, needs to inject N trap, form the 3rd well region, be arranged at the right side of P trap in figure, by P trap " encirclement " in centre.Namely the first well region NWELL of buried regions and drain terminal and the 3rd well region NWELL overlaps and forms complete isolation, is separated by the second well region PWELL and substrate P-sub.
Because substrate P-sub is ground connection, after isolation, make the source electrode of NMOS tube can connect the current potential on non-ground, as shown in FIG., meet the pin IO2 on non-ground.So just reduce further the source electrode of NMOS tube during electrostatic leakage and the pressure drop V of drain electrode, and the formula that generates heat is I*V, V is less, and esd discharge electric current I just can be larger, and opposing electrostatic capacity is stronger.
First active area N+, the second active area N+ and the first substrate contact region P+ between them are connected with the first link, and the first link is connected with pin IO1.All the other structures are above-mentioned to be explained, does not repeat them here.
The another kind of electrostatic discharge protection circuit structural representation that Fig. 6 provides for the embodiment of the present invention.As shown in the figure, the first active area and the first substrate contact region are connected with the 3rd link; First grid, described 3rd active area and the second substrate contact region are connected with the 4th link.
Particularly, the 3rd link is connected with the input and output pin IO of protected chip; Described 4th link is connected with the ground pin of protected chip.
The present embodiment is being equivalent to the upper connection eliminating NMOS drain terminal second active area N+ and IO1 pin on the basis of Fig. 5, and remains the connection of the first active area N+ and IO1.
All the other structure above-described embodiments explain, do not repeat them here.
The another kind of electrostatic discharge protection circuit structural principle schematic diagram that Fig. 7 provides for the embodiment of the present invention.As schemed shown in equivalent circuit, the electric current that Q1 asks for from its collector electrode after puncturing conducting needs to flow through longer distance, needs by I/O pin, the first active area N+, and flows through the equivalent parasitic resistance R_NWELL of the first well region N trap.Equivalent parasitic resistance shares a part of voltage, the base stage of Q2 is more easily dragged down, the conducting therefore Q2 is more easily triggered, and then more ESD electric current of releasing, reduce the effect of voltage (Foldbackvoltage) that turn back, opposing electrostatic capacity is stronger.
The present embodiment can be accomplished, when flowing through Q1 electric current and not being very large, because dead resistance R_NWELL can share a part of voltage, just more easily can drag down the current potential of Q2 base stage, and then the path that triggering ESD releases.Avoid when the electric current flowing through Q1 is less, effectively can not drag down the current potential of Q2 base stage, and then the path of the ESD that releases can not be triggered, thus the situation that path does not trigger and ESD device is broken by ESD may be occurred.
All the other electrostatic leakage processes are same as the previously described embodiments, do not repeat them here.
Another electrostatic discharge protection circuit structural representation that Fig. 8 provides for the embodiment of the present invention.Buried regions is set between described substrate and described well region, the substrate of the second well region and protected chip is separated.
The effect of buried regions is identical with effect with the principle of buried regions in above-described embodiment, does not repeat them here.
Arranging of all the other structures is same as the previously described embodiments, does not repeat them here.
The present invention by GGNMOS structure, takes to increase N trap in the drain electrode of NMOS tube and injects, and injects at N trap and carry out P+ and inject and realize SCR structure; And remove the connection of the input and output pin of the second active area and protected chip in NMOS tube drain terminal; And increase buried regions, P trap and substrate are thoroughly kept apart; Reduce the pressure drop on the later device of ESD path triggering, and then improve the relieving capacity of ESD device, improve antistatic level.
Professional should recognize further, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random asccess memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. an electrostatic discharge protective circuit, is characterized in that, comprising:
Substrate;
The well region be made up of the first well region and the second well region;
From the upper surface of described first well region to the first active area of downward-extension, and and described first interval, active area the second active area is set;
From the upper surface of described first well region to the first substrate contact region of downward-extension, between described first active area and described second active area;
From the upper surface of described second well region to the second active area of downward-extension, and and described second interval, active area the 3rd active area is set;
From the upper surface of described second well region to the second substrate contact region of downward-extension, and arrange on the position adjacent with described 3rd active area;
To be formed on described second well region upper surface and grid oxic horizon between described second active area and described 3rd active area;
Be formed at the grid on described grid oxic horizon.
2. circuit according to claim 1, it is characterized in that, the doping content of described substrate and described well region is lower than described first substrate contact region, described second substrate contact region and described first active area, described second active area and described 3rd active area doping content.
3. circuit according to claim 2, is characterized in that, described first well region and described first active area, described second active area and described 3rd active area are N-type doping;
Described second well region and described first substrate contact region, described second substrate contact region and described substrate are the doping of P type.
4. circuit according to claim 1, is characterized in that, described first active area, described first substrate contact region and described second active area are connected with the first link;
Described first grid, described 3rd active area and described second substrate contact region are connected with the second link.
5. circuit according to claim 4, is characterized in that, described first link is connected with the input and output pin of protected chip;
Described second link is connected with the ground pin of protected chip.
6. circuit according to claim 1, is characterized in that, described first active area and described first substrate contact region are connected with the 3rd link;
Described grid, described 3rd active area and described second substrate contact region are connected with the 4th link.
7. circuit according to claim 6, is characterized in that, described 3rd link is connected with the input and output pin of protected chip;
Described 4th link is connected with the ground pin of protected chip.
8. the circuit according to claim 4 or 5, is characterized in that, arranges buried regions between described substrate and described well region, described second well region and described substrate is separated.
9. an integrated circuit, is characterized in that, comprise protected chip and as claim 1-8 arbitrary as described in electrostatic discharge protective circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510900703.4A CN105390490B (en) | 2015-12-08 | 2015-12-08 | A kind of electrostatic discharge protective circuit and integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510900703.4A CN105390490B (en) | 2015-12-08 | 2015-12-08 | A kind of electrostatic discharge protective circuit and integrated circuit |
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| Publication Number | Publication Date |
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| CN105390490A true CN105390490A (en) | 2016-03-09 |
| CN105390490B CN105390490B (en) | 2018-11-13 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108172566A (en) * | 2016-12-07 | 2018-06-15 | 北大方正集团有限公司 | The production method of ESD protection structure |
| CN109449155A (en) * | 2018-11-16 | 2019-03-08 | 合肥博雅半导体有限公司 | A kind of static leakage circuit and device |
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| CN102693980A (en) * | 2012-06-14 | 2012-09-26 | 上海贝岭股份有限公司 | Silicon controlled rectifier electro-static discharge protection structure with low trigger voltage |
| CN104979805A (en) * | 2015-07-08 | 2015-10-14 | 无锡中星微电子有限公司 | Bidirectional static protection circuit and battery protection circuit thereof |
| CN205319155U (en) * | 2015-12-08 | 2016-06-15 | 无锡中感微电子股份有限公司 | Static protective circuit and integrative circuit |
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| US20050098795A1 (en) * | 2003-11-12 | 2005-05-12 | Geeng-Lih Lin | High voltage device with ESD protection |
| CN102693980A (en) * | 2012-06-14 | 2012-09-26 | 上海贝岭股份有限公司 | Silicon controlled rectifier electro-static discharge protection structure with low trigger voltage |
| CN104979805A (en) * | 2015-07-08 | 2015-10-14 | 无锡中星微电子有限公司 | Bidirectional static protection circuit and battery protection circuit thereof |
| CN205319155U (en) * | 2015-12-08 | 2016-06-15 | 无锡中感微电子股份有限公司 | Static protective circuit and integrative circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108172566A (en) * | 2016-12-07 | 2018-06-15 | 北大方正集团有限公司 | The production method of ESD protection structure |
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| CN109449155B (en) * | 2018-11-16 | 2024-05-24 | 合肥博雅半导体有限公司 | Static electricity discharge circuit and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105390490B (en) | 2018-11-13 |
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