CN203707130U

CN203707130U - A latch-up protection structure of an integrated circuit chip

Info

Publication number: CN203707130U
Application number: CN201320839302.9U
Authority: CN
Inventors: 金湘亮; 蒋琦; 袁晖晖
Original assignee: Xiangtan University
Current assignee: Xiangtan University
Priority date: 2013-12-18
Filing date: 2013-12-18
Publication date: 2014-07-09
Anticipated expiration: 2023-12-18

Abstract

The utility model discloses a latch-up protection structure of an integrated circuit chip. The protection structure includes an internal circuit of a chip and a drive circuit connected to the internal circuit. The drive circuit comprises a P-type substrate, an NMOS transistor and a PMOS transistor. The NMOS transistor is arranged on the P-type substrate which is provided with an N-well. The PMOS transistor is arranged in the N-well. A first isolating layer is disposed between the PMOS transistor and the N-well; a second isolating layer is disposed between the NMOS transistor and the P-type substrate; a first protection ring is disposed between the first isolating layer and the N-well; and a second protection layer is disposed between the second isolating layer and the P-type substrate. With ESD1DM isolating layers on the substrate of the NMOS transistor and the PMOS transistor, isolation between a drain electrode diffusion area and the substrate is enhanced. With the protection ring arranged between the NMOS transistor and the PMOS transistor, the purpose of cutting off an SCR-parasitized current path in the chip is achieved.

Description

A kind of latch-up protection structure of integrated circuit (IC) chip

Technical field

The utility model relates to integrated circuit fields, particularly a kind of latch-up of integrated circuit (IC) chip protection structure.

Background technology

In integrated circuit fields, a lot of chips are usually operated in the strongly disturbing environment such as high-intensity magnetic field, highfield, chip is often subject to the interference of static and other electric pulses, under normal circumstances, the input/output port of chip has the protection of the protection devices such as ESD that chip can normally be worked, but for certain some chip, because the metal-oxide-semiconductor drain diffusion regions of its circuit of output terminal is directly connected with output PAD, the substrate that outside disturbance current can directly enter chip forms substrate current (consulting Fig. 1); In cmos circuit, adjacent nmos device and PMOS device are due to substrate parasitic triode (Q1, Q2) and dead resistance R _sub, R _wellexistence, can there is SCR (being silicon controlled rectifier) structure (consulting Fig. 2), the generation of substrate current can make the electromotive force of each point in substrate different and form underlayer voltage and fall, voltage drop meeting on substrate makes triode (Q1, the Q2) conducting in SCR structure, if the current gain of triode is greater than 1 breech lock that can cause circuit, and then cause chip failure even permanently to damage.

Summary of the invention

In order to solve the problems of the technologies described above, the utility model provides a kind of latch-up protection structure of simple in structure, the integrated circuit (IC) chip that can improve latch-up immunity.

The technical scheme that the utility model addresses the above problem is: a kind of latch-up protection structure of integrated circuit (IC) chip; the drive circuit that comprises the internal circuit of chip and be connected with internal circuit; described drive circuit comprises P type substrate; NMOS pipe and PMOS pipe; NMOS pipe is placed on P type substrate, and P type substrate is provided with N trap, and described PMOS pipe is placed in N trap; between described PMOS pipe and N trap, be provided with the first separator, between described NMOS pipe and P type substrate, be provided with the second separator.

Between described the first separator and N trap, be provided with the first guard ring, between the second separator and P type substrate, be provided with the second guard ring, between NMOS pipe and PMOS pipe, separate by the first guard ring and the second guard ring.

The input of chip is connected with the grid of NMOS pipe, the grid of PMOS pipe respectively, the source electrode of PMOS pipe connects high level, the source ground of NMOS pipe, after the drain electrode of NMOS pipe is connected with the drain electrode of PMOS pipe, as the output of chip, the output of chip is connected with PAD after current-limiting resistance.

The latch-up protection structure of described integrated circuit (IC) chip also comprises ESD device, and described ESD device is connected with PAD.

Between described PAD and drive circuit, be provided with the first double shielding ring.

Between described drive circuit and internal circuit, be provided with the second double shielding ring.

The beneficial effects of the utility model are:

1, in the substrate of NMOS pipe of the present utility model and PMOS pipe, be provided with ESD1DM separator, strengthened the isolation of drain diffusion regions and substrate;

2, between NMOS pipe of the present utility model and PMOS pipe, be provided with guard ring, can reach the object of cutting off the current path of parasitic SCR in chip;

3, the output of the utility model drive circuit and output are provided with a current-limiting resistance between PAD, can reduce to flow into the external disturbance electric current of circuitry substrate, reduce chip and inject the probability that brings out latch-up because of foreign current;

4, between drive circuit of the present utility model and internal circuit, be equipped with double shielding ring between drive circuit and output PAD, can noise isolation, reduce influencing each other of output stage and near circuit.

Accompanying drawing explanation

Fig. 1 is the circuit structure profile of general driver output.

Fig. 2 is SCR electrical block diagram parasitic in chip substrate.

Fig. 3 is structural representation of the present utility model.

Fig. 4 is the vertical view of Fig. 3.

In figure: 1 is P-sub (being P type substrate); 2 is N-well (being N trap); 3 is current-limiting resistance; 4 is the ESD1DM layer of PMOS; 5 is the drain electrode of PMOS; 6 is the source electrode of PMOS; 7 is the substrate contact of PMOS; 8,9 guard rings that are PMOS; 10,15 guard rings that are NMOS; 11 is the drain electrode of NMOS; 12 is the ESD1DM layer of NMOS; 13 is the source electrode of NMOS; 14 is NMOS substrate contact; 16 is driver output PAD; 17 is ESD device; 18,19 and 20,21 be respectively two-layer guard ring; 22 is chip internal circuit.

Embodiment

Below in conjunction with drawings and Examples, the utility model is further described.

As shown in Figure 3, Figure 4, the drive circuit that the utility model comprises the internal circuit of chip and is connected with internal circuit, described drive circuit comprises Psub1, NMOS pipe and PMOS pipe, NMOS pipe is placed on P type substrate 1, P type substrate is provided with Nwell2, described PMOS pipe is placed in N trap 2, the input of chip is connected with the grid of NMOS pipe, the grid of PMOS pipe respectively, the source electrode 6 of PMOS pipe connects high level, source electrode 13 ground connection of NMOS pipe, after the drain electrode 11 of NMOS pipe is connected with the drain electrode 5 of PMOS pipe as the output of chip.In addition, in the substrate of PMOS pipe, NMOS pipe, add respectively separator (being ESD1DM layer) 4, separator (being ESD1DM layer) 12, ESD1DM layer has been strengthened the drain diffusion regions of metal-oxide-semiconductor and the isolation of substrate; Respectively NMOS and PMOS are kept apart with the first guard ring, the second guard ring, the first guard ring comprises guard ring 8, guard ring 9 again, and guard ring 8, guard ring 9 be around Nwell2 inner side, and meets V _dDform the how sub-guard ring of electronics, and play substrate contact effect, the second guard ring comprises guard ring 10, guard ring 15; guard ring 10, guard ring 15 are managed around NMOS; and connect the how sub-guard ring in GND formation hole, and play substrate contact effect, thus cut off the current path of parasitic SCR in chip.

Than common MOS device, the drain diffusion regions 11 of NMOS pipe of the present utility model, the drain diffusion regions 5 of PMOS pipe are larger, prevent the damage of device when large electric current exists; In addition, increase the contact hole density of device and substrate to reduce resistance substrate, made the resistance (R of (shown in Fig. 2) in parasitic SCR structure _sub, R _well) upper pressure drop deficiency makes transistor turns, thereby avoid the generation of latch-up.

The utility model adds double shielding ring guard-ring(one deck majority carrier guard ring 20 and one deck minority carrier guard ring 21 between the drive circuit of chip and internal circuit) they are isolated, its effect one is noise isolation, the 2nd, reduce influencing each other of output stage and near circuit; The width of guard-ring can be adjusted as required, and generally the wider effect of width is just better, but in practical application, also should consider the restriction of chip area.

Another measure of the utility model latch-up safeguard structure is to allow the output of drive circuit be connected with output PAD16 by a current-limiting resistance 3, the resistance very little (generally tens ohm to 100 ohm left and right) of current-limiting resistance, be used for reducing to flow into the external disturbance electric current of circuitry substrate, reduce chip and bring out the probability of latch-up because foreign current injects.Choosing of the value of current-limiting resistance must consider that the impact on chip performance falls in the extra voltage that resistance self produces, and in the time of design circuit, can between chip performance requirement and the latch-up robustness of chip, do a compromise and select.

Outermost one deck protection of chip is at its integrated ESD17 device in output PAD16 place, and between ESD device and internal circuit, embed double shielding ring (majority carrier guard ring 19 and minority carrier guard ring 18): its effect one is the antistatic capacity that improves chip, the 2nd, the interference signal that reduces to enter internal circuit; Minority carrier guard ring 18 is collections of carrying out electronics, and the minority carrier guard ring degree of depth is darker, and it can reduce on substrate the current gain of parasitic horizontal triode; Majority carrier guard ring 19 is corresponding, collects hole.For P type substrate, the effect of majority carrier guard ring is to reduce dead resistance local on substrate.

Claims

1. the latch-up of integrated circuit (IC) chip protection structure; the drive circuit that comprises the internal circuit of chip and be connected with internal circuit; described drive circuit comprises P type substrate; NMOS pipe and PMOS pipe; NMOS pipe is placed on P type substrate, and P type substrate is provided with N trap, and described PMOS pipe is placed in N trap; it is characterized in that: between described PMOS pipe and N trap, be provided with the first separator, between described NMOS pipe and P type substrate, be provided with the second separator.

2. the latch-up of integrated circuit (IC) chip according to claim 1 protection structure; it is characterized in that: between described the first separator and N trap, be provided with the first guard ring; between the second separator and P type substrate, be provided with the second guard ring, between NMOS pipe and PMOS pipe, separate by the first guard ring and the second guard ring.

3. the latch-up of integrated circuit (IC) chip according to claim 1 protection structure; it is characterized in that: the input of chip is connected with the grid of NMOS pipe, the grid of PMOS pipe respectively; the source electrode of PMOS pipe connects high level; the source ground of NMOS pipe; after the drain electrode of NMOS pipe is connected with the drain electrode of PMOS pipe, as the output of chip, the output of chip is connected with PAD after current-limiting resistance.

4. the latch-up of integrated circuit (IC) chip according to claim 3 protection structure, is characterized in that: also comprise ESD device, described ESD device is connected with PAD.

5. the latch-up of integrated circuit (IC) chip according to claim 4 protection structure, is characterized in that: between described PAD and drive circuit, be provided with the first double shielding ring.

6. the latch-up of integrated circuit (IC) chip according to claim 4 protection structure, is characterized in that: between described drive circuit and internal circuit, be provided with the second double shielding ring.