CN105679658B - A kind of reinforcement means of cmos device anti-single particle locking - Google Patents
A kind of reinforcement means of cmos device anti-single particle locking Download PDFInfo
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- CN105679658B CN105679658B CN201610065541.1A CN201610065541A CN105679658B CN 105679658 B CN105679658 B CN 105679658B CN 201610065541 A CN201610065541 A CN 201610065541A CN 105679658 B CN105679658 B CN 105679658B
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/263—Bombardment with radiation with high-energy radiation
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a kind of reinforcement means of cmos device anti-single particle locking, neutron irradiation is carried out to cmos device, displacement damage is introduced by neutron irradiation, P N P N lockings will not be occurred by being reduced to the current gain of device CMOS inverter endophyte bipolar transistor, the reinforcement means is a kind of externally reinforced method, do not increase the processing step of production device, redesign element layout without being directed to single-event latchup, do not increase the complexity of original system.Therefore, the intrinsic size of device will not be changed, peripheral circuit will not be increased.
Description
Technical field
The present invention relates to a kind of reinforcement means of cmos device anti-single particle locking, are particularly suitable for commercial cmos device and resist
The reinforcing of single event latchup.
Technical background
An important research direction of the moonlet as current space industry, is of great significance for national defense construction.For
Reduction R＆D costs mitigate quality and shorten the R＆D cycle, using commercial cmos device are space technologies in moonlet
New developing direction.
Commercial cmos device is the stock device for referring to be bought directly from the market, and includes two layers of meaning：When
The rank for referring to product is business level or technical grade, to be different from army grade and aerospace grade；Second is that product stock in hand is supplied, do not need to
Custom-made.At present, developed country carries out export restrictions for army grade and aerospace grade device, and the introduction of commercial off-the-shelf device
It is relatively loose.And the manufacturer of commercial devices is more, and choice is big.General army grade, aerospace grade Flouride-resistani acid phesphatase device
The cost of part is 1000 to 10000 dollars, and the cost of commercial cmos device is 1 to 100 dollars.Therefore, it is used on moonlet
Commercial cmos device can substantially reduce research and development and rise this, shorten the R＆D cycle.
Due to not using special reinforcement measure, itself capability of resistance to radiation of commercial cmos device is weaker than army grade and aerospace grade
Device.It predictably, will be by spoke when the moonlet using commercial cmos device is placed in the radiation environment of cosmic space
The influence for penetrating effect generates performance degradation even damage.
Single event latchup (Single Event Latchup, SEL) is that cosmic space radiation environment generates electronic device
One of radiation effect, it can cause hardware within the extremely short time permanent destruction, very harmful, therefore aerospace electricity consumption
Sub- device should avoid that single-event latchup occurs completely.At present, industry provides the anti-list of the device used on moonlet
LET (Linear Energy Transfer) threshold value of particle locking should be not less than 75MeVcm2/mg.This is also just commercialization
Use of the cmos device on moonlet proposes higher reinforcement criteria.
The endoparasitic P-N-P-N four-layer structures of cmos device are as shown in Figure 1, similar to thyristor structure.It is wherein vertical
PNP pipe in, P+Source electrode (meeting VDD) is as emitter E, N traps as base stage B, p-type epitaxial layer as collector C；Lateral
In NPN pipes, N+Source electrode is as emitter E, p-type epitaxial layer as base stage B, N trap as collector C.
This structure can be equivalent to two triodes (PNP and NPN) positive feedback connect as shown in Fig. 2, by weight from
During son bombardment, a large amount of electron-hole pair can be generated in semiconductor chip, these electron-hole pairs are in external electric field and built-in electricity
Drift or diffusion under the collective effect of field, so as to form electric current.These electric currents flow through p-well resistance RPShi Ruguo generates sufficiently large
Pressure drop will be connected the base-emitter of parasitic NPN transistor, and NPN pipes is made to enter amplification mode, while the conducting of NPN pipes
It can cause there is electric current to flow through N trap resistance RN, similary generation pressure drop leads to vertical PNP pipe base-emitter, and also forward bias is opened
It opens, such PNP pipe also enters amplification mode.The conducting of PNP pipe is but also flow through RPElectric current increase so that NPN pipes are further
Conducting.So cycle, eventually leads to two parasitic transistors all saturations, and a low-resistance will be formed by being generated between power supply and ground
Channel, formation are enough the high current maintained down, and here it is single event latchup phenomenons.In this state, since electric current increases
Chip temperature is caused drastically to increase, and then device can be caused to burn.
The necessary condition that cmos device forms locking is as follows：
(1) the current gain product of parasitic NPN and PNP bipolar transistor, i.e. βnpn·βpnp＞ 1.
(2) P-N-P-N four-layer structures are in forward bias, and make emitter-base stage of parasitic NPN or PNP transistor
It is connected in forward bias so as to cause parasitic transistor.
(3) electric current that power supply can be provided to P-N-P-N four-layer structures, which is more than, maintains electric current IH。
The method for solving single-event latchup at present is the third condition from barring condition mostly, that is, limit
The electric current that power supply processed provides.Limiting electric current, there are two types of methods：The first is to introduce current-limiting resistance, although this reinforcement means can be with
It avoids being latched to a certain extent, but additional partial pressure can be generated, can also increase circuit power consumption, this is not in many devices
It is allowed to；Another is to use constant-current source, that is, directly limit the electric current for flowing into device, and this method can be certain
Single-event latchup is avoided in degree, but effect is not just had when the operating current of device is more than when locking maintains electric current
.
Number of patent application CN200710118543.3, entitled " a kind of plate grade single event latchup failure detects automatically and solution
Except circuit " in use pass through voltage comparator identification locking failure, cut off all power supply access, until latch up effect solution
Except re-powering again.Number of patent application CN201410026106.9, entitled " a kind of renewable type anti-single particle locking power supply connects
What mouthful circuit " used is also outer protection circuit, when single event latchup phenomenon occurs for load, to load circuit power-off protection,
Then trouble shooting time configuration power-off time is latched according to load equipment.This two methods are it is possible to prevente effectively from latch up effect
Maintenance, but be powered off powering on the function effect caused by device and cannot ignore, because the method is suitable for effect study rank
Section.
Number of patent application CN201410126616.3, a kind of entitled " standard cell design of anti-single particle latch up effect
Method " is then using redesign circuit layout addition protection band, changes technological parameter and adds to carry out anti-single particle latch up effect
Gu.This scheme is suitable for layout design, on the device that processing step can change, and this exactly commercial cmos device institute is not
The condition having.Therefore, it is not suitable for commercial cmos device.
Invention content
It is of the invention successfully to propose that one kind is not changing device layout design, do not increase periphery protection circuit, do not change life
Profit experimentally inhibits the reinforcement means of cmos device single event latchup under the premise of production. art step.
The present invention technical solution be：
A kind of reinforcement means of cmos device anti-single particle locking provided by the invention, is characterized in that：
Neutron irradiation is carried out to cmos device, displacement damage is introduced by neutron irradiation, is made inside device CMOS inverter
The current gain of parasitic bipolar transistor, which is reduced to, will not occur P-N-P-N lockings.
Above-mentioned the determining of neutron irradiation fluence follows the steps below：
1) cmos device sample to be reinforced is selected, population parameter test is carried out to device sample, obtains each of device sample
Item performance indicator parameter is used as with reference to standard；
2) it is 1 × 10 to select equivalent 1MeV neutron fluences12/cm2~1 × 1014/cm2Between multiple fluence values；
3) multiple cmos device samples to be reinforced are selected, it is real to carry out pre-irradiation under the neutron fluence of step 2) respectively
It tests；
4) population parameter test is also carried out to multiple cmos device samples to be reinforced after pre-irradiation is tested, got rid of
The inconsistent device of reference standard that performance indicator and step 1) are surveyed；
5) device intact to function after neutron pre-irradiation and the sample without neutron pre-irradiation carry out identical heavy respectively
Single event latchup experiment under ion irradiation environment, obtains the locking cross section curve after different neutron fluence predoses；
6) locking cross section curve is analyzed, obtains meeting " the minimum neutron fluence " under the conditions of reinforcement criteria, and will
The reinforcing standard neutron irradiation fluence as the cmos device.
Compared with prior art, the present invention main technological merit is embodied in：
1st, the Scheme of Strengthening of neutron pre-irradiation proposed by the present invention so that commercial cmos device may replace army grade and aerospace
Grade cmos device, not only reduces cost, is also army grade, aerospace grade Flouride-resistani acid phesphatase device provides the range of choice of bigger, keeps away
The export restrictions that Kai Liao developed countries carry out army grade and aerospace grade device.
2nd, the reinforcement means that the present invention uses is a kind of externally reinforced method, does not increase the processing step of production device, no
Element layout is redesigned with for single-event latchup, does not increase the complexity of original system.Therefore, device will not be changed
Intrinsic size, peripheral circuit will not be increased.As it can be seen that this method is fit closely for commercial cmos device.
3rd, the reinforcement means step that the present invention uses is simple, is obtaining " the best neutron fluence " of corresponding commercial cmos device
After can directly carry out neutron irradiation processing to device, this just shortens the R＆D cycle of moonlet internal electronic device, drop
Low R＆D costs.
4th, the reinforcement means that the present invention uses influences the electrology characteristic of commercial cmos device small.Modern Commercial cmos device
Anti- neutron irradiation ability it is stronger, the reinforcement criteria of neutron pre-irradiation can be met, this just for this reinforcement means provide feasibility protect
Card.
5th, neutron according to the present invention, the application of heavy ion experimental facilities at home comparative maturity, this is just this
The itd is proposed reinforcement measure of invention provides strong guarantee.
Description of the drawings
Fig. 1 is the schematic diagram that single event latchup occurs for typical cmos device；
Fig. 2 is that single event latchup positive feedback loop simplification figure occurs for typical cmos device；
Fig. 3 is that the present invention improves commercial cmos device anti-single particle locking function flow chart；
Fig. 4 is best neutron fluence selection schematic diagram of the invention.
Specific embodiment
The Scheme of Strengthening of neutron pre-irradiation proposed by the present invention, the scope of application is more extensive, is applicable not only to army grade, aerospace
Grade cmos device, is more suitable for commercial cmos device.Many researchs both domestic and external have been verified that neutron irradiation to bipolar device
The influence of DC current gain, but neutron irradiation is applied to the method that device reinforces does not have even at home, it is external also only
It is to study neutron irradiation for single particle effect, is not applied to device reinforcing.The present invention is with commercial CMOS devices
Application demand of the part in moonlet increasingly compels to be cut to application background, and the anti-neutron irradiation ability of modern cmos device is general
All over 110 can be reached15n/cm2More than, the present invention provides feasibility guarantees for this position.In addition, the proposition of the present invention is aiming at small
The consolidation process of the commercial cmos device of satellite so the device model to be reinforced is relatively fixed, finds the " best of respective devices
The complexity of reinforcing neutron fluence " is greatly reduced.=
The technical principle of the present invention：Neutron is uncharged particle, its penetration capacity is extremely strong.Because not charged, it can be with
Adequately close to the atomic nucleus of radioactive material lattice atoms, elastic collision occurs with atomic nucleus.Lattice atoms are in collision process
In obtain energy, so as to leave its normal lattice position, become lattice interstitial atoms, one left in its original position
Vacancy forms not human relations Cole defect.
There are three main Macroscopic physical parameters for various semi-conducting materials：Minority carrier lifetime tau, majority carrier concentration
N (or p) and mobility [mu].
Neutron irradiation, which forms defect, to introduce additional energy in the forbidden band of semi-conducting material atom, these defects can fill
Work as complex centre, increase minority carrier and the compound chance of majority carrier, increase recombination rate, minority carrier lifetime
It reduces, reduction can be represented by the formula
In formula (1)：τ (Ф) is the minority carrier lifetime of material after neutron irradiation；τ (0) is material before neutron irradiation
Minority carrier lifetime；KτIt is special with irradiation particle types, energy and body material for the minority carrier lifetime damage constant of material
Property is related；Ф is radiation neutron fluence.
The parameter of most critical is current gain in the unit for electrical property parameters of bipolar transistor, is divided into common-base current gain (α
Or hFB) and common emitter current gain (β or hFE).The attenuation of current gain be bipolar transistor most significantly simultaneously and most
Typical radiation injury effect.One of the main reason for gain reduction is the displacement damage in semiconductor devices body, is caused in vivo
The increase of complex centre quantity, so as to reduce the service life of minority carrier.Another causes the major reason of gain reduction to be
Ionization damage in oxide skin(coating), the oxide skin(coating) for being especially covered in transmitting tie region are damaged.Capture in oxide
Charge and newly-generated interfacial state can lead to the increase of minority carrier recombination-rate surface, reduce base transport factor, so as to
Reduce gain.According to transistor physics parameter model, basic current gain expression formula is：
In formula (2)：β is current gain；S is recombination-rate surface；AsFor surface recombination area；W is base width；DBFor
Few sub- diffusion coefficient in base area；AETo emit junction area；σBAnd σEThe respectively conductivity of base stage and emitter；LEExist for few son
Diffusion length in emitter；τBFor minority carrier life time in base area；
First item is surface recombination item on the right of formula (2), and Section 2 is emission effciency item, and Section 3 is bluk recombination item.For
Different use conditions and radiation environment, each single item role are different.For currently designed preferable transistor, the
Binomial is mainly initial current gain, only related with the temperature in use of device.The ionization damage of first item and bipolar transistor
Effect is related, and Section 3 is related with the displacement damage effect of bipolar transistor.The radiation injury situation of current gain is commonly usedIt represents.In the case where not considering temperature, current gain variation is related with displacement damage and ionization damage.Due to this hair
The bright method that displacement damage is introduced using neutron pre-irradiation, therefore current gain variation and displacement damage relationship is most close.
Assuming that the surface recombination and emission effciency item in formula (2) are invariable, simultaneous equations can obtain Messenger-
Spratt formula：
In formula (3)Refer to the yield value variation brought due to displacement damage.It can illustrate, work as bipolar transistor
When pipe is subjected to displacement damage, the variable quantity reciprocal and irradiation fluence of current gain are in a linear relationship.The neutron that this formula is applicable in
Fluence ranging from 109/cm2~1016/cm2。
2nd, operating process of the invention refinement
The flow of neutron pre-irradiation experiment is as shown in Figure 3.
First, 6 samples therein is selected to carry out 6 different notes respectively into line label in cmos device to be reinforced
The neutron of amount irradiates in advance, and the equivalent 1MeV neutron fluences that can rule of thumb select are 1 × 1012/cm2~1 × 1014/cm2It
Between 6 fluence values.Then, population parameter test is carried out to the device after neutron pre-irradiation, obtains device property indices
There is abnormal device and record corresponding neutron fluence in situation of change, remove function, and the fluence for illustrating the neutron irradiation is more than
The anti-neutron ability of device；It picks out function, the device that parameter is kept and predose is basically identical and records corresponding neutron
Fluence.Then, to not neutron-irradiated device sample and 6 after by neutron irradiation normally functioning device sample do respectively weight
Single event latchup experiment under ion irradiation environment, obtains the change curve in device single event latchup section before and after neutron irradiation.
Finally, the situation of change of observation locking cross section curve, the locking section minimum for tentatively selecting device of sening as an envoy to are not latched even
Neutron fluence as best neutron fluence.
It is important to note that best neutron fluence is so that the electric current of commercial cmos device parasitic bipolar transistor increases
Benefit is reduced to " the minimum neutron fluence " that single event latchup does not occur.As shown in Figure 4,6 neutron fluences of selection are to device
The improvement degree of anti-single particle locking is different, and from " node 1 " to " node 6 " is it is observed that device locking section is in decline
Gesture, the neutron fluence corresponding to " node 5 " are a relatively apparent turning points, its corresponding neutron fluence cuts the locking of device
Face, which improves, to be readily apparent that, and " node 6 " thereafter be compared to the improvement unobvious of " node 5 ", thus we to select it is full
" the minimum neutron fluence " of sufficient reinforcement criteria, that is, " node 5 " corresponding neutron fluence, the standard neutron as the device are pre-
Irradiate fluence.
If the neutron fluence of radiation is excessive, the no doubt decline of current gain can be met the requirements, and obtain larger peace
Full surplus, but simultaneously increased input leakage current and quiescent power supply current in semiconductor integrated circuit, this is the result for being not intended to see.This is also choosing
Select the current demand of " minimum neutron fluence ".
The undisclosed technology of the present invention belongs to common sense well known to those skilled in the art.
Claims (1)
1. a kind of reinforcement means of cmos device anti-single particle locking, it is characterised in that：
Neutron irradiation is carried out to cmos device, displacement damage is introduced by neutron irradiation, makes device CMOS inverter endophyte
The current gain of bipolar transistor, which is reduced to, will not occur P-N-P-N lockings；
The determining of neutron irradiation fluence follows the steps below：
1) cmos device sample to be reinforced is selected, population parameter test is carried out to device sample, obtains the items of device sample
Energy index parameter is used as with reference to standard；
2) it is 1 × 10 to select equivalent 1MeV neutron fluences12/cm2~1 × 1014/cm2Between multiple fluence values；
3) multiple cmos device samples to be reinforced are selected, carry out pre-irradiation experiment under the neutron fluence of step 2) respectively；
4) population parameter test is also carried out to multiple cmos device samples to be reinforced after pre-irradiation is tested, gets rid of performance
The inconsistent device of reference standard that index and step 1) are surveyed；
5) device intact to function after neutron pre-irradiation and the sample without neutron pre-irradiation carry out identical heavy ion respectively
Single event latchup experiment under radiation environment, obtains the locking cross section curve after different neutron fluence predoses；
6) locking cross section curve is analyzed, obtains meeting " the minimum neutron fluence " under the conditions of reinforcement criteria, and making it into
Reinforcing standard neutron irradiation fluence for the cmos device.
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106569068B (en) * | 2016-11-04 | 2018-02-09 | 西北核技术研究所 | A kind of anti-transient ionizing radiation effect reinforcement means of SRAM memory |
| CN108037434B (en) * | 2017-12-07 | 2019-11-12 | 湘潭大学 | A kind of area of safety operaton of VDMOS device determines method and device |
| CN108470735B (en) * | 2018-04-10 | 2020-06-30 | 湘潭大学 | Reinforcing method for resisting single-particle disturbance of ferroelectric memory |
| CN108962307A (en) * | 2018-07-17 | 2018-12-07 | 湘潭大学 | A kind of ferroelectric memory anti-single particle overturning reinforcement means and system |
| CN110045204B (en) * | 2019-04-26 | 2021-09-07 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Single event latch-up holding current test method, device and system |
| CN110045205B (en) * | 2019-04-26 | 2021-05-11 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Single event latch-up limited current test method, device and system |
| CN111508933B (en) * | 2020-04-29 | 2023-09-19 | 西安电子科技大学 | Method for reinforcing single event effect resistance of germanium-silicon heterojunction transistor |
| CN111987073B (en) * | 2020-08-28 | 2022-05-31 | 厦门理工学院 | Neutron irradiation-based anti-irradiation reinforced SOI device and preparation method thereof |
| CN114861589A (en) * | 2022-04-22 | 2022-08-05 | 电子科技大学 | Method for generating anti-irradiation CMOS standard unit |
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| US5315544A (en) * | 1991-11-29 | 1994-05-24 | Trw Inc. | Radiation-hardened memory storage device for space applications |
| CN102522362A (en) * | 2011-12-14 | 2012-06-27 | 中国科学院微电子研究所 | Method for improving anti-irradiation performance of SOI (Silicon On Insulator) structure |
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| JPH0750774B2 (en) * | 1985-05-10 | 1995-05-31 | 工業技術院長 | MOS integrated circuit |
| JPH0228967A (en) * | 1988-07-19 | 1990-01-31 | Nec Corp | Complementary insulated-gate field-effect semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315544A (en) * | 1991-11-29 | 1994-05-24 | Trw Inc. | Radiation-hardened memory storage device for space applications |
| CN102522362A (en) * | 2011-12-14 | 2012-06-27 | 中国科学院微电子研究所 | Method for improving anti-irradiation performance of SOI (Silicon On Insulator) structure |
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