CN105679658A - Reinforcement method for single event latchup resistance of CMOS device - Google Patents

Abstract

The invention discloses a reinforcement method for the single event latchup resistance of a CMOS device. Neutron irradiation is carried out on the CMOS device; a displacement damage is introduced in the neutron irradiation; and a current gain of a parasitical bipolar transistor in an inverter of the CMOS device is reduced, so that P-N-P-N latchup is not generated. The reinforcement method is an external reinforcement method; processing steps to produce the device will not be increased; there is no need to redesign a device layout for the single event latchup effect; and complexity of an original system will not be increased. Thus, the fixed size of the device will not be changed, and a peripheral circuit will not be increased either.

Description

A kind of reinforcement means of cmos device anti-single particle locking

Technical field

The present invention relates to the reinforcement means of a kind of cmos device anti-single particle locking, be particularly suited for the reinforcing of commercial cmos device anti-single particle locking.

Technical background

Moonlet, as an important research direction of current space industry, is significant for national defense construction. In order to reduce R&D costs, alleviate quality and shorten the R&D cycle, adopting commercial cmos device in moonlet is the developing direction that space technology is new.

Commercial cmos device refers to the stock device being bought directly from the market, and comprises the two-layer meaning: one refers to that the rank of product is business level or technical grade, to be different from army grade and aerospace level; Two is product stock in hand supply, it is not necessary to custom-made. At present, developed country carries out export restrictions for army grade and aerospace level device, and the introduction of COTS device is relatively loose. And the manufacturer of commercial devices is many, choice is big. General army grade, the cost of aerospace level Flouride-resistani acid phesphatase device are 1000 to 10000 dollars, and the cost of commercial cmos device is 1 to 100 dollars. Therefore, moonlet adopts commercial cmos device can be substantially reduced research and development and rise this, shorten the R&D cycle.

Owing to being provided without special reinforcement measure, commercial cmos device self capability of resistance to radiation is weaker than army grade and aerospace level device. Predictably, when the moonlet adopting commercial cmos device is placed in the radiation environment of cosmic space, the impact of effect exposed to radiation will produce performance degradation and even damage.

Single event latchup (SingleEventLatchup, SEL) it is that cosmic space radiation environment is to one of radiation effect that electronic device produces, hardware can be caused permanent destruction by it within the extremely short time, very harmful, therefore aerospace electronic device should be avoided single-event latchup completely. At present, industry specifies that LET (LinearEnergyTransfer) threshold value of the device anti-single particle locking used on moonlet should be not less than 75MeV cm²/ mg. This also just proposes higher reinforcement criteria for commercial cmos device use on moonlet.

The endoparasitic P-N-P-N four-layer structure of cmos device is as it is shown in figure 1, be similar to thyristor structure. In wherein vertical PNP pipe, P⁺Source electrode (meets VDD) as emitter E, N trap as base stage B, P type epitaxial layer as colelctor electrode C; In horizontal NPN pipe, N⁺Source electrode as emitter E, P type epitaxial layer as base stage B, N trap as colelctor electrode C.

This structure can be equivalent to two audion (PNP and NPN) positive feedbacks and connect as shown in Figure 2, when suffering heavy ion bombardment, substantial amounts of electron-hole pair can be produced in semiconductor chip, these electron-hole pairs drift about under the combined effect of external electric field and built in field or spread, thus forming electric current. These electric currents flow through p-well resistance R_PShi Ruguo produces sufficiently large pressure drop, and the base-emitter of parasitic NPN transistor will be made to turn on, and makes NPN pipe enter amplification mode, and the conducting of NPN pipe simultaneously can make electric current flow through N trap resistance R_N, same generation pressure drop causes that vertical PNP pipe base-emitter also forward bias is opened, and such PNP pipe is also into amplification mode. The conducting of PNP pipe also makes to flow through R_PElectric current increase so that the further conducting of NPN pipe. So circulation, ultimately results in two parasitic transistors all saturated, produces to constitute a low impedance path, form the big electric current being enough to maintain down between power supply and ground, here it is single event latchup phenomenon. In this state, cause that chip temperature sharply raises owing to electric current raises, and then can cause that device burns.

The essential condition that cmos device forms locking is as follows:

(1) the current gain product of parasitic NPN and PNP bipolar transistor, i.e. β_npn·β_pnp> 1.

(2) P-N-P-N four-layer structure is in forward bias, and makes the NPN of parasitism or the emitter stage-base stage of PNP transistor be in forward bias thus causing parasitic transistor to turn on.

(3) power supply can to the electric current that P-N-P-N four-layer structure provides more than maintaining electric current I_H。

The method solving single-event latchup at present is the 3rd condition from barring condition mostly, the electric current that namely restriction power supply provides. Restriction electric current has two kinds of methods: the first is introduced into current-limiting resistance, although this reinforcement means can avoid locking to a certain extent, but can produce extra dividing potential drop, also can increase circuit power consumption, and this is not allowed in many devices; Another is to adopt constant-current source, namely directly limits the electric current flowing into device, and this method can avoid single-event latchup to a certain extent, but does not just have effect when the operating current of device maintains electric current more than locking.

Number of patent application CN200710118543.3, name be called " a kind of plate level single event latchup fault automatically detect and relieving circuit " adopts by voltage comparator identification locking fault, cut off all power supply access, re-power again until latch up effect releases. Number of patent application CN201410026106.9; name is called that " a kind of renewable type anti-single particle locking power interface circuit " what adopt is also outer protection circuit; when load generation single event latchup phenomenon; to load circuit power-off protection, then configure power-off time according to the load equipment locking trouble shooting time. This two kinds of methods can be prevented effectively from the maintenance of latch up effect, but the function effect that device is caused that is powered off powering on can not be ignored, because the method is applicable to the effect study stage.

Number of patent application CN201410126616.3, name is called that " standard cell design method of a kind of anti-single particle latch up effect " is then adopt to redesign circuit layout interpolation protection band, changes technological parameter and carries out anti-single particle latch up effect reinforcing. This scheme is applicable to layout design, on the device that processing step can change, and this commercial condition not available for cmos device exactly.Therefore, it is not suitable for commercial cmos device.

Summary of the invention

The present invention successfully proposes one and is not changing element layout design, does not increase peripheral protection circuit, does not change the reinforcement means of profit experimentally suppression cmos device single event latchup under the premise of production craft step.

The technical solution of the present invention is:

The reinforcement means of a kind of cmos device anti-single particle locking provided by the invention, it is characterized in that

Cmos device is carried out neutron irradiation, introduces displacement damage by neutron irradiation, make the current gain of device CMOS inverter endophyte bipolar transistor be reduced to and P-N-P-N locking will not occur.

The determination of above-mentioned neutron irradiation fluence carries out according to following steps:

1) select cmos device sample to be reinforced, device sample is carried out population parameter test, obtain the property indices parameter of device sample as reference standard;

2) selecting equivalence 1MeV neutron fluence is 1 × 10¹²/cm²～1 × 10¹⁴/cm²Between multiple fluence values;

3) select multiple cmos device sample to be reinforced, respectively in step 2) neutron fluence under carry out pre-irradiation experiment;

4) the cmos device sample multiple to be reinforced after pre-irradiation is tested is also carried out population parameter test, gets rid of performance indications and step 1) the inconsistent device of the reference standard surveyed;

5) to the intact device of function after neutron pre-irradiation and carry out the single event latchup experiment under identical heavy ion irradiation environment respectively without the sample of neutron pre-irradiation, the locking cross section curve after different neutron fluence predose is obtained;

6) locking cross section curve is analyzed, is met " the minimum neutron fluence " when reinforcement criteria, and using it reinforcing standard neutron irradiation fluence as this cmos device.

Compared with prior art, main technological merit is embodied in the present invention:

1, the Scheme of Strengthening of the neutron pre-irradiation that the present invention proposes, commercial cmos device is made to may replace army grade and aerospace level cmos device, not only reduce cost, also provide the bigger range of choice for army grade, aerospace level Flouride-resistani acid phesphatase device, avoid the export restrictions that developed country carries out for army grade and aerospace level device.

2, the reinforcement means that the present invention adopts is a kind of externally reinforced method, does not increase the processing step producing device, need not redesign element layout for single-event latchup, not increase the complexity of original system. Therefore, the intrinsic size of device will not be changed, without increasing peripheral circuit. Visible, this method is fit closely for commercial cmos device.

3, the reinforcement means step that the present invention adopts is simple, at " the best neutron fluence " that obtain corresponding commercial cmos device, device just can be made directly neutron irradiation afterwards to process, this just shortens the R&D cycle of moonlet internal electronic device, reduces R&D costs.

4, the reinforcement means that the present invention adopts is little on the electrology characteristic impact of commercial cmos device. The anti-neutron irradiation ability of modern Commercial cmos device is relatively strong, can meet the reinforcement criteria of neutron pre-irradiation, and this just provides feasibility to ensure for this reinforcement means.

5, neutron involved in the present invention, the heavy ion experimental facilities comparative maturity of application at home, this just provides strong guarantee for reinforcement measure proposed by the invention.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of typical cmos device generation single event latchup;

Fig. 2 is typical cmos device generation single event latchup positive feedback loop simplification figure;

Fig. 3 is that the present invention improves commercial cmos device anti-single particle locking function flow chart;

Fig. 4 is that the best neutron fluence of the present invention selects schematic diagram.

Detailed description of the invention

The Scheme of Strengthening of the neutron pre-irradiation that the present invention proposes, the scope of application is more extensive, is applicable not only to army grade, aerospace level cmos device, is more suitable for commercial cmos device. A lot of research both domestic and external has been verified that the neutron irradiation impact on bipolar device DC current gain, but the method that neutron irradiation is applied to device reinforcing does not have at home not yet, the external single particle effect that is also simply used for by neutron irradiation is studied, and is not applied to device and reinforces. The present invention increasingly compels to be cut to application background with commercial cmos device application demand in moonlet, and the anti-neutron irradiation ability of modern cmos device generally can reach 110¹⁵n/cm²Above, this position the invention provides feasibility guarantee. Additionally, the proposition of the present invention is aiming at the consolidation process of the commercial cmos device of moonlet, so the device model to reinforce is relatively fixed, the complexity of " the best reinforcing neutron fluence " of respective devices is found to be greatly reduced.=

The know-why of the present invention: neutron is uncharged particle, its penetration capacity is extremely strong. Because not charged, it can fully near the atomic nucleus of radioactive material lattice atoms, with atomic nucleus generation elastic collision. Lattice atoms obtains energy in collision process, thus leaving its normal lattice position, becomes lattice interstitial atoms, stays next room in its original position, forms not human relations Cole defect.

Various semi-conducting materials have three main Macroscopic physical parameters: minority carrier lifetime tau, majority carrier concentration n (or p) and mobility [mu].

Neutron irradiation forms defect can introduce additional energy in the forbidden band of semi-conducting material atom, these defects just may act as complex centre, adds the chance of minority carrier and majority carrier compound, makes recombination rate increase, minority carrier lifetime reduces, and its minimizing can be represented by the formula

$\frac{1}{\mathrm{\τ}\left(\mathrm{\Φ}\right)}=\frac{1}{\mathrm{\τ}\left(0\right)}+K_{\mathrm{\τ}}\·\mathrm{\Φ}---\left(1\right)$

In formula (1): τ (Ф) is the minority carrier lifetime of material after neutron irradiation; τ (0) is the minority carrier lifetime of material before neutron irradiation; K_τFor the minority carrier lifetime damage constant of material, relevant with irradiation particle types, energy and body material behavior; Ф is radiation neutron fluence.

In the unit for electrical property parameters of bipolar transistor, the parameter of most critical is current gain, is divided into common-base current gain (α or h_FB) and common emitter current gain (β or h_FE). The decay of current gain is bipolar transistor is the most also most typical radiation damage effect. The one of the main reasons of gain reduction is the displacement damage in semiconductor device body, causes the increase of internal complex centre quantity, thus reducing the life-span of minority carrier. Another causes that the major reason of gain reduction is the ionization damage in oxide skin(coating), and the oxide skin(coating) especially covering emitter junction region sustains damage. Trap-charge in oxide and newly-generated interfacial state can cause the increase of minority carrier recombination-rate surface, reduce base transport factor, thus reducing gain. According to transistor physics parameter model, its basic current gain expression formula is:

$\frac{1}{\mathrm{\β}}=\frac{s\·A_s\·W}{D_B\·A_E}+\frac{{\mathrm{\σ}}_B\·W}{{\mathrm{\σ}}_E\·L_E}+\frac{W^2}{2\·D_B\·{\mathrm{\τ}}_B}---\left(2\right)$

In formula (2): β is current gain; S is recombination-rate surface; A_sFor surface recombination area; W is base width; D_BFor sub-diffusion coefficient few in base; A_EFor emitter junction area;σ_BAnd σ_EThe respectively electrical conductivity of base stage and emitter stage; L_EFor few son diffusion length in emitter stage; τ_BFor minority carrier life time in base;

Formula (2) the right Section 1 is surface recombination item, and Section 2 is emission effciency item, and Section 3 is bluk recombination item. For different use conditions and radiation environment, each role difference. For currently designed good transistor, Section 2 is mainly initial current gain, only relevant with the use temperature of device. Section 1 is relevant with the ionization damage effect of bipolar transistor, and Section 3 is relevant with the displacement damage effect of bipolar transistor. The radiation damage situation of current gain is commonly usedRepresent. When being left out temperature, current gain change is relevant with displacement damage and ionization damage. What adopt due to the present invention is the neutron pre-irradiation method that introduces displacement damage, therefore current gain change and displacement damage relation is the closest.

Assuming that the surface recombination in formula (2) and emission effciency item are invariable, simultaneous equations can obtain Messenger Spratt formula:

$\mathrm{\Δ}\left(\frac{1}{\mathrm{\β}}\right)=\mathrm{\Δ}{\left(\frac{1}{\mathrm{\β}}\right)}_d=\frac{W^2}{2D_B}\·K_{\mathrm{\τ}}\·\mathrm{\Φ}---\left(3\right)$

In formula (3)Refer to the yield value change owing to displacement damage brings. Can illustrating, when bipolar transistor is subjected to displacement damage, the variable quantity reciprocal of its current gain is linear with irradiation fluence. The neutron fluence that this formula is suitable for ranges for 10⁹/cm²～10¹⁶/cm²。

2, the operating process refinement of the present invention

The flow process of neutron pre-irradiation experiment is as shown in Figure 3.

First, selecting 6 samples therein to carry out label in cmos device to be reinforced, carry out the neutron irradiation in advance of 6 different fluences respectively, the equivalent 1MeV neutron fluence that rule of thumb can select is 1 × 10¹²/cm²～1 × 10¹⁴/cm²Between 6 fluence values. Then, the device after neutron pre-irradiation is carried out population parameter test, obtain the situation of change of device property indices, remove function and abnormal device occurs and records the neutron fluence of correspondence, illustrate that the fluence of this neutron irradiation has exceeded the anti-neutron ability of device; Pick out the basically identical device of function, parameter maintenance and predose and record the neutron fluence of correspondence. Then, not neutron-irradiated device sample and 6 single event latchups done respectively under heavy ion irradiation environment by normally functioning device sample after neutron irradiation are tested, obtains the change curve in device single event latchup cross section before and after neutron irradiation. Finally, observe the situation of change of locking cross section curve, tentatively select the minimum neutron fluence neutron fluence as the best that locking does not even occur in locking cross section of device of sening as an envoy to.

It is important to note that the current gain that best neutron fluence is so that commercial cmos device parasitic bipolar transistor is reduced to " minimum neutron fluence " that single event latchup does not occur. as shown in Figure 4, 6 neutron fluences selected are different to the improvement degree of the anti-single particle locking of device, from " node 1 " to " node 6 " it is observed that device locking cross section is on a declining curve, neutron fluence corresponding to " node 5 " is a relatively obvious turning point, the locking cross section improvement of device is readily apparent that by the neutron fluence of its correspondence, and " node 6 " thereafter is inconspicuous compared to the improvement of " node 5 ", so we to select to meet " the minimum neutron fluence " of reinforcement criteria, the neutron fluence that namely " node 5 " is corresponding, standard neutron pre-irradiation fluence as this device.

If the neutron fluence of radiation is excessive, no doubt the decline of current gain can meet requirement, and obtains bigger safe clearance, but make input leakage current and quiescent power supply current in semiconductor integrated circuit increase to some extent simultaneously, and this is without wishing to the result seen. This is also the current demand selecting " minimum neutron fluence ".

The unexposed technology of the present invention belongs to general knowledge as well known to those skilled in the art.

Claims (2)

1. the reinforcement means of a cmos device anti-single particle locking, it is characterised in that:

Cmos device is carried out neutron irradiation, introduces displacement damage by neutron irradiation, make the current gain of device CMOS inverter endophyte bipolar transistor be reduced to and P-N-P-N locking will not occur.

2. the reinforcement means of cmos device anti-single particle locking according to claim 1, it is characterised in that:

The determination of neutron irradiation fluence carries out according to following steps:

1) select cmos device sample to be reinforced, device sample is carried out population parameter test, obtain the property indices parameter of device sample as reference standard;

2) selecting equivalence 1MeV neutron fluence is 1 × 10¹²/cm²～1 × 10¹⁴/cm²Between multiple fluence values;

3) select multiple cmos device sample to be reinforced, respectively in step 2) neutron fluence under carry out pre-irradiation experiment;

4) the cmos device sample multiple to be reinforced after pre-irradiation is tested is also carried out population parameter test, gets rid of performance indications and step 1) the inconsistent device of the reference standard surveyed;

5) to the intact device of function after neutron pre-irradiation and carry out the single event latchup experiment under identical heavy ion irradiation environment respectively without the sample of neutron pre-irradiation, the locking cross section curve after different neutron fluence predose is obtained;

6) locking cross section curve is analyzed, is met " the minimum neutron fluence " when reinforcement criteria, and using it reinforcing standard neutron irradiation fluence as this cmos device.