CN102130124A - Chip structure for preventing latch-up effect and method thereof - Google Patents
Chip structure for preventing latch-up effect and method thereof Download PDFInfo
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- CN102130124A CN102130124A CN 201010603955 CN201010603955A CN102130124A CN 102130124 A CN102130124 A CN 102130124A CN 201010603955 CN201010603955 CN 201010603955 CN 201010603955 A CN201010603955 A CN 201010603955A CN 102130124 A CN102130124 A CN 102130124A
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Abstract
The invention relates to a chip structure for preventing latch-up effect and a method thereof. The method comprises the following steps: adding nwell minority carrier guard rings between a driving module of a chip and other modules, enabling the concentration of a substrate which is near to the minority carrier rings to reduce, increasing the resistance of the substrate, and further preventing the generation of the latch-up effect in the chip. Further, the nwell minority carrier rings are connected with 0 potential. The chip structure mainly comprises the driving module and other modules with a digital-analog module, and the nwell minority carrier guard rings are loaded between the driving module and other modules. By adopting the chip structure and the method, the good effect of preventing the latch-up effect can be generated under the premise of not increasing the area of a layout, and the normal working performance of the chip can not be affected.
Description
Technical field
The present invention relates to chip structure and the method for a kind of latch of preventing up (latch-up) of technical field of integrated circuits.
Background technology
Along with the development of IC manufacturing process, Chip Packaging density and integrated level are more and more higher, and the possibility that produces latch up will be increasing.In general, the condition of generation latch up is: loop current gains greater than 1, β npn β pnp＞=1; Two BJT emitters all are in positively biased; Can form one at emitter and keep the big electric current of electric current than PNPN device.Drive circuit is owing to be big electric current on output stage, producing certain displacement current near meeting in the substrate of driving element, this electric current flows through low-pressure section, on dead resistance Rp, just have drop of potential, consult Fig. 1, when this electromotive force reaches certain value, this part parasitic horizontal triode Q1 is opened.The transistor of opening can amplify substrate current, electric current on the Q1 pipe collector is flowed in the trap, again the entozoic vertical triode Q2 of trap is opened, latch up structure is triggered, in case form this positive feedback path, power supply can make the heating of monoblock chip lose efficacy to the big electric current between the ground.For overcoming this problem; people generally adopt and add the how sub-guard ring of majority carrier (this guard ring ground connection) in driver module and other modules; increase the methods such as distance that drive with other intermodules; increase the methods such as distance (consulting Fig. 2) that drive with other intermodules, but this method can increase chip area.
Summary of the invention
The objective of the invention is to propose a kind of novel chip structure and method that can effectively prevent latch up, it is by realizing at the few sub-guard ring of adding nwell between driver module and other module majority carrier guard ring.
For achieving the above object, the present invention has adopted following technical scheme:
A kind of method that prevents latch-up; it is characterized in that this method is: between the driver module of chip and all the other modules, add nwell minority carrier guard ring, make that the substrate concentration near the minority carrier subring reduces; and the increase resistance substrate, thereby prevent to take place in the chip latch-up.
Particularly, described nwell minority carrier articulating 0 current potential.
A kind of chip structure that prevents latch-up mainly by driver module with comprise that all the other modules of digital module form, is characterized in that loading nwell minority carrier guard ring between described driver module and all the other modules.
Say described nwell minority carrier articulating 0 current potential further.
Description of drawings
Fig. 1 is the generation circuit diagram of latch-up;
Fig. 2 is for preventing the chip structure figure of latch-up in the prior art;
Fig. 3 is for preventing the chip structure figure of latch-up among the present invention;
Embodiment
At the existing deficiency that prevents the technical scheme of latch-up effect in the chip; the present invention proposes the scheme of adding nwell minority carrier guard ring between driver module and other module majority carrier guard ring that comprises digital module, as shown in Figure 3.
Because of the minority carrier guard ring is exactly the collection of carrying out electronics in advance, and the minority carrier guard ring degree of depth is darker, effect also be suitable obviously, it can reduce the current gain of parasitic horizontal triode Q1, i.e. β npn.
And majority carrier is corresponding, collects the hole.But because of being P type substrate, the hole must enter into substrate, and the majority carrier guard ring has reduced local resistance in essence.Added after the minority carrier guard ring, p+ type majority carrier guard ring is near from nwell, is more conducive to collect in advance, and effect will be more obviously.
Between driver module and other module, add nwell minority carrier guard ring; make the substrate concentration of close minority carrier subring reduce; and widen that driver module is the same with distance method between other modules can to increase resistance substrate, played the effect of anti-latch-up.And the present invention does not increase chip area.As shown in Figure 3, nwell minority carrier articulating 0 current potential can not only be avoided the phase mutual interference between the module, also can avoid the driving element substrate current to flow to the digital module power supply, do not influence the reliability of digital-to-analog circuit, can play the effect that absorbs substrate current simultaneously.
Below only be concrete exemplary applications of the present invention, protection scope of the present invention is not constituted any limitation.All employing equivalents or equivalence are replaced and the technical scheme that forms, all drop on rights protection scope of the present invention it.
Claims (4)
1. method that prevents latch-up; it is characterized in that; this method is: add nwell minority carrier guard ring between the driver module of chip and all the other modules; make the substrate concentration of close minority carrier subring reduce; and the increase resistance substrate, thereby prevent to take place in the chip latch-up.
2. the method that prevents latch-up according to claim 1 is characterized in that, described nwell minority carrier articulating 0 current potential.
3. chip structure that prevents latch-up mainly by driver module with comprise that all the other modules of digital module form, is characterized in that loading nwell minority carrier guard ring between described driver module and all the other modules.
4. the chip structure that prevents latch-up according to claim 3 is characterized in that, described nwell minority carrier articulating 0 current potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010603955 CN102130124A (en) | 2010-12-24 | 2010-12-24 | Chip structure for preventing latch-up effect and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010603955 CN102130124A (en) | 2010-12-24 | 2010-12-24 | Chip structure for preventing latch-up effect and method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102130124A true CN102130124A (en) | 2011-07-20 |
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Family Applications (1)
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| CN 201010603955 Pending CN102130124A (en) | 2010-12-24 | 2010-12-24 | Chip structure for preventing latch-up effect and method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104319286A (en) * | 2014-11-04 | 2015-01-28 | 北京奥贝克电子股份有限公司 | Device structure applicable to bulk silicon CMOS and capable of restraining parasitic latch-up effect |
| CN105552073A (en) * | 2015-12-14 | 2016-05-04 | 武汉芯昌科技有限公司 | Chip layout structure and method for preventing latch up effects and noise interference |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7167350B2 (en) * | 2003-11-14 | 2007-01-23 | Texas Instruments Incorporated | Design implementation to suppress latchup in voltage tolerant circuits |
| CN100474578C (en) * | 2005-12-06 | 2009-04-01 | 上海华虹Nec电子有限公司 | Electrostatic-proof protection structure using NMOS |
-
2010
- 2010-12-24 CN CN 201010603955 patent/CN102130124A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7167350B2 (en) * | 2003-11-14 | 2007-01-23 | Texas Instruments Incorporated | Design implementation to suppress latchup in voltage tolerant circuits |
| CN100474578C (en) * | 2005-12-06 | 2009-04-01 | 上海华虹Nec电子有限公司 | Electrostatic-proof protection structure using NMOS |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104319286A (en) * | 2014-11-04 | 2015-01-28 | 北京奥贝克电子股份有限公司 | Device structure applicable to bulk silicon CMOS and capable of restraining parasitic latch-up effect |
| CN104319286B (en) * | 2014-11-04 | 2017-12-01 | 北京奥贝克电子股份有限公司 | A kind of device architecture that can suppress parasitic latch-up suitable for Bulk CMOS |
| CN105552073A (en) * | 2015-12-14 | 2016-05-04 | 武汉芯昌科技有限公司 | Chip layout structure and method for preventing latch up effects and noise interference |
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Application publication date: 20110720 |