CN105551702A - Chip resistor array vacuum coating method - Google Patents
Chip resistor array vacuum coating method Download PDFInfo
- Publication number
- CN105551702A CN105551702A CN201511016634.7A CN201511016634A CN105551702A CN 105551702 A CN105551702 A CN 105551702A CN 201511016634 A CN201511016634 A CN 201511016634A CN 105551702 A CN105551702 A CN 105551702A
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- China
- Prior art keywords
- resistance
- substrate
- chip array
- taeniae
- vacuum film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/28—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
- H01C17/288—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals by thin film techniques
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/04—Coating on selected surface areas, e.g. using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
- H01C17/065—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thick film techniques, e.g. serigraphy
- H01C17/06506—Precursor compositions therefor, e.g. pastes, inks, glass frits
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
The invention discloses a chip resistor array vacuum coating method. The chip resistor array vacuum coating method comprises the following steps: substrate preparation: preparing a substrate, wherein a plurality of holes are distributed uniformly in the substrate in an array manner, and every three holes are vertically arranged as one group; step C2, step C1, step RS, step G1, step LT, step G2, stacking, cutting off to obtain grains, electroplating, testing and packaging. By mean of the chip resistor array vacuum coating method, due to improvement of techniques, a problem that grooves of a resistor array are easy to sputter can be effectively solved, so that a vacuum coating technique instead of a rolling-soaking silver coating manner is utilized to perform silver coating on an end face of a chip resistor array, and the quality of products and the production efficiency are improved.
Description
Technical field
The present invention relates to production of electronic components field, be specifically related to a kind of chip array resistance vacuum film plating process.
Background technology
At Chip-R production field, there is groove because of substrate in chip array resistance and network resistor, end silver coating generally adopts end face to roll to be stained with and is coated with silver-colored mode, namely uses sponge roller evenly to dip silver-colored ink, then rotates the end face that silver-colored ink is coated in resistor by sponge roller.But the silver-colored mode of this painting needs to rely on artificial ceaselessly inspection to be coated with silver-colored effect aborning, and production efficiency is lower, and labour intensity is comparatively large, and the cost of raw material is higher, and more difficult to govern control is coated with silver-colored effect, and yields is lower; And in the silver-colored process of painting, be easily coated onto in the groove of chip array resistance.Thus, chip array resistance is improved and network resistor end silver coating technology is one of most important research topic of Chip-R production field.Vacuum coating technology mainly utilizes glow discharge (glowdischarge) by argon gas (Ar) ionic bombardment target material surface, and the atom of target is ejected and is deposited in substrate surface formation film.Product coating film thickness through vacuum splashing and plating is even, and yields is high, and product quality is good, and production efficiency is high, and production cost is low, will more and more be widely used in Chip-R production field.But in the production of chip array resistance and network resistor, at present and carry out silver-plated there are no employing vacuum coating technology, tracing it to its cause is that substrate due to chip array resistance and network resistor exists groove, according to vacuum coating technology, is easily arrived by sputter in groove.
Summary of the invention
For deficiency of the prior art, the object of the present invention is to provide a kind of chip array resistance vacuum film plating process, the method effectively can solve the problem that arrangement resistance groove is easily sputtered to, thus make the end silver coating of chip array resistance use vacuum coating technology replace roll be stained be coated with silver-colored mode, improving product quality status, enhances productivity.
For achieving the above object, technical scheme disclosed by the invention is as follows: a kind of chip array resistance vacuum film plating process, and it comprises the following steps:
Substrate prepares: get one piece of substrate, and on this substrate, homogeneous matrix formula distributes some holes, and wherein every three hole vertical array are as one group;
Step C2: at the back up conductor of substrate;
Step C1: at the front printed conductor of substrate;
Step RS: at the front printed resistor of substrate, the position of resistance is between two printed conductors that substrate front side is adjacent;
Step G1: after step RS terminates, printed resistor layer protective layer on substrate, described resistive layer protective layer covers on the resistance printed by step RS;
Step LT: radium-shine cutting resistance, adjusting resistance value;
Step G2: print laser protective layer, described radium-shine protective layer covers whole resistance and covers radium-shine cutting mouth;
End silver: substrate is divided into some taeniaes, every root taeniae comprises multiple resistance unit; Arranged in stacking tool by multiple taeniae, the groove of the same position on the resistance unit now on adjacent taeniae discharges side by side, forms some slot sticks; Magnet is provided with at the back side of stacking tool, then the bar column be made of a steel hides bar and hides some slot sticks, under about the suction of magnet, bar column hides bar and firmly sucks in some slot sticks, thus covers in the groove on each resistance unit on every root taeniae completely; Then silver-plated through the side of vacuum coating equipment to each taeniae, the side by each resistance unit on each taeniae is silver-plated;
Folding grain: every root taeniae is fractureed, obtains some graininess resistance units;
Plating: by some graininess resistance unit first nickel plating in surface, and then zinc-plated, obtain finished product chip array resistance;
Testing package: finished product chip array resistance is carried out resistance mensuration one by one, packs after test passes.
In the present invention, in described step RS printed resistor resistance required for resistance be allotment gained by resistance printing ink, it is required resistance-40%-0% Inner that resistance is completed for printing rear Standard resistance range.
Preferably, described substrate is ceramic substrate.The size of substrate described in the present invention is long: 3.2 ± 0.20, wide: 1.6 ± 0.15, high by 0.50 ± 0.10.
Preferably, in described step C2, during printed conductor, print thickness is 31 ± 10 μm.
Preferably, in described step C1, during printed conductor, print thickness is 25 ± 10 μm.
Preferably, in described step RS, resistance print thickness is 20 ± 10mm.
Preferably, in described step G1, the print thickness of resistive layer protective layer is 20 ± 10 μm.
Preferably, in described step G2, the thickness of print laser protective layer is 20 ± 10mm.Print laser protective layer material used is G2 ink material.
Preferably, in described end silver process, impedance :≤65 Ω of each resistance unit both sides coating.
Preferably, in described electroplating process, the thickness of each resistance unit plated surface nickel dam is between 5.0-6.0 μm.
Preferably, in described electroplating process, the thickness of each resistance unit Zinc coat is between 7.0-8.0 μm.
On the substrate adopted in the present invention, former design band is fluted, therefore after holding the operation such as silver, folding grain, each resistance unit can be with fluted.
Hidden design and the use of bar by magnetic stack tool and bar column in the present invention, effective in vacuum coating process, ohmically for chip array resistance groove to be hidden, thus achieve can not by silver slurry on sputter in resistance groove in vacuum coating process.
The invention has the beneficial effects as follows: the present invention passes through process modification, effectively can solve the problem that arrangement resistance groove is easily sputtered to, thus make the end silver coating of chip array resistance use vacuum coating technology replace roll be stained be coated with silver-colored mode, improving product quality status, enhances productivity.
Accompanying drawing explanation
Fig. 1 is the structural representation of substrate in a preferred embodiment of the present invention;
Fig. 2 is the structural representation in step C2 after printed conductor;
Fig. 3 is the structural representation in step C1 after printed conductor;
Fig. 4 is the structural representation in step RS after printed resistor layer;
Fig. 5 is the structural representation of printed resistor layer protective layer in step G1;
Fig. 6 is the structural representation in step LT after radium-shine cutting;
Fig. 7 is the structural representation of print laser protective layer in step G2;
Fig. 8 is structural representation substrate being cut into single taeniae after multiple taeniae;
Fig. 9 is the side structure schematic diagram of taeniae before vacuum coating;
Figure 10 is the side structure schematic diagram of taeniae after vacuum coating;
Figure 11 is resistor unit electroplating process schematic diagram after folding grain;
Figure 12 is front, the inverse layer structure schematic diagram that plating terminates rear each resistance unit;
Figure 13 is the side structure schematic diagram that plating terminates rear each resistance unit.
Embodiment
Below in conjunction with accompanying drawing, preferred embodiment of the present invention is described in detail, can be easier to make advantages and features of the invention be readily appreciated by one skilled in the art, thus more explicit defining is made to protection scope of the present invention.
Please refer to accompanying drawing 1 to accompanying drawing 13:
embodiment 1:a kind of chip array resistance vacuum film plating process, it comprises the following steps:
Substrate prepares: get one piece of substrate 1, and on this substrate 1, homogeneous matrix formula distributes some holes 10, and wherein every three hole vertical array are as one group;
Step C2: at the back up conductor 20 of substrate, see accompanying drawing 2;
Step C1: at the front printed conductor 21 of substrate, see accompanying drawing 3;
Step RS: at the front printed resistor 22 of substrate, the position of resistance 22 is between two printed conductors that substrate front side is adjacent, sees Fig. 4;
Step G1: after step RS terminates, on substrate 1 printed resistor layer protective layer 23, resistive layer protective layer 23 covers on the resistance 22 printed by step RS, sees Fig. 5;
Step LT: radium-shine cutting resistance, adjusting resistance value; Radium-shine cutting mouth 24, is shown in Fig. 6;
Step G2: print laser protective layer 25, radium-shine protective layer 25 covers whole resistance and covers radium-shine cutting mouth 24, sees Fig. 7;
End silver: substrate is divided into some taeniaes, every root taeniae comprises multiple resistance unit; Arranged in stacking tool by multiple taeniae, the groove of the same position on the resistance unit now on adjacent taeniae discharges side by side, forms some slot sticks; Magnet is provided with at the back side of stacking tool, then the bar column be made of a steel hides bar and hides some slot sticks, under about the suction of magnet, bar column hides bar and firmly sucks in some slot sticks, thus covers in the groove on each resistance unit on every root taeniae completely; Then silver-plated through the side of vacuum coating equipment to each taeniae, the side by each resistance unit on each taeniae is silver-plated;
Folding grain: every root taeniae is fractureed, obtains some graininess resistance units 2;
Plating: by some graininess resistance unit first nickel plating in surface, and then zinc-plated, obtain finished product chip array resistance;
Testing package: finished product chip array resistance is carried out resistance mensuration one by one, packs after test passes.
In the present embodiment, substrate is ceramic substrate, and the size of substrate is long: 3.2 ± 0.20, wide: 1.6 ± 0.15, high by 0.50 ± 0.10.
embodiment 2:the difference of the present embodiment and embodiment 1 is, in the present embodiment, in step C2, during printed conductor, print thickness is 31 ± 10 μm; In step C1, during printed conductor, print thickness is 25 ± 10 μm; In step RS, resistance print thickness is 20 ± 10 μm; In step G1, the print thickness of resistive layer protective layer is 20 ± 10 μm; In step G2, the thickness of print laser protective layer is 20 ± 10 μm.
embodiment 3:the difference of the present embodiment and embodiment 1 is, in the present embodiment, holds in silver-colored process, impedance :≤65 Ω of each resistance unit both sides coating; In electroplating process, the thickness of each resistance unit plated surface nickel dam is between 5.0-6.0 μm; The thickness of each resistance unit Zinc coat is between 7.0-8.0 μm.
embodiment 4:the difference of the present embodiment and embodiment 1 is, in the present embodiment, in step C2, during printed conductor, print thickness is 31 μm; In step C1, during printed conductor, print thickness is 25 μm; In step RS, resistance print thickness is 20 μm; In step G1, the print thickness of resistive layer protective layer is 20 μm; In step G2, the thickness of print laser protective layer is 20 μm.
embodiment 5:the difference of the present embodiment and embodiment 1 is, in the present embodiment, in step C2, during printed conductor, print thickness is 21 μm; In step C1, during printed conductor, print thickness is 35 μm; In step RS, resistance print thickness is 10 μm; In step G1, the print thickness of resistive layer protective layer is 30 μm; In step G2, the thickness of print laser protective layer is 10 μm.
embodiment 6:the difference of the present embodiment and embodiment 1 is, in the present embodiment, in step C2, during printed conductor, print thickness is 41 μm; In step C1, during printed conductor, print thickness is 15 μm; In step RS, resistance print thickness is 30 μm; In step G1, the print thickness of resistive layer protective layer is 10 μm; In step G2, the thickness of print laser protective layer is 30 μm.
embodiment 7:the difference of the present embodiment and embodiment 1 is, in the present embodiment, holds in silver-colored process, impedance :≤65 Ω of each resistance unit both sides coating; In electroplating process, the thickness of each resistance unit plated surface nickel dam is 5.41 ± 1 μm; The thickness of each resistance unit Zinc coat is 7.48 ± 1 μm.
embodiment 8:the difference of the present embodiment and embodiment 1 is, in the present embodiment, holds in silver-colored process, impedance :≤65 Ω of each resistance unit both sides coating; In electroplating process, the thickness of each resistance unit plated surface nickel dam is 5 μm; The thickness of each resistance unit Zinc coat is 7 μm.
embodiment 9:the difference of the present embodiment and embodiment 1 is, in the present embodiment, holds in silver-colored process, impedance :≤65 Ω of each resistance unit both sides coating; In electroplating process, the thickness of each resistance unit plated surface nickel dam is 6 μm; The thickness of each resistance unit Zinc coat is 8 μm.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (10)
1. a chip array resistance vacuum film plating process, is characterized in that, it comprises the following steps:
Substrate prepares: get one piece of substrate, and on this substrate, homogeneous matrix formula distributes some holes, and wherein every three hole vertical array are as one group;
Step C2: at the back up conductor of substrate;
Step C1: at the front printed conductor of substrate;
Step RS: at the front printed resistor of substrate, the position of resistance is between two printed conductors that substrate front side is adjacent;
Step G1: after step RS terminates, printed resistor layer protective layer on substrate, described resistive layer protective layer covers on the resistance printed by step RS;
Step LT: radium-shine cutting resistance, adjusting resistance value;
Step G2: print laser protective layer, described radium-shine protective layer covers whole resistance and covers radium-shine cutting mouth;
Stacking: substrate is divided into some taeniaes, every root taeniae comprises multiple resistance unit; Arranged in stacking tool by multiple taeniae, the groove of the same position on the resistance unit now on adjacent taeniae discharges side by side, forms some slot sticks; Magnet is provided with at the back side of stacking tool, then the bar column be made of a steel hides bar and hides some slot sticks, under about the suction of magnet, bar column hides bar and firmly sucks in some slot sticks, thus covers in the groove on each resistance unit on every root taeniae completely; Then through the side Du Silver of vacuum coating equipment to each taeniae, the side by each resistance unit on each taeniae is silver-plated;
Folding grain: every root taeniae is fractureed, obtains some graininess resistance units;
Plating: by some graininess resistance unit first nickel plating in surface, and then zinc-plated, obtain finished product chip array resistance;
Testing package: finished product chip array resistance is carried out resistance mensuration one by one, packs after test passes.
2. chip array resistance vacuum film plating process according to claim 1, it is characterized in that, described substrate is ceramic substrate.
3. chip array resistance vacuum film plating process according to claim 1, is characterized in that, in described step C2, during printed conductor, print thickness is 31 ± 10 μm.
4. chip array resistance vacuum film plating process according to claim 1, is characterized in that, in described step C1, during printed conductor, print thickness is 25 ± 10 μm.
5. chip array resistance vacuum film plating process according to claim 1, is characterized in that, in described step RS, resistance print thickness is 20 ± 10 μm.
6. chip array resistance vacuum film plating process according to claim 1, is characterized in that, in described step G1, the print thickness of resistive layer protective layer is 20 ± 10 μm.
7. chip array resistance vacuum film plating process according to claim 1, is characterized in that, in described step G2, the thickness of print laser protective layer is 20 ± 10 μm.
8. chip array resistance vacuum film plating process according to claim 1, is characterized in that, in described end silver process, and impedance :≤65 Ω of each resistance unit both sides coating.
9. chip array resistance vacuum film plating process according to claim 1, is characterized in that, in described electroplating process, the thickness of each resistance unit plated surface nickel dam is between 5.0-6.0 μm.
10. chip array resistance vacuum film plating process according to claim 1, is characterized in that, in described electroplating process, the thickness of each resistance unit Zinc coat is between 7.0-8.0 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511016634.7A CN105551702B (en) | 2015-12-31 | 2015-12-31 | A kind of chip array resistance vacuum film plating process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511016634.7A CN105551702B (en) | 2015-12-31 | 2015-12-31 | A kind of chip array resistance vacuum film plating process |
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| CN105551702A true CN105551702A (en) | 2016-05-04 |
| CN105551702B CN105551702B (en) | 2018-07-20 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108335811A (en) * | 2018-01-30 | 2018-07-27 | 旺诠科技(昆山)有限公司 | A method of producing reverse side concave electrode thick film chip resistor |
| CN108346494A (en) * | 2018-01-30 | 2018-07-31 | 旺诠科技(昆山)有限公司 | A kind of chip resister and its production technology improving resistance printing |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10199703A (en) * | 1997-01-08 | 1998-07-31 | Hokuriku Electric Ind Co Ltd | Manufacture of substrate for chip resistor, and chip resistor |
| JP2005026525A (en) * | 2003-07-03 | 2005-01-27 | Shinko Electric Ind Co Ltd | Wiring board and method of manufacturing the same |
| CN101950645A (en) * | 2010-08-27 | 2011-01-19 | 广东风华高新科技股份有限公司 | Chip overvoltage protector and manufacturing method thereof |
| CN202601344U (en) * | 2012-06-05 | 2012-12-12 | 广东风华高新科技股份有限公司 | Erosion-resisting chip resistor |
-
2015
- 2015-12-31 CN CN201511016634.7A patent/CN105551702B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10199703A (en) * | 1997-01-08 | 1998-07-31 | Hokuriku Electric Ind Co Ltd | Manufacture of substrate for chip resistor, and chip resistor |
| JP2005026525A (en) * | 2003-07-03 | 2005-01-27 | Shinko Electric Ind Co Ltd | Wiring board and method of manufacturing the same |
| CN101950645A (en) * | 2010-08-27 | 2011-01-19 | 广东风华高新科技股份有限公司 | Chip overvoltage protector and manufacturing method thereof |
| CN202601344U (en) * | 2012-06-05 | 2012-12-12 | 广东风华高新科技股份有限公司 | Erosion-resisting chip resistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108335811A (en) * | 2018-01-30 | 2018-07-27 | 旺诠科技(昆山)有限公司 | A method of producing reverse side concave electrode thick film chip resistor |
| CN108346494A (en) * | 2018-01-30 | 2018-07-31 | 旺诠科技(昆山)有限公司 | A kind of chip resister and its production technology improving resistance printing |
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| Publication number | Publication date |
|---|---|
| CN105551702B (en) | 2018-07-20 |
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