CN105529304A - 半导体装置与其制造方法 - Google Patents

半导体装置与其制造方法 Download PDF

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Publication number
CN105529304A
CN105529304A CN201410524797.5A CN201410524797A CN105529304A CN 105529304 A CN105529304 A CN 105529304A CN 201410524797 A CN201410524797 A CN 201410524797A CN 105529304 A CN105529304 A CN 105529304A
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layer
dielectric layer
dielectric
semiconductor devices
metal level
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CN105529304B (zh
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蔡世昌
曾姿锦
林筱婷
陈长义
赖龙山
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US14/515,514 priority patent/US9312357B1/en
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Abstract

本发明公开一种半导体装置与其制造方法。制造半导体装置的方法，包括以下步骤：提供一基板，并在其上方形成第一介电层。第一介电层具有一沟槽。接着，形成金属层，其填入沟槽并且覆盖第一介电层的表面。部分移除金属层，使得金属层的剩余部分覆盖第一介电层。进行处理程序，使得金属层的剩余部分的上部分形成钝化层以及下部分形成栅极金属层。最后，进行化学机械研磨程序，直到露出第一介电层为止，使得钝化层的剩余部分留在沟槽中。

Description

半导体装置与其制造方法
技术领域
本发明涉及一种半导体程序技术，尤其是涉及一种半导体装置与其制造方法。
背景技术
集成电路程序技术不断演进的动力在于金属氧化物半导体场效晶体管(metal-oxide-semiconductorfield-effecttransistor,MOSFET)尺寸不断地缩小化，以满足提升元件切换速度、降低元件消耗功率以及提高电路的元件积成密度等要求。高介电常数金属栅极(high-kmetalgate,HKMG)技术促进晶体管尺寸缩小化并且由于栅极漏电流减小而降低功率损耗。
在HKMG技术领域中，通常以铝作为金属栅极的导电材料。金属栅极的电阻值(Rs_MG)会随着金属栅极中铝的厚度减少而增加，而使得元件的特性受到金属栅极中铝的程序参数变动的影响。例如，对于输入/输出元件来说，其栅极面积大于核心元件的栅极面积，因此在化学机械研磨(chemical-mechanicalpolishing,CMP)的平坦化程序时，由于研磨图案密度的不同，造成图案密度低区域(即输入/输出元件的栅极区域)会有过度抛光所造成的浅碟化(dishing)效应，导致金属栅极的电阻值Rs_MG由于金属栅极中铝的厚度减少而增加，造成临界电压(thresholdvoltage,Vt)提高与导通电流(turn-oncurrent,Ion)下降的现象。甚至，由于金属栅极的浅碟化效应，导致成对的输入/输出元件因为金属栅极厚度不一，而发生临界电压不匹配(Vtmismatch)的现象。上述两种状况均会造成半导体芯片的损坏。
为了克服化学机械研磨程序所造成的金属栅极浅碟化效应而导致的上述缺失，亟需提供一种半导体装置与其制造方法，以避免半导体芯片的损坏。
发明内容
本发明的一目的在于提供一种半导体装置与其制造方法，通过在进行金属栅极的化学机械研磨程序之前，对于金属栅极进行一道处理程序，以避免浅碟化效应的发生，而造成元件特性受到影响。
本发明的另一目的在于提供一种半导体装置与其制造方法，通过在进行金属栅极的化学机械研磨程序之前，对于金属栅极进行一道处理程序，以提升成对的大面积元件的临界电压匹配度。
为达成上述目的，在一具体实施例中，本发明提供一种制造半导体装置的方法，包括以下步骤：提供一基板，并在其上方形成第一介电层。第一介电层具有一沟槽。接着，形成金属层，其填入沟槽并且覆盖第一介电层的表面。部分移除金属层，使得金属层的剩余部分覆盖第一介电层。进行处理程序，使得金属层的剩余部分的上部分形成钝化层以及下部分形成栅极金属层。最后，进行化学机械研磨程序，直到露出第一介电层为止，使得钝化层的剩余部分留在沟槽中。
为达成上述目的，在另一具体实施例中，本发明还提供一种半导体装置，包括基板，其上方形成第一介电层以及栅极结构。栅极结构包括由下而上依序形成的栅极介电层、栅极金属层以及钝化层。其中钝化层为一种化合物，其包括构成栅极金属层的材料的元素。
附图说明
为让本发明的上述和其他目的、特征和优点能更明显易懂，下文特举优选实施例，并配合所附的附图，作详细说明如下。其中：
图1A至图1E为本发明一具体实施例的一种制造半导体装置的方法的流程示意图。
符号说明
100半导体装置
110基板
111n通道金属氧化物半导体场效晶体管
1111源/漏极
112p通道金属氧化物半导体场效晶体管
1121源/漏极
113浅沟槽隔离结构
120第一介电层
121第二介电层
122堆叠层
123堆叠层
124间隔层
125沟槽
126栅极介电层
127堆叠层
128堆叠层
130金属层
131金属层的剩余部分
132钝化层
133栅极金属层
134钝化层的剩余部分
140栅极结构
具体实施方式
为说明本发明的要义，请参阅图1A至图1E，其为本发明一具体实施例的一种制造半导体装置100的方法的流程示意图。
首先，如图1A所示，提供基板110，其上方形成第一介电层120。第一介电层120具有至少一沟槽125。在一些具体实施例中，基板110可为硅基板、III-V族半导体基板、蓝宝石(sapphire)基板、绝缘层上有硅(silicononInsulator,SOI)基板、或其他各种上面提供有电子元件的基板。举例而言，如图1A所示，在本具体实施例中，基板110为一硅基板，其具有至少一n通道金属氧化物半导体场效晶体管(MOSFET)111以及至少一p通道金属氧化物半导体场效晶体管112，每两相邻晶体管通过一个浅沟槽隔离(shallowtrenchisolation,STI)结构113而隔开。在本具体实施例中，第一介电层120为氧化层或其他可由沉积方式形成的低介电常数(low-k)介电层。举例而言，第一介电层120可为碳掺杂的氧化层。此外，沟槽125由间隔层(spacer)124的侧壁所定义。间隔层124可由，例如，氮化物所构成。在图1A中，n通道金属氧化物半导体场效晶体管111的源/漏极1111由掺杂五族元素，例如磷(P)，硅所构成，并且在源/漏极1111之间的通道中产生拉伸应力(tensilestrain)，来增加电子迁移率。相对地，p通道金属氧化物半导体场效晶体管112的源/漏极1121由硅锗(SiGe)所构成。因为硅锗的晶格比硅晶格大，以硅锗取代硅的源/漏极1121会压缩通道，并且在源/漏极1121之间的通道中产生压缩应力(compressivestrain)，来增加空穴迁移率。
此外，在一些具体实施例中，可进一步依序形成第二介电层121与堆叠层122与123，覆盖第一沟槽125的底部、间隔层124的侧壁以及第一介电层120的表面。其中，第二介电层121可为高介电常数介电层，例如，铪基(hafnium-based)介电层，如氧化铪(HfO2)、硅氧化铪(HfSiO)等。堆叠层122与123包括阻障层以及功函数金属层。举例来说，在n通道金属氧化物半导体场效晶体管111的堆叠层122中，阻障层可包括氮化钛(TiN)层以及氮化钽(TaN)层，功函数金属层可包括钛铝(TiAl)合金层。在p通道金属氧化物半导体场效晶体管112的堆叠层123中，阻障层可包括氮化钛(TiN)层以及氮化钽(TaN)层，功函数金属层可包括两层结构，由上层的钛铝(TiAl)合金层以及下层的氮化钛(TiN)层组成。然而，本发明并不限于上述结构，本技术领域中具有通常技术的人士当可在本发明的范围内作出其他修正。
接着，如图1B所示，形成金属层130，其填入沟槽125并且覆盖第一介电层120的表面。在一些具体实施例中，金属层130为铝、钨或铜。然而，本发明并不限于金属层130的材料，本技术领域中具有通常技术的人士当可在本发明的范围内作出其他修正。
如图1C所示，部分移除金属层130，使得金属层的剩余部分131覆盖第一介电层120。在一些具体实施例中，部分移除金属层130可以通过蚀刻或化学机械研磨等程序完成，而剩余部分131的厚度一般小于20nm。优选者，剩余部分131的厚度可小于10nm。
接着，在图1D中，进行一处理程序，使得金属层的剩余部分131的上部分形成钝化层132以及下部分形成栅极金属层133。如图1D中所示，栅极金属层133的形状为块状(bulkshape)。在一些具体实施例中，处理程序可通过等离子体辅助氧化或等离子体辅助氮化而进行。因此，钝化层132为一种化合物，其包括构成栅极金属层133的材料的元素。详而言之，钝化层132可为金属氧化物或金属氮化物。
最后，如图1E所示，进行化学机械研磨程序，直到露出第一介电层120为止，使得钝化层132的剩余部分134留在沟槽125中。在一些具体实施例中，钝化层132的剩余部分134的厚度一般小于10nm。优选者，剩余部分134的厚度介于2nm至8nm。
此外，在一些具体实施例中，可进一步形成一接触插塞(未示于图中)，其穿透钝化层的剩余部分134而连接栅极金属层133。
在完成上述图1A至图1E所示的步骤之后，可以形成如图1E所示的半导体装置100，其包括基板110，其上方形成第一介电层120以及栅极结构140。栅极结构140包括由下而上依序形成的栅极介电层126、栅极金属层133以及钝化层134。其中钝化层134系为一种化合物，其包括构成栅极金属层133的材料的元素。
在一些具体实施例中，栅极结构140由间隔层124的侧壁所定义。栅极介电层126与栅极金属层133之间还包括堆叠层127与128，且栅极介电层126与堆叠层127与128沿着间隔层124的侧壁与底部而呈现U型。此外，半导体装置100还可包括一接触插塞(未示于图中)，其穿透钝化层134而连接栅极金属层133。值得注意的是，在图1E所示的本发明具体实施例中，所形成的栅极结构为一种高介电质后(high-klast)栅极结构。本发明所揭的方法并不局限于上述实施例，亦即，本发明的方法也可使用来制造具有高介电质先(high-kfirst)栅极结构的半导体装置。
通过本发明的实施，由于形成了图1E所示的半导体装置100的钝化层134，可以避免半导体装置的栅极区域过度抛光所造成栅极金属的浅碟化效应，除了可以改善现有技术中，高临界电压而低导通电流的不佳特性之外，更可以使成对的输入/输出元件因为临界电压匹配状况获得改善，而避免半导体芯片受到损害。
值得注意的是，在进行钝化层132的化学机械研磨程序时，即使栅极区域的钝化层132发生浅碟化效应，其下方的栅极金属层133的厚度并不会受到改变。因此，依然能够维持良好的电气特性以及临界电压匹配。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作各种的更动与润饰，因此本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (20)

1.一种制造半导体装置的方法，包括以下步骤：
提供一基板，其上方形成一第一介电层，该第一介电层具有一沟槽；
形成一金属层，该金属层填入该沟槽并且覆盖该第一介电层的表面；
部分移除该金属层，使得该金属层的一剩余部分覆盖该第一介电层；
进行一处理程序，使得该金属层的该剩余部分的一上部分形成一钝化层以及一下部分形成一栅极金属层；以及
进行一化学机械研磨程序，直到露出该第一介电层为止，使得该钝化层的一剩余部分留在该沟槽中。
2.如权利要求1所述的方法，其中该沟槽由一间隔层的侧壁所定义。
3.如权利要求2所述的方法，还包括在形成该金属层之前的一步骤：依序形成一第二介电层与一堆叠层，覆盖该第一沟槽的底部、该间隔层的侧壁以及该第一介电层的表面。
4.如权利要求1所述的方法，还包括一步骤：形成一接触插塞，其穿透该钝化层的该剩余部分而连接该栅极金属层。
5.如权利要求1所述的方法，其中该第一介电层为一氧化层。
6.如权利要求3所述的方法，其中该第二介电层为一高介电常数介电层。
7.如权利要求2所述的方法，其中该间隔层为一氮化层。
8.如权利要求1所述的方法，其中该处理程序通过等离子体辅助氧化或等离子体辅助氮化而进行。
9.如权利要求1所述的方法，其中该金属层为铝、钨或铜。
10.如权利要求1所述的方法，其中该金属层的该剩余部分的厚度小于20nm。
11.如权利要求1所述的方法，其中该钝化层的该剩余部分的厚度小于10nm。
12.一种半导体装置，包括：
基板，其上方形成第一介电层以及栅极结构，该栅极结构包括由下而上依序形成的栅极介电层、栅极金属层以及钝化层；
其中该钝化层为一化合物，该化合物包括构成该栅极金属层的材料的元素。
13.如权利要求12所述的半导体装置，其中该栅极结构由一间隔层的侧壁所定义。
14.如权利要求13所述的半导体装置，其中该栅极介电层与该栅极金属层之间还包括堆叠层，且该栅极介电层与该堆叠层沿着该间隔层的侧壁与底部而呈现U型。
15.如权利要求12所述的半导体装置，还包括接触插塞，其穿透该钝化层而连接该栅极金属层。
16.如权利要求12所述的半导体装置，其中该第一介电层为氧化层。
17.如权利要求12所述的半导体装置，其中该第二介电层为高介电常数介电层。
18.如权利要求13所述的半导体装置，其中该间隔层为氮化层。
19.如权利要求12所述的半导体装置，其中该金属层为铝、钨或铜。
20.如权利要求12所述的半导体装置，其中该钝化层的厚度小于10nm。
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