CN105529298A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN105529298A
CN105529298A CN201410561454.6A CN201410561454A CN105529298A CN 105529298 A CN105529298 A CN 105529298A CN 201410561454 A CN201410561454 A CN 201410561454A CN 105529298 A CN105529298 A CN 105529298A
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metal layer
layer
aluminum metal
platinum metal
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吕信谊
王镇和
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。其制作方法包括：首先提供一基底，且基底具有一介电层，然后形成一铝金属层于介电层上，形成一铂金属层于铝金属层上，进行一第一蚀刻制作工艺去除部分铂金属层及部分铝金属层以形成一图案化的铂金属层，之后再进行一第二蚀刻制作工艺去除部分由图案化的铂金属层所暴露出的铝金属层及部分介电层。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种利用铝金属层为蚀刻停止层来图案化铂金属层的方法。
背景技术
微机电(microelectromechanicalsystems,MEMS)装置包括具有微机电的基板与微电子电路整合在一起。此种装置可形成例如微感应器(microsensors)或微驱动器(microactuators)，其基于例如电磁、电致伸缩(electrostrictive)、热电、压电、压阻(piezoresistive)等效应来操作。MEMS装置可通过微电子技术例如光刻、气相沉积、及蚀刻等，在绝缘层或其他的基板上制得。近来，有使用与现有的模拟及数字CMOS(互补式金属氧化物半导体)电路的同类型的制造步骤(例如材料层的沉积与材料层的选择性移除)来制造MEMS。
铂金属由于其特有化学稳定度以及具有抗氧化等特性，因此已广泛使用于超大型集成电路与微机电领域中作为电热、湿度以及气体侦测器。此外，铂金属又因具有高功函数且在与介电材料的交界面可针对电子的传输产生高电荷阻障屏蔽，因此可用来抑止漏电流。然而，现今对铂金属进行图案化的过程中时常因蚀刻的力道无法被有效控制而造成均一度不佳及底下的介电材料耗损等问题。因此如何改良现行制作工艺即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例是公开一种制作半导体元件的方法。首先提供一基底，且基底具有一介电层，然后形成一铝金属层于介电层上，形成一铂金属层于铝金属层上，进行一第一蚀刻制作工艺去除部分铂金属层及部分铝金属层以形成一图案化的铂金属层，之后再进行一第二蚀刻制作工艺去除部分由图案化的铂金属层所暴露出的铝金属层及部分介电层。
本发明另一实施例公开一种半导体元件，包含一基底，该基底具有一介电层；一铝金属层设于介电层上；以及一铂金属层设于铝金属层上。
附图说明
图1至图4为本发明优选实施例制作一半导体元件的方法示意图。
主要元件符号说明
12基底14导电堆叠层
16介电层18金属层
20接触孔22金属间介电层
24导电区26铝金属层
28阻障层30铂金属层
具体实施方式
请参照图1至图4，图1至图4为本发明优选实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一由硅、硅覆绝缘材料、外延层、硅锗层或其他半导体材料所构成的基底。基底12中可包含至少一导电堆叠层14与至少一介电层16设于导电堆叠层14上，其中导电堆叠层14可包含一由金属层18、接触孔20、金属间介电层22以及导电区24等元件所构成的堆叠结构。在本实施例中，导电堆叠层14可利用例如双镶嵌(dualdamascene)制作工艺等方式制作而成，而介电层16则优选由低介电常数材料(介电常数低于3.9)、超低介电常数材料(介电常数低于2.6)或通孔型超低介电常数材料所构成，例如本实施例的介电层16优选由氧化硅所构成，但不局限于此。另外导电堆叠层14的层数，包括金属层18与接触孔20的数量等均可视产品需求调整，并不局限于本实施例所公开的数量。由于形成导电堆叠层14与介电层16是本领域所熟知技术，在此不另加赘述。
如图2所示，接着依序形成一铝金属层26于介电层16上、一阻障层28于铝金属层26上以及一铂金属层30于阻障层28上。在本实施例中，阻障层28优选自由钛、氮化钛、钽及氮化钽所构成的群组，但不局限于此。其次，铝金属层26与相对于铂金属层30的厚度比优选大于30％，且铝金属层26的厚度优选介于300-1000埃，而铂金属层30的厚度优选约1000埃。另外需注意的是，本实施例虽于铝金属层26及铂金属层30之间设置一阻障层28，但阻障层28为选择性设置的材料层，即本发明又可依据制作工艺需求省略阻障层28的设置，而直接形成铂金属层30于铝金属层26表面，此实施例也属本发明所涵盖的范围。
随后如图3所示，进行一第一蚀刻制作工艺去除部分铂金属层30、部分阻障层28以及部分铝金属层26以形成一图案化的铂金属层30与一图案化的阻障层28。在本实施例中，第一蚀刻制作工艺优选先形成一图案化光致抗蚀剂(图未示)于铂金属层30上，然后以图案化光致抗蚀剂为蚀刻掩模去除部分铂金属层30与部分阻障层28。接着以铝金属层26为蚀刻停止层，使第一蚀刻制作工艺去除部分铂金属层30与部分阻障层28后停在铝金属层26中且不侵蚀底下的介电层16。另外，第一蚀刻制作工艺所使用的蚀刻气体优选选自由氯气(Cl2)及三氟甲烷(CHF3)所构成的群组，但不局限于此。
接着如图4所示，进行一第二蚀刻制作工艺，去除部分由图案化的铂金属层30所暴露出的铝金属层26及部分介电层16，以形成图案化的铝金属层26。在本实施例中，第二蚀刻制作工艺可再次利用先前第一蚀刻制作工艺所使用的图案化光致抗蚀剂为蚀刻掩模去除部分铝金属层26及部分介电层16，或可先去除该图案化光致抗蚀剂，直接以图案化的铂金属层30为蚀刻掩模来去除部分铝金属层26及介电层16，此实施例也属本发明所涵盖的范围。其次，经由上述蚀刻制作工艺后介电层16的耗损优选小于600埃。另外，第二蚀刻制作工艺所使用的蚀刻气体优选选自由氯气(Cl2)及三氯化硼(BCl3)所构成的群组，但不局限于此。至此即完成本发明优选实施例制作一半导体元件的方法。
请再参照图4，图4还公开一种半导体元件结构，其包含一基底12、一导电堆叠层14设于基底12上、一介电层16覆盖于导电堆叠层14上、一铝金属层26设于介电层16上一铂金属层30设于铝金属层26上以及一阻障层28设于铝金属层26与铂金属层30之间。在本实施例中，阻障层28虽设于铝金属层26与铂金属层30之间并直接接触铝金属层26与铂金属层30，但由于阻障层28为一选择性设置的结构，若依据制作工艺需求选择不设置任何阻障层28于铝金属层26与铂金属层30之间，则铂金属层30优选直接接触铝金属层26。其次需注意的是，由于铂金属层30、阻障层28及铝金属层26优选利用同一道图案化光致抗蚀剂经由图案转移制作工艺而完成图案化，因此这三者优选具有相同图案。另外本实施例的介电层16优选包含氧化硅而阻障层28优选自由钛、氮化钛、钽及氮化钽所构成的群组，但不局限于此。
综上所述，相较于现有图案化铂金属层时仅利用由例如氮化钛所构成的阻障层为蚀刻停止层，本发明主要在图案化铂金属层时利用一铝金属层作为蚀刻停止层，由此在图案化的过程中精准控制蚀刻的进度，如此不但可提升整个晶片中心区与周边区的均匀度(uniformity)，又可同时降低铝金属层底下介电层的耗损。依据本发明的优选实施例，经由此蚀刻方式所形成的图案化的铂金属层搭配图案化的铝金属层等图案可应用于诸多感测器相关的元件上，包括用于检测酒驾的侦测器以及DNA检测器等应用上。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (16)

1.一种制作半导体元件的方法，包含：
提供一基底，且该基底具有一介电层；
形成一铝金属层于该介电层上；
形成一铂金属层于该铝金属层上；
进行一第一蚀刻制作工艺，去除部分该铂金属层及部分该铝金属层以形成一图案化的铂金属层；以及
进行一第二蚀刻制作工艺，去除部分由该图案化的铂金属层所暴露出的铝金属层及部分该介电层。
2.如权利要求1所述的方法，还包含：
形成一阻障层于该铝金属层上；
形成该铂金属层于该阻障层上；
进行该第一蚀刻制作工艺去除部分该铂金属层、部分该阻障层及部分该铝金属层以形成该图案化的铂金属层与一图案化的阻障层；以及
进行该第二蚀刻制作工艺去除部分由该图案化的铂金属层所暴露出的铝金属层及部分该介电层。
3.如权利要求1所述的方法，其中该阻障层选自由钛、氮化钛、钽及氮化钽所构成的群组。
4.如权利要求1所述的方法，还包含利用一气体进行该第一蚀刻制作工艺，该气体选自由氯气(Cl2)及三氟甲烷(CHF3)所构成的群组。
5.如权利要求1所述的方法，还包含利用一气体进行该第二蚀刻制作工艺，该气体选自由氯气(Cl2)及三氯化硼(BCl3)所构成的群组。
6.如权利要求1所述的方法，其中该基底包含一导电堆叠层设于该介电层下方。
7.如权利要求1所述的方法，其中该介电层包含氧化硅。
8.一种半导体元件，包含：
基底，该基底具有一介电层；
铝金属层设于该介电层上；以及
铂金属层设于该铝金属层上。
9.如权利要求8所述的半导体元件，还包含一阻障层，于铝金属层及铂金属层之间。
10.如权利要求9所述的半导体元件，其中该阻障层选自由钛、氮化钛、钽及氮化钽所构成的群组。
11.如权利要求9所述的半导体元件，其中该铂金属层及该铝金属层直接接触该阻障层。
12.如权利要求8所述的半导体元件，还包含一导电堆叠层，设于该介电层下方。
13.如权利要求8所述的半导体元件，其中该介电层包含氧化硅。
14.如权利要求8所述的半导体元件，其中该铝金属层及该铂金属层包含相同图案。
15.如权利要求8所述的半导体元件，其中该铂金属层直接接触该铝金属层。
16.如权利要求8所述的半导体元件，其中该铝金属层相对于铂金属层的厚度比大于30％。
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