CN105493403B - 包括占空比校正的时钟倍频器 - Google Patents

包括占空比校正的时钟倍频器 Download PDF

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Publication number
CN105493403B
CN105493403B CN201480042441.6A CN201480042441A CN105493403B CN 105493403 B CN105493403 B CN 105493403B CN 201480042441 A CN201480042441 A CN 201480042441A CN 105493403 B CN105493403 B CN 105493403B
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CN
China
Prior art keywords
clock signal
charge pump
current
during
mismatch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201480042441.6A
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English (en)
Chinese (zh)
Other versions
CN105493403A (zh
Inventor
J·M·辛里奇斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
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Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105493403A publication Critical patent/CN105493403A/zh
Application granted granted Critical
Publication of CN105493403B publication Critical patent/CN105493403B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
CN201480042441.6A 2013-07-30 2014-07-24 包括占空比校正的时钟倍频器 Expired - Fee Related CN105493403B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/954,691 US9124250B2 (en) 2013-07-30 2013-07-30 Clock doubler including duty cycle correction
US13/954,691 2013-07-30
PCT/US2014/047959 WO2015017233A1 (en) 2013-07-30 2014-07-24 Clock doubler including duty cycle correction

Publications (2)

Publication Number Publication Date
CN105493403A CN105493403A (zh) 2016-04-13
CN105493403B true CN105493403B (zh) 2018-10-23

Family

ID=51398862

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480042441.6A Expired - Fee Related CN105493403B (zh) 2013-07-30 2014-07-24 包括占空比校正的时钟倍频器

Country Status (6)

Country Link
US (1) US9124250B2 (cg-RX-API-DMAC7.html)
EP (1) EP3028383B1 (cg-RX-API-DMAC7.html)
JP (1) JP2016533083A (cg-RX-API-DMAC7.html)
KR (1) KR20160039210A (cg-RX-API-DMAC7.html)
CN (1) CN105493403B (cg-RX-API-DMAC7.html)
WO (1) WO2015017233A1 (cg-RX-API-DMAC7.html)

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* Cited by examiner, † Cited by third party
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US9413339B2 (en) * 2013-10-03 2016-08-09 Samsung Display Co., Ltd. Apparatus and method for offset cancellation in duty cycle corrections
US10409464B2 (en) * 2015-03-18 2019-09-10 Microsoft Technology Licensing, Llc Providing a context related view with a wearable apparatus
US10324519B2 (en) * 2016-06-23 2019-06-18 Intel Corporation Controlling forced idle state operation in a processor
US10303482B2 (en) * 2017-03-07 2019-05-28 Red Hat, Inc. Dynamic processor frequency selection
JP6903977B2 (ja) * 2017-03-22 2021-07-14 日本電気株式会社 デジタル変調器、通信装置、デジタル変調器の制御方法及びプログラム
CN110324037B (zh) 2018-03-31 2021-08-20 华为技术有限公司 一种倍频器、数字锁相环电路以及倍频方法
CN111193499B (zh) * 2018-11-15 2024-12-06 长鑫存储技术有限公司 时钟占空比校准电路及校准方法
CN111192609B (zh) * 2018-11-15 2024-09-06 长鑫存储技术有限公司 时钟占空比校准电路及校准方法
EP3840223A1 (en) * 2019-12-16 2021-06-23 ams International AG Duty cycle correction circuit and applications thereof
TWI751878B (zh) * 2021-01-06 2022-01-01 瑞鼎科技股份有限公司 電荷泵電路
US11711087B2 (en) 2021-07-05 2023-07-25 Shaoxing Yuanfang Semiconductor Co., Ltd. Reducing noise contribution in compensating for unequal successive time periods of a reference clock in a fractional-N phase locked loop
US11533045B1 (en) * 2022-02-22 2022-12-20 Qualcomm Incorporated Dynamic aging monitor and correction for critical path duty cycle and delay degradation
KR20250018718A (ko) 2023-07-31 2025-02-07 에스케이하이닉스 주식회사 클럭 더블러 및 이를 이용하는 반도체 장치
US20250055446A1 (en) * 2023-08-09 2025-02-13 Nxp B.V. Quadrature phase shifted clock generation with duty cycle correction
US20250317055A1 (en) * 2024-04-04 2025-10-09 Qualcomm Incorporated Duty cycle corrector systematic offset reduction
CN119341529B (zh) * 2024-09-11 2025-08-15 西安芯存半导体有限公司 占空比调整电路、延迟锁相环电路及存储器
CN119727708B (zh) * 2024-12-16 2025-08-12 慷智集成电路(上海)有限公司 一种锁相环参考时钟占空比校准电路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2250538A1 (en) * 1998-10-30 2000-04-30 Mosaid Technologies Incorporated Duty cycle regulator
US20110291726A1 (en) * 2010-05-28 2011-12-01 Woo-Seok Kim Duty correcting circuit, delay-locked loop circuit including the circuit, and method of correcting duty

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566925B2 (en) 1995-10-25 2003-05-20 Mosaid Technologies Incorporated Duty-cycle regulator
KR100891300B1 (ko) * 2007-09-04 2009-04-06 주식회사 하이닉스반도체 반도체 장치 및 그 구동방법
US8049540B2 (en) 2008-09-19 2011-11-01 Analog Devices, Inc. Calibration system and method for phase-locked loops
US8406021B2 (en) * 2009-08-10 2013-03-26 Emerson Climate Technologies, Inc. System and method for reducing line current distortion
US8198927B2 (en) 2010-02-01 2012-06-12 Analog Devices, Inc. High speed charge pump
US8149031B1 (en) 2010-09-08 2012-04-03 Applied Micro Circuits Corporation Duty-cycle feedback charge pump
CN103348596B (zh) 2011-02-04 2016-08-10 马维尔国际贸易有限公司 用于分数-n锁相环(pll)的参考时钟补偿

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2250538A1 (en) * 1998-10-30 2000-04-30 Mosaid Technologies Incorporated Duty cycle regulator
US20110291726A1 (en) * 2010-05-28 2011-12-01 Woo-Seok Kim Duty correcting circuit, delay-locked loop circuit including the circuit, and method of correcting duty

Also Published As

Publication number Publication date
JP2016533083A (ja) 2016-10-20
WO2015017233A1 (en) 2015-02-05
US20150035570A1 (en) 2015-02-05
KR20160039210A (ko) 2016-04-08
EP3028383A1 (en) 2016-06-08
US9124250B2 (en) 2015-09-01
CN105493403A (zh) 2016-04-13
EP3028383B1 (en) 2022-04-13

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Granted publication date: 20181023

Termination date: 20210724