CN1054931C - 共用总线非顺序数据排序方法与装置 - Google Patents

共用总线非顺序数据排序方法与装置 Download PDF

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Publication number
CN1054931C
CN1054931C CN95102491A CN95102491A CN1054931C CN 1054931 C CN1054931 C CN 1054931C CN 95102491 A CN95102491 A CN 95102491A CN 95102491 A CN95102491 A CN 95102491A CN 1054931 C CN1054931 C CN 1054931C
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China
Prior art keywords
data
bus
value
chip
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN95102491A
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English (en)
Chinese (zh)
Other versions
CN1117617A (zh
Inventor
H·L·布拉克曼
R·A·德里梅尔
L·E·格罗斯巴哈
K·H·哈塞尔霍斯特
D·J·克罗拉克
J·A·马塞拉
P·J·保罗森
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International Business Machines Corp
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International Business Machines Corp
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Publication of CN1117617A publication Critical patent/CN1117617A/zh
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Publication of CN1054931C publication Critical patent/CN1054931C/zh
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Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Small-Scale Networks (AREA)
CN95102491A 1994-04-01 1995-03-16 共用总线非顺序数据排序方法与装置 Expired - Fee Related CN1054931C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US22214794A 1994-04-01 1994-04-01
US222147 1994-04-01
US222,147 1994-04-01

Publications (2)

Publication Number Publication Date
CN1117617A CN1117617A (zh) 1996-02-28
CN1054931C true CN1054931C (zh) 2000-07-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN95102491A Expired - Fee Related CN1054931C (zh) 1994-04-01 1995-03-16 共用总线非顺序数据排序方法与装置

Country Status (9)

Country Link
US (1) US5748919A (enExample)
EP (1) EP0676702B1 (enExample)
JP (1) JPH07281998A (enExample)
KR (1) KR0175980B1 (enExample)
CN (1) CN1054931C (enExample)
AT (1) ATE166733T1 (enExample)
CA (1) CA2142028A1 (enExample)
DE (1) DE69502656D1 (enExample)
TW (1) TW321744B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7765307B1 (en) * 2006-02-28 2010-07-27 Symantec Operating Corporation Bulk network transmissions using multiple connections primed to optimize transfer parameters

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280598A (en) * 1990-07-26 1994-01-18 Mitsubishi Denki Kabushiki Kaisha Cache memory and bus width control circuit for selectively coupling peripheral devices

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4056845A (en) * 1975-04-25 1977-11-01 Data General Corporation Memory access technique
US4514808A (en) * 1978-04-28 1985-04-30 Tokyo Shibaura Denki Kabushiki Kaisha Data transfer system for a data processing system provided with direct memory access units
US4490819A (en) * 1982-04-22 1984-12-25 International Telephone And Telegraph Corporation Rate converter
US4507731A (en) * 1982-11-01 1985-03-26 Raytheon Company Bidirectional data byte aligner
US4837785A (en) * 1983-06-14 1989-06-06 Aptec Computer Systems, Inc. Data transfer system and method of operation thereof
JPS61175845A (ja) * 1985-01-31 1986-08-07 Toshiba Corp マイクロプロセツサシステム
JPS6226561A (ja) * 1985-07-26 1987-02-04 Toshiba Corp パ−ソナルコンピユ−タ
US5243701A (en) * 1987-09-17 1993-09-07 Mitsubishi Denki Kabushiki Kaisha Method of and system for processing data having bit length variable with modes of operation
US4878166A (en) * 1987-12-15 1989-10-31 Advanced Micro Devices, Inc. Direct memory access apparatus and methods for transferring data between buses having different performance characteristics
US5237676A (en) * 1989-01-13 1993-08-17 International Business Machines Corp. High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device
JPH03186928A (ja) * 1989-12-16 1991-08-14 Mitsubishi Electric Corp データ処理装置
US5287470A (en) * 1989-12-28 1994-02-15 Texas Instruments Incorporated Apparatus and method for coupling a multi-lead output bus to interleaved memories, which are addressable in normal and block-write modes
JP2646854B2 (ja) * 1990-12-18 1997-08-27 三菱電機株式会社 マイクロプロセッサ
US5255374A (en) * 1992-01-02 1993-10-19 International Business Machines Corporation Bus interface logic for computer system having dual bus architecture
US5257391A (en) * 1991-08-16 1993-10-26 Ncr Corporation Disk controller having host interface and bus switches for selecting buffer and drive busses respectively based on configuration control signals
US5293381A (en) * 1992-03-27 1994-03-08 Advanced Micro Devices Byte tracking system and method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280598A (en) * 1990-07-26 1994-01-18 Mitsubishi Denki Kabushiki Kaisha Cache memory and bus width control circuit for selectively coupling peripheral devices

Also Published As

Publication number Publication date
TW321744B (enExample) 1997-12-01
KR0175980B1 (ko) 1999-05-15
DE69502656D1 (de) 1998-07-02
CN1117617A (zh) 1996-02-28
US5748919A (en) 1998-05-05
EP0676702B1 (en) 1998-05-27
EP0676702A1 (en) 1995-10-11
JPH07281998A (ja) 1995-10-27
CA2142028A1 (en) 1995-10-02
KR950029955A (ko) 1995-11-24
ATE166733T1 (de) 1998-06-15

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Granted publication date: 20000726