CN105470218A - 用于热管理的背侧散热器的集成 - Google Patents

用于热管理的背侧散热器的集成 Download PDF

Info

Publication number
CN105470218A
CN105470218A CN201510627492.1A CN201510627492A CN105470218A CN 105470218 A CN105470218 A CN 105470218A CN 201510627492 A CN201510627492 A CN 201510627492A CN 105470218 A CN105470218 A CN 105470218A
Authority
CN
China
Prior art keywords
layer
heat dissipation
substrate
microelectronic component
radiator material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510627492.1A
Other languages
English (en)
Other versions
CN105470218B (zh
Inventor
A·维诺戈帕
M·丹尼森
L·哥伦布
H·尼古耶
D·爱德华兹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN105470218A publication Critical patent/CN105470218A/zh
Application granted granted Critical
Publication of CN105470218B publication Critical patent/CN105470218B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0341—Manufacturing methods by blanket deposition of the material of the bonding area in liquid form
    • H01L2224/03416—Spin coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/05078—Plural internal layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05187—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05193—Material with a principal constituent of the material being a solid not provided for in groups H01L2224/051 - H01L2224/05191, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05578—Plural external layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05687—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05693—Material with a principal constituent of the material being a solid not provided for in groups H01L2224/056 - H01L2224/05691, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08153—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/08155—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. being an insulating substrate with or without metallisation
    • H01L2224/08165—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. being an insulating substrate with or without metallisation the bonding area connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/29191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Ceramic Engineering (AREA)

Abstract

本发明涉及用于热管理的背侧散热器的集成。一种微电子器件(100)包括半导体器件(102)，其中，在该半导体器件(102)的前表面(104)处具有组件(108)并且在该半导体器件(102)的后表面(106)上具有背侧散热器层(110)。该背侧散热器层(110)的厚度为100纳米至3微米，具有至少150瓦特/(米·开尔文)的层内导热系数、以及小于100微欧姆厘米的电阻率。

Description

用于热管理的背侧散热器的集成
技术领域
本发明涉及微电子器件的领域。更具体地，本发明涉及在微电子器件中的热管理结构。
背景技术
具有局部生热组件的半导体器件经历导致降低可靠性的热点。去除热量同时保持期望的成本和结构形式因素已经是个问题。
发明内容
下面呈现简单的概述以便提供对该发明的一个或更多方面的基本理解。此概述不是该发明的广泛综述，并且既不旨在标识该发明的关键或重要因素，也不旨在描绘其范围。而是，该概述的主要目的是以简化的形式呈现该发明的一些概念，作为之后呈现的更加详细的描述的前序。
一种微电子器件包括半导体器件，在该半导体器件的前表面处具有组件并且在该半导体器件的后表面上具有背侧散热器层。该背侧散热器层的厚度为100纳米至3微米，具有至少150瓦特/(米·开尔文)的层内导热系数(in-planethermalconductivity)、以及小于100微欧姆厘米的电阻率。
附图简要说明
图1是具有背侧散热器层的示例性微电子器件的截面。
图2是具有背侧散热器层的另一个示例性微电子器件的截面。
图3是具有背侧散热器层的另一个示例性微电子器件的截面。
图4是具有背侧散热器层的另一个示例性微电子器件的截面。
图5A至图5C描绘了形成具有背侧散热器层的微电子器件的示例性过程。
图6描绘了一种用于在微电子器件上形成背侧散热器层的示例性方法。
图7A和图7B描绘了用于在微电子器件上形成散热器层的另一个示例性方法。
具体实施方式
以下同时处于申请状态的专利申请(co-pendingpatentapplication)是相关的并且通过以下引用结合在此：美国专利申请12/xxx,xxx(德州仪器案卷号TI-73378与此申请同时提交)。
参照这些附图描述本发明。这些附图不是按比例绘制的并且提供它们仅为了说明该发明。以下参照用于说明的多个示例性应用描述了该发明的若干方面。应当理解的是，列出许多具体的细节、关系和方法以提供对该发明的理解。然而，相关领域的技术人员将容易地意识到，能够无需这些具体细节中的一个或更多细节或者使用其他方法来实践该发明。在其他实例中，没有详细地示出众所周知的结构或者操作以避免混淆该发明。本发明不受展示的行动或者事件的顺序所限制，因为某些行动可以以不同的顺序发生和/或与其他行动或者事件同时发生。此外，不要求所有展示的行动或者事件根据本发明实施方法。
为了本披露的目的，术语“微电子器件”可以指诸如集成电路或者离散半导体组件的半导体器件，可以指与其他半导体器件在一个薄片中的半导体器件，可以指安装在衬底上的半导体器件，可以指在封装中的半导体器件，以及可以指被密封在电绝缘材料中的半导体器件。
图1是具有背侧散热器层的示例性微电子器件的截面。微电子器件100包括具有前表面104和后表面106的半导体器件102。诸如晶体管、二极管或者电阻器的组件108在半导体器件102中在前表面104处形成。组件108可以深入延伸进入半导体器件中，有可能到达后表面106。背侧散热器层110在半导体器件102的后表面106处形成。背侧散热器层110包括散热器材料112，该散热器材料可以按照在图1中所描绘的被图案化或者可以是连续的。该散热器材料112的厚度为100纳米至3微米，具有至少150瓦特/(米·开尔文)的层内导热系数、以及小于100微欧姆厘米的电阻率。散热器材料112可以包括例如石墨、碳纳米管(CNT)、多层石墨烯、和/或氮化硼。背侧散热器层110可以可选地包括在散热器材料112和半导体器件102的后表面106之间的粘合层114。粘合层114可以包括例如通过溅射形成的钛或钛钨，并且可以减少散热器材料112的分层。诸如镍的其他金属可以被添加到粘合层114以改进随后形成散热器材料112。背侧散热器层110可以可选地包括在散热器材料112上与后表面106相反的盖层(caplayer)116。盖层116可以包括例如通过溅射形成的钛和氮化钛，并且可以减少散热器材料112的分层。
半导体器件102被安装在衬底118上，该衬底包括包含玻璃纤维加强塑料(FRP)的头部120、包含铜的顶部引线122、连接至顶部引线122的包含铜的通孔124、连接至通孔124的包含铜的底部引线126、以及连接至底部引线126的锡球128。半导体器件102被贴附到具有诸如环氧树脂的电绝缘固晶胶130的衬底118，该电绝缘固晶胶将背侧散热器层110贴附于顶部引线122。通过在前表面104处的接线键合(wirebond)132将在半导体器件102中的电路连接至顶部引线122。在微电子器件100的操作过程中，组件108可以生成非期望量的热量；背侧散热器层110可以传导热量使之远离组件108并且因此相比于相似的没有背侧散热器层的微电子器件，有利地减少了在组件108中的温度上升。
图2是具有背侧散热器层的另一个示例性微电子器件的截面。微电子器件200包括具有前表面204和后表面206的半导体器件202。组件208在半导体器件202中在前表面204处形成。组件208可以深入延伸进入半导体器件中，有可能到达后表面206。背侧散热器层210在半导体器件202的后表面206处形成。背侧散热器层210包括散热器材料212，该散热器材料可以如在图2中所描绘的是连续的或者可以被图案化。该散热器材料212的厚度为100纳米至3微米，具有至少150瓦特/(米·开尔文)的层内导热系数、以及小于100微欧姆厘米的电阻率。在当前示例中，散热器材料212是导电的并且可以包括例如石墨、CNT和/或多层石墨烯。如参照图1所描述的，背侧散热器层210可以可选地包括在散热器材料212和半导体器件202的后表面206之间的粘合层214。背侧散热器层210可以可选地包括在散热器材料212上与后表面206相反的盖层216。盖层216可以包括铜层和镍层。
半导体器件202被安装在双列直插式封装(DIP)218的接地板220上。半导体器件202被贴附到具有诸如焊料或者填充银的环氧树脂的电绝缘固晶材料(dieattachmaterial)230的接地板220，该电绝缘固晶材料将背侧散热器层210贴附于接地板220。该DIP218包括金属引线222。通过在前表面204处的接线键合232将在半导体器件202中的电路连接至引线222。该微电子器件包括封装半导体器件202和接地板220的塑料电绝缘材料234并且将引线222保持在适当位置中。如参照图1所描述的，微电子器件200可以从背侧散热器层210中产生相同益处。
图3是具有背侧散热器层的另一个示例性微电子器件的截面。微电子器件300包括具有前表面304和后表面306的半导体器件302。组件308在半导体器件302中在前表面304处形成。组件308可以深入延伸进入半导体器件中，有可能到达后表面306。
背侧散热器层310在半导体器件302的后表面306处形成。在当前示例中，背侧散热器层310包括如在图2中描绘的被图案化的第一散热器材料312。该第一散热器材料312的厚度为100纳米至3微米，具有至少150瓦特/(米·开尔文)的层内导热系数、以及小于100微欧姆厘米的电阻率。第一散热器材料312可以包括例如石墨、CNT、多层石墨烯、和/或氮化硼。如参照图1所描述的，背侧散热器层310可以可选地包括在第一散热器材料312和半导体器件302的后表面306之间的粘合层314。背侧散热器层310可以可选地包括在第一散热器材料312上与后表面306相反的第一盖层316。第一盖层316可以包括钛和氮化钛。在当前示例中，背侧散热器层310包括在该第一散热器材料312上的后表面306处的与第一盖层316(若存在)相接触的第二散热器材料336。该第二散热器材料336的厚度也为100纳米至3微米，具有至少150瓦特/(米·开尔文)的层内导热系数、以及小于100微欧姆厘米的电阻率。第二散热器材料336可以具有与第一散热器材料312的相同构成。第二散热器材料336填充了与第一散热器材料312之间的间隙，并且可以按照在图3中所描绘的被图案化或者可以是连续的。第一盖层316可以提供针对第二散热器材料336的粘合。背侧散热器层310可以可选地包括钛和氮化钛的第二盖层338。
在半导体器件302中的电路在前表面304处由焊料凸块(solderbump)332凸点键合(bumpbonded)至衬底318的顶部引线322。衬底318包括包含FRP的头部320、顶部引线322、连接至顶部引线322的底部引线326、以及连接至底部引线326的锡球328。可选的灌注胶334可以被施加到半导体器件302，覆盖背侧散热器层310并且向下延伸至衬底318。在微电子器件300的操作过程中，背侧散热器层310可以有利地传导热量使之远离组件308。形成背侧散热器层310，其中，第二散热器材料336穿过在第一散热器材料312中的间隙覆盖并且延伸，相比于分段的仅具有一层散热器材料的背侧散热器层，可以有利地减少在组件308中的温度上升。
图4是具有背侧散热器层的另一个示例性微电子器件的截面。微电子器件400包括具有前表面404和后表面406的半导体器件402。组件408在半导体器件402中在前表面404处形成。背侧散热器层410在半导体器件402的后表面406处形成。在当前示例中，背侧散热器层410包括连续的散热器材料412。该散热器材料412的厚度为100纳米至3微米，具有至少150瓦特/(米·开尔文)的层内导热系数、以及小于100微欧姆厘米的电阻率。散热器材料412可以包括例如石墨、CNT、多层石墨烯、和/或氮化硼。如参照图1所描述的，背侧散热器层410可以可选地包括在散热器材料412和半导体器件402的后表面406之间的粘合层414。背侧散热器层410可以可选地包括在散热器材料412上与后表面406相反的第一盖层416。第一盖层416可以包括钛和氮化钛。
在半导体器件402中的电路在前表面404处由焊料凸块432凸点键合至衬底418的顶部引线422。衬底418包括可能包含FRP的头部420、在头部420上的顶部引线422、连接至顶部引线422的底部引线426、以及连接至底部引线426的锡球428。可选的灌注胶434可以被施加到半导体器件402，提供对衬底418的机械粘合。
在当前示例中，如在图4中所描绘的，散热器盖440被放置在背侧散热器层410的上方，覆盖半导体器件402并且可能接触衬底418。散热器盖440可以是诸如不锈钢的金属。散热器盖440可以贴附到背侧散热器层410，该背侧散热器层具有诸如填充的环氧树脂或者基于硅树脂的散热器化合物的热传导材料442。
在微电子器件400的操作过程中，背侧散热器层410可以有利地传导热量使之远离组件408并且进入散热器盖440中，并且因此减少在组件408中的温度上升。相比于没有背侧散热器层的微电子器件，该背侧散热器层410可以有利地提高到散热器盖440的热量转移。
图5A至图5C描绘了形成具有背侧散热器层的微电子器件的示例性过程。参照图5A，从包括半导体材料诸如硅晶体544的器件衬底544开始形成多个微电子器件500。经过制造步骤处理半导体衬底544以在器件衬底544的前表面504处形成多个半导体器件502。每个微电子器件500包括半导体器件502，以及每个半导体器件502在前表面处包括组件508，该组件可能延伸进入器件衬底544，可能到达器件衬底544的后表面506。连续的背侧散热器层510在器件衬底544的后表面506处形成。背侧散热器层510包括散热器材料512。散热器材料512的厚度为100纳米至3微米，具有至少150瓦特/(米·开尔文)的层内导热系数、以及小于100微欧姆厘米的电阻率。散热器材料512可以包括例如石墨、CNT、多层石墨烯、和/或氮化硼。背侧散热器层510可以可选地包括在散热器材料512和器件衬底544的后表面506之间的粘合层514。穿过该多个半导体器件502的后表面506形成背侧散热器层510可以有利地减少微电子器件500的制造成本和复杂性。
参照图5B，背侧散热器层510例如由掩模和蚀刻过程而被图案化。被图案化的背侧散热器层510的立体构型可以不必与半导体器件502的立体构型重合或对准。在半导体器件502之间的划线546可以例如通过锯削或划片被标定用来随后使半导体器件502单一化。在当前示例的替代版本中，背侧散热器层510可以不被图案化，保持为连续的层直到后来的单一化。在使器件衬底544单一化之前将背侧散热器层510图案化可以有利地减少针对微电子器件500的制造成本和复杂性。
参照图5C，通过划线546使图5B中的器件衬底544单一化将这些微电子器件500隔离开。例如如参照图1至图4所描述的，可以进一步组装每个微电子器件500。
图6描绘了一种用于在微电子器件上形成背侧散热器层的示例性方法。在一个或更多器件衬底644上形成微电子器件600的多个半导体器件602。器件衬底644可以是例如半导体晶片。每个半导体器件602包括在相应的器件衬底644的前表面604处形成的组件。每个器件衬底644具有与前表面604相反的后表面606。器件衬底644被放置在如炉管的沉积室648中，从而使得每个器件衬底644的前表面604和后表面606暴露于沉积室648的环境中。反应物气体如甲烷、氢气和氩气被引入到沉积室648中并且器件衬底644被加热。可以有可能施加RF功率以在反应物气体中形成等离子体。反应物气体在每个器件衬底644的前表面604和后表面606上同时形成一层散热器材料612。随后从沉积室648中将器件衬底644移除。例如如参照图5A至图5C所描述的，可以在每个器件衬底644的后表面606上将该层散热器材料612图案化，以在微电子器件600上形成背侧散热器层。可以在每个半导体器件602的前表面604上将该层散热器材料612图案化以形成可以有利地减少组件的温度上升的散热器层，如同在共同受让的具有专利申请序列号xx/xxx,xxx(律师卷号为TI-73378)的与此申请同时提交的专利申请中所描述的，其通过引用结合在此。在前表面604和后表面606上同时形成该层散热器材料612可以有利地减少微电子器件600的制造成本和复杂性。
图7A和图7B描绘了用于在微电子器件上形成散热器层的另一个示例性方法。参照图7A，在其可以是例如半导体晶片的器件衬底744上形成微电子器件700的多个半导体器件702。每个半导体器件702包括在器件衬底744的前表面704处形成的组件708。每个器件衬底744具有与前表面704相反的后表面706。
器件衬底744被放置在旋涂装置750中。分配装置752提供CNT分散754于器件衬底744的后表面706上。CNT分散754包括分散在溶剂中的CNT。
参照图7B，器件衬底744被放置在烘焙室756中，该烘焙室例如使用辐射发热器758将器件衬底744加热到100℃至150℃，从而蒸发来自图7A的CNT分散754的溶剂760以提供背侧散热器层710。背侧散热器层710因此包括在连续的层中互相重叠的CNT，其有利地提供了较高的层内导热系数。使用图7A和图7B的旋涂工艺形成背侧散热器层710有利地减少了微电子器件700的热型面并且相比于真空沉积设备有利地利用了更低成本设备。
虽然以上已经描述了本发明的不同实施例，但应理解，这些实施例仅通过举例而不是限制性的方式来呈现。能够根据在此的披露，在不背离该发明的精神和范围的情况下针对披露后的实施例作出各种改变。因此，本发明的广度和范围应该不受任何一个以上描述的实施例的限制。而是，本发明的范围应当根据以下权利要求书及其等效物来限定。

Claims (20)

1.一种微电子器件，包括：
具有前表面和后表面的半导体器件；
在所述前表面处的组件；以及
在所述后表面处的背侧散热器层，所述背侧散热器层包括厚度为100纳米至3微米的散热器材料、具有至少150瓦特/米·开尔文的层内导热系数以及小于100微欧姆厘米的电阻率。
2.如权利要求1所述的微电子器件，其中，所述散热器材料包括石墨。
3.如权利要求1所述的微电子器件，其中，所述散热器材料包括碳纳米管即CNT。
4.如权利要求1所述的微电子器件，其中，所述散热器材料包括多层石墨烯。
5.如权利要求1所述的微电子器件，其中，所述散热器材料包括氮化硼。
6.如权利要求1所述的微电子器件，其中，所述背侧散热器层被图案化。
7.如权利要求1所述的微电子器件，其中，所述背侧散热器层包括在所述散热器材料与所述后表面之间的粘合层。
8.如权利要求1所述的微电子器件，其中，所述背侧散热器层包括在所述散热器材料上的与所述后表面相反的盖层。
9.如权利要求1所述的微电子器件，其中，所述微电子器件进一步包括衬底，其中，通过接触所述衬底和所述背侧散热器层的固晶材料将所述半导体器件贴附到所述衬底。
10.如权利要求1所述的微电子器件，其中，所述微电子器件进一步包括衬底，其中，通过在所述前表面处的凸点键合将所述半导体器件贴附到所述衬底，所述凸点键合接触所述衬底，并且所述背侧散热器层被贴附到散热件上。
11.一种形成微电子器件的方法，包括以下步骤：
为所述微电子器件的半导体器件提供器件衬底，所述器件衬底具有前表面和后表面；
在所述前表面处形成组件；以及
在所述后表面处形成散热器材料以形成背侧散热器层，所述散热器材料的厚度为100纳米至3微米、具有至少150瓦特/米·开尔文的层内导热系数以及小于100微欧姆厘米的电阻率。
12.如权利要求11所述的方法，其中，形成所述散热器材料包括使用甲烷和氢气以形成石墨层的等离子体增强式化学气相沉积即PECVD工艺。
13.如权利要求11所述的方法，其中，形成所述散热器材料包括在所述后表面上形成包括分散在溶剂中的CNT的CNT分散层，接着是加热所述器件衬底以移除所述溶剂的至少一部分以在连续层中形成互相重叠的CNT层。
14.如权利要求11所述的方法，其中，形成所述散热器材料包括氮化硼。
15.如权利要求11所述的方法，包括在形成所述散热器材料之前在所述后表面上形成粘合层，从而使得在所述粘合层上形成所述散热器材料。
16.如权利要求11所述的方法，包括将所述散热器材料图案化。
17.如权利要求11所述的方法，包括在所述散热器材料上形成盖层。
18.如权利要求11所述的方法，包括通过形成接触所述衬底和所述背侧散热器层的固晶材料层来将所述半导体器件贴附到衬底上，以及在所述半导体器件与所述衬底之间形成接线键合。
19.如权利要求19所述的方法，其中，所述固晶材料层是导电的。
20.如权利要求11所述的方法，包括通过在所述前表面处形成接触所述衬底的凸块键合来将所述半导体器件贴附到衬底上，以及将散热件贴附到所述背侧散热器层上。
CN201510627492.1A 2014-09-28 2015-09-28 用于热管理的背侧散热器的集成 Active CN105470218B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/499,222 US9496198B2 (en) 2014-09-28 2014-09-28 Integration of backside heat spreader for thermal management
US14/499,222 2014-09-28

Publications (2)

Publication Number Publication Date
CN105470218A true CN105470218A (zh) 2016-04-06
CN105470218B CN105470218B (zh) 2020-12-08

Family

ID=55585272

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510627492.1A Active CN105470218B (zh) 2014-09-28 2015-09-28 用于热管理的背侧散热器的集成

Country Status (2)

Country Link
US (2) US9496198B2 (zh)
CN (1) CN105470218B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107579050A (zh) * 2016-07-05 2018-01-12 慧隆科技股份有限公司 晶片封装体及其制造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9496198B2 (en) * 2014-09-28 2016-11-15 Texas Instruments Incorporated Integration of backside heat spreader for thermal management
CN108281404A (zh) * 2015-04-30 2018-07-13 华为技术有限公司 一种集成电路管芯及制造方法
US10607958B2 (en) * 2015-08-28 2020-03-31 Texas Instruments Incorporated Flip chip backside die grounding techniques
US10600753B2 (en) * 2015-08-28 2020-03-24 Texas Instruments Incorporated Flip chip backside mechanical die grounding techniques
US10854455B2 (en) * 2016-11-21 2020-12-01 Marvell Asia Pte, Ltd. Methods and apparatus for fabricating IC chips with tilted patterning
US11508674B2 (en) * 2016-12-06 2022-11-22 The Boeing Company High power thermally conductive radio frequency absorbers
US10002821B1 (en) 2017-09-29 2018-06-19 Infineon Technologies Ag Semiconductor chip package comprising semiconductor chip and leadframe disposed between two substrates
US10658263B2 (en) * 2018-05-31 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US11355414B2 (en) 2019-09-27 2022-06-07 Texas Instruments Incorporated Nanoparticle matrix for backside heat spreading
US11854933B2 (en) * 2020-12-30 2023-12-26 Texas Instruments Incorporated Thermally conductive wafer layer

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030209802A1 (en) * 2002-05-13 2003-11-13 Fujitsu Limited Semiconductor device and method for fabricating the same
CN101044809A (zh) * 2005-07-05 2007-09-26 财团法人首尔大学校产学协力财团 镀覆有碳纳米管的散热装置及其制造方法
US20090232991A1 (en) * 2008-03-17 2009-09-17 The Research Foundation Of State University Of New York Composite thermal interface material system and method using nano-scale components
CN102593081A (zh) * 2011-01-12 2012-07-18 英飞凌科技股份有限公司 包括散热器的半导体器件
CN202855803U (zh) * 2012-10-31 2013-04-03 深圳市志金电子有限公司 一种高导热led封装基板
CN203150536U (zh) * 2013-03-25 2013-08-21 深圳市跨越电子有限公司 高导热石墨膜
CN103545272A (zh) * 2012-07-12 2014-01-29 三星电子株式会社 包括热辐射部的半导体芯片及半导体芯片的制造方法
US8778784B2 (en) * 2010-09-21 2014-07-15 Ritedia Corporation Stress regulated semiconductor devices and associated methods
US20140284040A1 (en) * 2013-03-22 2014-09-25 International Business Machines Corporation Heat spreading layer with high thermal conductivity
CN104282640A (zh) * 2013-07-05 2015-01-14 爱思开海力士有限公司 半导体芯片与具有该半导体芯片的层叠型半导体封装

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006032410A (ja) * 2004-07-12 2006-02-02 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US8709538B1 (en) * 2009-09-29 2014-04-29 The Boeing Company Substantially aligned boron nitride nano-element arrays and methods for their use and preparation
JP6201322B2 (ja) * 2013-01-18 2017-09-27 富士通株式会社 電子デバイス及びその製造方法、並びに基板構造及びその製造方法
US9496198B2 (en) * 2014-09-28 2016-11-15 Texas Instruments Incorporated Integration of backside heat spreader for thermal management

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030209802A1 (en) * 2002-05-13 2003-11-13 Fujitsu Limited Semiconductor device and method for fabricating the same
CN101044809A (zh) * 2005-07-05 2007-09-26 财团法人首尔大学校产学协力财团 镀覆有碳纳米管的散热装置及其制造方法
US20090232991A1 (en) * 2008-03-17 2009-09-17 The Research Foundation Of State University Of New York Composite thermal interface material system and method using nano-scale components
US8778784B2 (en) * 2010-09-21 2014-07-15 Ritedia Corporation Stress regulated semiconductor devices and associated methods
CN102593081A (zh) * 2011-01-12 2012-07-18 英飞凌科技股份有限公司 包括散热器的半导体器件
CN103545272A (zh) * 2012-07-12 2014-01-29 三星电子株式会社 包括热辐射部的半导体芯片及半导体芯片的制造方法
CN202855803U (zh) * 2012-10-31 2013-04-03 深圳市志金电子有限公司 一种高导热led封装基板
US20140284040A1 (en) * 2013-03-22 2014-09-25 International Business Machines Corporation Heat spreading layer with high thermal conductivity
CN203150536U (zh) * 2013-03-25 2013-08-21 深圳市跨越电子有限公司 高导热石墨膜
CN104282640A (zh) * 2013-07-05 2015-01-14 爱思开海力士有限公司 半导体芯片与具有该半导体芯片的层叠型半导体封装

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
李勤涛: "低能甲烷和氢气混合离子束诱导产生石墨纳米晶包覆多壁碳纳米管的复合结构", 《新型碳材料》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107579050A (zh) * 2016-07-05 2018-01-12 慧隆科技股份有限公司 晶片封装体及其制造方法
CN107579050B (zh) * 2016-07-05 2019-11-15 慧隆科技股份有限公司 晶片封装体的制造方法

Also Published As

Publication number Publication date
US20160322277A1 (en) 2016-11-03
CN105470218B (zh) 2020-12-08
US9496198B2 (en) 2016-11-15
US9698075B2 (en) 2017-07-04
US20160093552A1 (en) 2016-03-31

Similar Documents

Publication Publication Date Title
CN105470218A (zh) 用于热管理的背侧散热器的集成
JP5239768B2 (ja) 放熱材料並びに電子機器及びその製造方法
CN104733329A (zh) 半导体封装结构和工艺
JP6127417B2 (ja) 放熱材料の製造方法
CN105470217A (zh) 用于beol热管理的散热器的集成
WO2013046291A1 (ja) 放熱材料及びその製造方法並びに電子機器及びその製造方法
JP5707810B2 (ja) 半導体モジュールの製造方法
JP5212253B2 (ja) シート状構造体の製造方法
US20210272804A1 (en) Semicondctor device package thermal conduit
CN103632985A (zh) 制造裸片的金属垫片结构的方法、裸片配置和芯片配置
WO2014204828A2 (en) Thermal interface nanocomposite
CN105101673A (zh) 金属基座基板、功率模块、以及金属基座基板的制造方法
JP5447117B2 (ja) 電子機器の製造方法
US8749075B2 (en) Integrated circuits and a method for manufacturing an integrated circuit
US9644128B2 (en) Carbon nanotube sheet, electronic device, method of manufacturing carbon nanotube sheet, and method of manufacturing electronic device
JP5343620B2 (ja) 放熱材料及びその製造方法並びに電子機器及びその製造方法
KR101111127B1 (ko) 시트 형상 구조체와 그 제조 방법 및 전자기기
TW200905821A (en) Semiconductor device and method for manufacturing the same
JP5875102B2 (ja) 半導体モジュールの製造方法
CN109348616A (zh) 一种具有热传导结构的线路板及其制作方法
CN103515354A (zh) 用于低接触电阻碳纳米管互连件的装置和方法
CN110931368A (zh) 一种半导体封装结构及其制备方法
US11355414B2 (en) Nanoparticle matrix for backside heat spreading
WO2015029111A1 (ja) 半導体装置及びその製造方法
JP2013153042A (ja) 放熱材料の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant