CN105448896A - Integrated package structure to reduce footprint of off-chip capacitor - Google Patents
Integrated package structure to reduce footprint of off-chip capacitor Download PDFInfo
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- CN105448896A CN105448896A CN201410438974.8A CN201410438974A CN105448896A CN 105448896 A CN105448896 A CN 105448896A CN 201410438974 A CN201410438974 A CN 201410438974A CN 105448896 A CN105448896 A CN 105448896A
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- encapsulation structure
- polar plate
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Abstract
The invention relates to the field of electronic technology, particularly to a package structure. An integrated package structure to reduce the footprint of an off-chip capacitor comprises a package for packaging a chip. Bonding pads for external connection are disposed on the package, capacitor units are connected onto the bonding pads at predetermined positions, and metal pad blocks are connected onto the bonding pads at other positions. According to the invention, the capacitor units are connected onto the bonding pads at the predetermined positions on the chip to replace capacitors in an external circuit, without an increase in the process complexity of the package structure, the peripheral circuit is simplified, convenience is brought to a customer in practical application and the requirements of low power consumption and high integration are met.
Description
Technical field
The present invention relates to electronic technology field, be specifically related to a kind of encapsulating structure.
Background technology
Integrated antenna package not only plays bonding point and the outside effect carrying out being electrically connected in integrated circuit (IC) chip; also for integrated circuit (IC) chip provides a reliable and stable operational environment; integrated circuit (IC) chip is played to the effect of machinery or environmental protection; thus the function that integrated circuit (IC) chip can be brought into normal play, and ensure that it has high stability and reliability.In chip application; electric capacity in peripheral circuit usually can take too much printed circuit board space; too increase the application cost of chip, and the electric capacity in peripheral circuit is arranged on chip and also can sacrifices too much chip area, also do not have a kind of desirable mode to carry out layout to electric capacity at present.
Summary of the invention
The object of the invention is to, provide a kind of off-chip capacitive that reduces to hold the integrated encapsulation structure taken up room, solve above technical problem.
Technical problem solved by the invention can realize by the following technical solutions:
Reduce off-chip capacitive and hold the integrated encapsulation structure taken up room, comprise packaging body, for chip package, described packaging body is provided with the pad for being connected with outside, wherein, the described pad of desired location arranges capacitor cell, connection metal cushion block on the described pad of all the other positions.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and described capacitor cell is identical with the height of described backing metal.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and described backing metal and described inductance unit are connected with described circuit board by soldered ball.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and described capacitor cell comprises the first metal polar plate, the second metal polar plate;
Described second metal substrate and described first metal polar plate are oppositely arranged, and described first metal polar plate connects described pad, and the lower surface of described second metal polar plate connects described soldered ball.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and fills capacitor dielectric between described first metal polar plate and described second metal polar plate.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and described chip comprises substrate, and described pad is the lower surface that array format is distributed in described substrate.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and described packaging body adopts ceramic material or plastics to make.
Beneficial effect: owing to adopting above technical scheme, the present invention connects capacitor cell on the pad of the desired location of chip, to replace the electric capacity in external circuit, when not increasing encapsulating structure process complexity, simplify periphery circuit design also for the practical application of client is provided convenience, meet the requirement of low-power consumption high integration.
Accompanying drawing explanation
Fig. 1 is integrated encapsulation structure front view of the present invention;
Fig. 2 is that the A-A of Fig. 1 is to cutaway view;
Fig. 3 is the enlarged drawing that pad place of the present invention arranges capacitor cell.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite of not making creative work, all belongs to the scope of protection of the invention.
It should be noted that, when not conflicting, the embodiment in the present invention and the feature in embodiment can combine mutually.
Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as limiting to the invention.
With reference to Fig. 1, Fig. 2, Fig. 3, reduce off-chip capacitive and hold the integrated encapsulation structure taken up room, comprise packaging body 1, for chip package, packaging body 1 is provided with the pad for being connected with outside, wherein, the pad of desired location is arranged capacitor cell 3, connection metal cushion block 2 on the pad of all the other positions.
The present invention connects capacitor cell on the pad of the desired location of chip, to replace the electric capacity in external circuit, when not increasing encapsulating structure process complexity, simplifying periphery circuit design also for the practical application of client is provided convenience, meeting the requirement of low-power consumption high integration.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and capacitor cell 3 is identical with the height of backing metal 2.To ensure evenness when chip 1 is connected with circuit board, and reliability, reduce rosin joint etc. and connect insecure defect.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and backing metal 2 and capacitor cell 3 are connected with circuit board by soldered ball 4.When soldered ball 4 makes chip 1 be connected with circuit board, pin can be very short, shortens the transmission path of signal, reduces lead-in inductance, resistance, thus can improve the performance of circuit.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and capacitor cell 3 comprises the first metal polar plate 31, second metal polar plate 32;
Second metal substrate 32 and the first metal polar plate 31 are oppositely arranged, and the first metal polar plate 31 connects pad, and the lower surface of the second metal polar plate 32 connects soldered ball 4.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and the second metal substrate 32 and the first metal polar plate 31 are oppositely arranged afterwards and chip be arranged in parallel.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and fills capacitor dielectric between the first metal polar plate 31 and the second metal polar plate 32.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, and chip comprises substrate 5, and pad is the lower surface that array format is distributed in substrate 5.
Reduction off-chip capacitive of the present invention holds the integrated encapsulation structure taken up room, the packaging body 1 that packaging body 1 can adopt ceramic material to make.The packaging body 1 that ceramic material is made has greater flexibility in external form and function aspects, has better heat dispersion simultaneously.
The foregoing is only preferred embodiment of the present invention; not thereby embodiments of the present invention and protection range is limited; to those skilled in the art; should recognize and all should be included in the scheme that equivalent replacement done by all utilizations specification of the present invention and diagramatic content and apparent change obtain in protection scope of the present invention.
Claims (7)
1. reduce off-chip capacitive and hold the integrated encapsulation structure taken up room, comprise packaging body, for chip package, described packaging body is provided with the pad for being connected with outside, it is characterized in that, the described pad of desired location arranges capacitor cell, connection metal cushion block on the described pad of all the other positions.
2. reduction off-chip capacitive according to claim 1 holds the integrated encapsulation structure taken up room, and it is characterized in that, described capacitor cell is identical with the height of described backing metal.
3. reduction off-chip capacitive according to claim 1 holds the integrated encapsulation structure taken up room, and it is characterized in that, described backing metal and described capacity cell are connected with described circuit board by soldered ball.
4. reduction off-chip capacitive according to claim 3 holds the integrated encapsulation structure taken up room, and it is characterized in that, described capacitor cell comprises the first metal polar plate, the second metal polar plate;
Described second metal substrate and described first metal polar plate are oppositely arranged, and described first metal polar plate connects described pad, and the lower surface of described second metal polar plate connects described soldered ball.
5. reduction off-chip capacitive according to claim 4 holds the integrated encapsulation structure taken up room, and it is characterized in that, fills capacitor dielectric between described first metal polar plate and described second metal polar plate.
6. reduction off-chip capacitive according to claim 1 holds the integrated encapsulation structure taken up room, and it is characterized in that, described chip comprises substrate, and described pad is the lower surface that array format is distributed in described substrate.
7. reduction off-chip capacitive according to claim 1 holds the integrated encapsulation structure taken up room, and it is characterized in that, described packaging body adopts ceramic material or plastics to make.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410438974.8A CN105448896B (en) | 2014-08-29 | 2014-08-29 | Reduce the integrated encapsulation structure that off-chip capacitive holds occupied space |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410438974.8A CN105448896B (en) | 2014-08-29 | 2014-08-29 | Reduce the integrated encapsulation structure that off-chip capacitive holds occupied space |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105448896A true CN105448896A (en) | 2016-03-30 |
| CN105448896B CN105448896B (en) | 2018-12-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410438974.8A Active CN105448896B (en) | 2014-08-29 | 2014-08-29 | Reduce the integrated encapsulation structure that off-chip capacitive holds occupied space |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369913A (en) * | 2001-02-15 | 2002-09-18 | 矽统科技股份有限公司 | Ball arra ypackage for redcing electric stray signals |
| CN1732570A (en) * | 2002-12-31 | 2006-02-08 | 英特尔公司 | Multilayer capacitor with multiple plates per layer |
| US20070216027A1 (en) * | 2006-03-15 | 2007-09-20 | Nec Electronics Corporation | Semiconductor device |
| CN101271874A (en) * | 2008-05-12 | 2008-09-24 | 日月光半导体制造股份有限公司 | Semiconductor element with noise suppressing function and its manufacturing method |
-
2014
- 2014-08-29 CN CN201410438974.8A patent/CN105448896B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369913A (en) * | 2001-02-15 | 2002-09-18 | 矽统科技股份有限公司 | Ball arra ypackage for redcing electric stray signals |
| CN1732570A (en) * | 2002-12-31 | 2006-02-08 | 英特尔公司 | Multilayer capacitor with multiple plates per layer |
| US20070216027A1 (en) * | 2006-03-15 | 2007-09-20 | Nec Electronics Corporation | Semiconductor device |
| CN101271874A (en) * | 2008-05-12 | 2008-09-24 | 日月光半导体制造股份有限公司 | Semiconductor element with noise suppressing function and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105448896B (en) | 2018-12-21 |
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