CN105448894B - Electrostatic discharge protective circuit in advanced technologies - Google Patents
Electrostatic discharge protective circuit in advanced technologies Download PDFInfo
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- CN105448894B CN105448894B CN201510897149.9A CN201510897149A CN105448894B CN 105448894 B CN105448894 B CN 105448894B CN 201510897149 A CN201510897149 A CN 201510897149A CN 105448894 B CN105448894 B CN 105448894B
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Abstract
The present invention discloses a kind of electrostatic discharge protective circuit, it includes：The well region being formed in substrate；Substrate contact region, the first active area and the second active area extended downwardly from the upper surface of substrate, a part for second active area are located in well region, and another part is located in substrate；The grid oxic horizon that is formed on the upper surface of substrate and with the polysilicon gate on grid oxic horizon；3rd active area and trap contact zone being extended downwardly from the upper surface of substrate and in well region；It is formed at the first metal silicide region of substrate contact region and the first active region；The second metal silicide region being formed above polysilicon gate；The 3rd metal silicide region being formed above the 3rd active area and trap contact zone；Wherein the first metal silicide region and the second metal silicide region are connected with the first connecting pin, and the 3rd metal silicide region is connected with second connection end.This improves the performance of the electrostatic discharge protective circuit with metal silicide technology.
Description
【Technical field】
The present invention relates to a kind of circuit design field, more particularly to the electrostatic discharge protective circuit in advanced technologies.
【Background technology】
The minimum feature of integrated circuit technology is smaller, and technique is more advanced.Advanced technologies are since size is smaller, with its manufacture
Chip area is smaller, and chip cost is relatively low.The speed of advanced technologies device faster, is conducive to manufacture high performance chips at the same time.By
Constantly reduce in technique minimum feature, one of difficulty is that connection resistances are too big, the impedance of the contact hole of one side small size
Larger, on the other hand the resistance of relatively narrow polysilicon cabling is larger, these can reduce circuit connectivity energy.As technology develops,
Metal silicide technology is proposed, i.e., metal silicide is grown in silicon face by increase, the electricity of polysilicon line can be lowered
Resistance, while the resistance of contact hole can be reduced.But the performance of electrostatic discharge protective circuit can be reduced by increasing this technique.
It is necessary to propose a kind of new scheme to improve the electrostatic discharge protective circuit with metal silicide technology, it is anti-quiet improves it
Electric energy power.
【The content of the invention】
It is an object of the present invention to providing the electrostatic discharge protective circuit in a kind of advanced technologies, it has in advanced technologies
There is preferable antistatic effect.
To achieve the above object, according to an aspect of the present invention, it provides a kind of electrostatic discharge protective circuit, it includes：
Substrate；The well region being formed in the substrate；The substrate contact region extended downwardly from the upper surface of substrate；From the upper of substrate
The first active area that surface extends downwardly, wherein the first active area and substrate contact region are spaced, and the substrate
Contact zone is farther apart from the well region compared with the first active area；The second active area extended downwardly from the upper surface of substrate, should
A part for second active area is located in the well region, and another part is located in the substrate；It is formed at the upper table of the substrate
Grid oxic horizon on face, wherein the grid oxic horizon has between the first active area and the second active area and with first
Source region and the second active area are adjacent；Polysilicon gate on the grid oxic horizon；Prolong downwards from the upper table of substrate
3rd active area stretching and in the well region, wherein the 3rd active area are adjacent with second active area；From
Trap contact zone that the upper surface of substrate extends downwardly and in the well region, wherein the trap contact zone and the described 3rd
Active area is adjacent；It is formed at the first metal silicide region of the substrate contact region and the first active region；It is formed at described
The second metal silicide region above polysilicon gate；The 3rd metal silication being formed above the 3rd active area and trap contact zone
Thing area；Wherein the first metal silicide region and the second metal silicide region lead to be connected with the first connecting pin, the 3rd metal silicide
Area is connected with second connection end.
Further, the first metal silicide region, the second metal silicide region and the 3rd metal silicide region are same
Formed in metal silicide layer formation process.
Further, the first connecting pin is ground terminal, and second connection end is the pin by the chip of electrostatic protection.
Further, trap contact zone all by the 3rd metal silicide region cover, the 3rd active area with trap contact zone
Adjacent part is covered by the 3rd metal silicide region, and the subregion adjacent with the second active area of the 3rd active area be not by
Three metal silicide regions cover, and the second active region does not have metal silicide region covering.
Further, substrate, substrate contact region, the 3rd active area adulterate for p-type, the first active area, the second active area, trap
Contact zone is n-type doping.
Compared with prior art, the electrostatic discharge protective circuit in the present invention, by the portion of the second active area, the 3rd active area
Metal silicide is not covered on subregion, so as to improve the performance of the electrostatic discharge protective circuit with metal silicide technology.
【Brief description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, it can also be obtained according to these attached drawings other
Attached drawing.Wherein：
Fig. 1 is the structure diagram of electrostatic discharge protective circuit in one embodiment in the present invention.
【Embodiment】
The detailed description of the present invention is mainly by program, step, logical block, process or other symbolistic descriptions come directly
Or the running of simulation technical solution of the present invention indirectly.For the thorough explanation present invention, set forth very in following description
More specific details.And in these specific details, it is of the invention then can still may realize.Technical staff in fields makes
With these descriptions herein and state that the others skilled in the art into fields effectively introduce their work essence.Change sentence
Talk about, for the purpose of the present invention of avoiding confusion, since well known methods and procedures has been readily appreciated that they are not detailed
Thin description.
" one embodiment " or " embodiment " referred to herein refers to may be included at least one implementation of the present invention
A particular feature, structure, or characteristic." in one embodiment " that different places occur in the present specification not refers both to same
A embodiment, nor the single or selective embodiment mutually exclusive with other embodiment.
Fig. 1 is the structure diagram of electrostatic discharge protective circuit 100 in one embodiment in the present invention.As described in Figure 1,
The electrostatic discharge protective circuit 100 includes：
Substrate 110；
The well region 120 being formed in the substrate 110；
The substrate contact region 130 extended downwardly from the upper surface of substrate 110；
The first active area 140 extended downwardly from the upper surface of substrate 110, wherein the first active area 140 and substrate
Contact zone 130 is spaced, and the substrate contact region 130 is farther apart from the well region 120 compared with the first active area 140；
The second active area 150 extended downwardly from the upper surface of substrate 120, a part for second active area 150
In the well region 120, another part is located in the substrate 110；
The grid oxic horizon 160 being formed on the upper surface of the substrate 110, wherein the grid oxic horizon 160
It is between the first active area 140 and the second active area 150 and adjacent with the first active area 140 and the second active area 150；
Polysilicon gate 170 on the grid oxic horizon 160；
3rd active area 180 being extended downwardly from the upper surface of substrate 110 and in the well region 120, its
In the 3rd active area 180 it is adjacent with second active area 150；
Trap contact zone 190 being extended downwardly from the upper surface of substrate 110 and in the well region 120, wherein
The trap contact zone 190 is adjacent with the 3rd active area 180；
It is formed at the first metal silicide region 210 of the top of 130 and first active area of substrate contact region 140；
It is formed at the second metal silicide region 220 of the top of polysilicon gate 170；
It is formed at the 3rd metal silicide region 230 of the 3rd active area 180 and the top of trap contact zone 190；
Wherein the first metal silicide region 210 and the second metal silicide region 220 pass through contact hole and metal and ground terminal
VSS is connected, and the 3rd metal silicide region 230 is connected by contact hole and metal and chip by the pin PAD of electrostatic protection.
In one embodiment, substrate 110, substrate contact region 130, the 3rd active area 180 adulterate for p-type, and first is active
Area 140, the second active area 150, trap contact zone 190 are n-type doping.Specifically, substrate 110 is identified as P-sub, substrate contact
130 and the 3rd active area of area is marked as P+, and the first active area 140, the second active area 150 and trap contact zone 190 are marked as N
+, well region 120 is marked as Nwell.N+ regions are expressed as N-type heavily doped region, and P+ regions are expressed as p-type heavily doped region.
One of the features of the present invention, advantage are：130 and first active area 140 of substrate contact region be separately, rather than
Adjacent, this contributes to the dead resistance for increasing substrate contact, can help to be triggered during 100 static electricity discharge of electrostatic discharge protective circuit
More thoroughly, its electrostatic leakage ability is stronger.
The features of the present invention, the two of advantage are：The part of second active area 150 is located in well region 120, partly beyond institute
Well region 120 is stated in substrate 110, so contributes to trigger voltage during reduction static discharge.
In one embodiment, trap contact zone 190 is all covered by the 3rd metal silicide region 230, the 3rd active area
180 part adjacent with trap contact zone 190 is covered by the 3rd metal silicide region 230, and the 3rd active area 180 has with second
The adjacent subregion of source region 150 is not covered by the 3rd metal silicide region.Preferably, the 3rd active area 180 not by the 3rd
The width D 2 for the subregion that metal silicide region 230 covers is 0.15 micron to 0.5 micron, such as 0.3 micron.
In one embodiment, the top of the second active area 150 is not covered by metal silicide region, it is in suspension
State, i.e., connect any node with contact hole not over metal, and it does not have metal silicide region above.Preferably, second has
The peak width D1 of source region 150 is 1.5 microns to 5 microns, is 3 microns than such width.This region helps to improve electrostatic guarantor
Uniformity of the protection circuit in static electricity discharge.Concretely, when locally take the lead in triggering electrostatic leakage when, series connection resistance (i.e. by
The resistance that second active area 150 is formed), local current limliting will be formed, causes to wait other regions progressively all to trigger electrostatic leakage.
In one embodiment, the first metal silicide region 210, the second metal silicide region 220 and the 3rd metal silication
Thing area 230 is formed in same metal silicide layer formation process.In actual layout design, generally by drawing gold
Belong to silicide barrier layer to design, it is necessary to realizing the region of metal silicide does not have blocking layer of metal silicide, not necessarily forming
The region of blocking layer of metal silicide draws blocking layer of metal silicide, i.e., the width regions of D1 and D2 draw metal silication in figure
Thing barrier layer.
The operation principle of the electrostatic discharge protective circuit in Fig. 1 is described in detail below.
When positive electrostatic impact occurs, i.e., when the voltage of pin PAD is higher than the voltage of ground terminal VSS, first passing through the 3rd has
The parasitic diode of source region P+180 to Nwell 120, by the second active area N+150, then the second active area of reverse breakdown
150 to substrate P-sub110 parasitic diode produces reverse breakdown current, and a part of reverse breakdown current is by substrate P-
Substrate contact region P+130 on Sub110 is collected, and when this accumulation of electrical current is to certain value, by triggering parasitic NPN electric discharge, this is parasitic
The base stage of NPN is the substrate contact region P+130 on substrate P-sub, the transmitting of this parasitic NPN extremely on substrate P-Sub first
Active area N+140, the current collection extremely Nwell120 and trap contact zone N+190 of this parasitic NPN.As discharge current increases, can also
The further parasitic PNP pipe of triggering, the base stage of parasitic PNP pipe are to connect the trap contact zone N+190 of PAD, the emitter of parasitic PNP pipe
For the 3rd active area P+150 in NWell120, the current collection extremely substrate P-Sub110 of parasitic PNP pipe.The NPN's and PNP of parasitism
Collective effect will cause electrostatic leakage ability to strengthen.Second active area N+150 helps prevent local current to converge, so as to prevent office
The situation of portion's damage so that electrostatic leakage electric current is more uniform in regional.
When negative sense electrostatic impact occurs, i.e., when the voltage of ground terminal VSS is higher than the voltage of pin PAD, leakage current from
The substrate contact region P+130 at VSS ends, by substrate P-Sub110, then by between substrate P-Sub110 and well region Nwell120
Positive parasitic diode, eventually flow to trap contact zone N+190 to pin PAD.
The word that the expressions such as " connection ", " connected " or " connecting " in the present invention are electrically connected all represent it is electrical indirect or
It is directly connected to.Described above has fully disclosed the embodiment of the present invention.It is pointed out that it is familiar with the field
Scope of the technical staff to any change that the embodiment of the present invention is done all without departing from claims of the present invention.
Correspondingly, the scope of claim of the invention is also not limited only to previous embodiment.
Claims (7)
1. a kind of electrostatic discharge protective circuit, it is characterised in that it includes：
Substrate；
The well region being formed in the substrate；
The substrate contact region extended downwardly from the upper surface of substrate；
The first active area extended downwardly from the upper surface of substrate, wherein the first active area and substrate contact region are mutual
Every, and the substrate contact region is farther apart from the well region compared with the first active area；
The second active area extended downwardly from the upper surface of substrate, a part for second active area are located at the well region
In, another part is located in the substrate；
The grid oxic horizon being formed on the upper surface of the substrate, wherein the grid oxic horizon be located at the first active area and
It is between second active area and adjacent with the first active area and the second active area；
Polysilicon gate on the grid oxic horizon；
3rd active area being extended downwardly from the upper surface of substrate and in the well region, wherein the 3rd active area
It is adjacent with second active area；
Trap contact zone being extended downwardly from the upper surface of substrate and in the well region, wherein the trap contact zone and institute
It is adjacent to state the 3rd active area；
It is formed at the first metal silicide region of the substrate contact region and the first active region；
The second metal silicide region being formed above the polysilicon gate；
The 3rd metal silicide region being formed above the 3rd active area and trap contact zone；
Wherein the first metal silicide region and the second metal silicide region are connected with the first connecting pin, the 3rd metal silicide region with
Second connection end is connected,
Trap contact zone is all covered by the 3rd metal silicide region,
The part adjacent with trap contact zone of 3rd active area is covered by the 3rd metal silicide region, the 3rd active area with second
The adjacent subregion of active area is not covered by the 3rd metal silicide region,
Second active region does not have metal silicide region covering.
2. electrostatic discharge protective circuit according to claim 1, it is characterised in that：First metal silicide region, the second metallic silicon
Compound area and the 3rd metal silicide region are formed in same metal silicide layer formation process.
3. electrostatic discharge protective circuit according to claim 1, it is characterised in that：First connecting pin is ground terminal, and second connects
Hold as by the pin of the chip of electrostatic protection.
4. electrostatic discharge protective circuit according to claim 1, it is characterised in that：Second active area is in suspended state.
5. electrostatic discharge protective circuit according to claim 1, it is characterised in that：The width of second active area is 1.5 microns~5
Micron.
6. electrostatic discharge protective circuit according to claim 1, it is characterised in that：3rd active area not by the 3rd metal silication
The width of the subregion of thing area covering is 0.15 micron to 0.5 micron.
7. according to any electrostatic discharge protective circuits of claim 1-6, it is characterised in that：
Substrate, substrate contact region, the 3rd active area adulterate for p-type,
First active area, the second active area, trap contact zone are n-type doping.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510897149.9A CN105448894B (en) | 2015-12-08 | 2015-12-08 | Electrostatic discharge protective circuit in advanced technologies |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510897149.9A CN105448894B (en) | 2015-12-08 | 2015-12-08 | Electrostatic discharge protective circuit in advanced technologies |
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| Publication Number | Publication Date |
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| CN105448894A CN105448894A (en) | 2016-03-30 |
| CN105448894B true CN105448894B (en) | 2018-05-01 |
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| CN201510897149.9A Active CN105448894B (en) | 2015-12-08 | 2015-12-08 | Electrostatic discharge protective circuit in advanced technologies |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101136400A (en) * | 2006-08-29 | 2008-03-05 | 上海华虹Nec电子有限公司 | Electrostatic prevention protection structure of grids coupling used for high voltage drain spreading NMOS |
| CN202172069U (en) * | 2011-08-25 | 2012-03-21 | 上海华虹Nec电子有限公司 | Device possessing static protection function |
| CN103579333A (en) * | 2012-07-20 | 2014-02-12 | 上海华虹Nec电子有限公司 | MOS electrostatic protection device |
| CN104716132A (en) * | 2013-12-17 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Silicon control rectifier for low trigger voltage and high maintaining voltage and circuit of silicon control rectifier |
| CN205231051U (en) * | 2015-12-08 | 2016-05-11 | 无锡中感微电子股份有限公司 | Electrostatic protection circuit in advanced technology |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100976410B1 (en) * | 2008-05-28 | 2010-08-17 | 주식회사 하이닉스반도체 | Electrostatic Discharge Device |
-
2015
- 2015-12-08 CN CN201510897149.9A patent/CN105448894B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101136400A (en) * | 2006-08-29 | 2008-03-05 | 上海华虹Nec电子有限公司 | Electrostatic prevention protection structure of grids coupling used for high voltage drain spreading NMOS |
| CN202172069U (en) * | 2011-08-25 | 2012-03-21 | 上海华虹Nec电子有限公司 | Device possessing static protection function |
| CN103579333A (en) * | 2012-07-20 | 2014-02-12 | 上海华虹Nec电子有限公司 | MOS electrostatic protection device |
| CN104716132A (en) * | 2013-12-17 | 2015-06-17 | 中芯国际集成电路制造(上海)有限公司 | Silicon control rectifier for low trigger voltage and high maintaining voltage and circuit of silicon control rectifier |
| CN205231051U (en) * | 2015-12-08 | 2016-05-11 | 无锡中感微电子股份有限公司 | Electrostatic protection circuit in advanced technology |
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| Publication number | Publication date |
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| CN105448894A (en) | 2016-03-30 |
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