CN105374816B - A kind of bidirectional ESD protective device based on Ge-Si heterojunction technique - Google Patents
A kind of bidirectional ESD protective device based on Ge-Si heterojunction technique Download PDFInfo
- Publication number
- CN105374816B CN105374816B CN201510976592.5A CN201510976592A CN105374816B CN 105374816 B CN105374816 B CN 105374816B CN 201510976592 A CN201510976592 A CN 201510976592A CN 105374816 B CN105374816 B CN 105374816B
- Authority
- CN
- China
- Prior art keywords
- conduction type
- layer
- sige
- sige layer
- esd protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001681 protective effect Effects 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 17
- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 61
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 230000003071 parasitic effect Effects 0.000 description 11
- 102000004207 Neuropilin-1 Human genes 0.000 description 9
- 108090000772 Neuropilin-1 Proteins 0.000 description 9
- 102000004213 Neuropilin-2 Human genes 0.000 description 9
- 108090000770 Neuropilin-2 Proteins 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000007667 floating Methods 0.000 description 5
- 230000024241 parasitism Effects 0.000 description 4
- 230000010485 coping Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 244000045947 parasite Species 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
Abstract
The invention belongs to integrated circuit electrostatic discharges to protect field, specially a kind of bidirectional ESD protective device based on Ge-Si heterojunction technique, for overcoming the problems, such as that existing SiGe Heterojunction Bipolar Transistors HBT device can not achieve identical bi-directional ESD protective capability.The structure includes: the first conduction type silicon substrate, second of conduction type buried layer, second of conduction type well region are sequentially formed on substrate, two of symmetrical distribution the first conduction type SiGe layers are formed on the well region, N number of second of conductivity type polysilicon layer is respectively formed in each SiGe layer, wherein, the polysilicon layer jointed anode formed in the SiGe layer of left side, the polysilicon layer connection cathode formed in the SiGe layer of right side.The present invention is based on the basic structures of SiGe heterojunction bipolar transistor HBT, constitute two-way full symmetric SCR structure；When the minus earth of the SCR device structure, which has two-way identical ESD protective capability.
Description
Technical field
The invention belongs to integrated circuit electrostatic discharge (Electrostatic Discharge, ESD) to protect field, specifically
It is related to a kind of novel bidirectional ESD protective device for being based on germanium silicon (SiGe) Heterojunction.
Background technique
Static discharge phenomenon is widely present in nature, it be cause IC products fail major reason it
One.IC products are highly susceptible to the influence of static discharge in its manufacturing and assembling process, cause product
Reliability reduces, or even damage.Therefore, high reliablity and the strong electrostatic discharge protection component and protection of electrostatic protection performance are studied
Circuit has considerable effect to the yield rate and reliability that improve integrated circuit.
When static discharge phenomenon occurs for integrated circuit, a large amount of charge moments flow into the pin of chip, these circuits generate
Electric current usually up to several amperes, the voltage generated at the pin is up to tens volts of even several hectovolts.Biggish electric current and
Higher voltage will cause the damage of chip internal circuits and the breakdown of device, so as to cause the failure of circuit function.Therefore, it is
Prevent damage of the chip by ESD, it is necessary to which effective ESD protection is carried out to each pin of chip.
SiGe technique can improve the performance of Si by energy band engineering and strain engineering in Si on piece, while can use again
Mature and cheap Si technology is processed.Under the overall situation that mobile terminal in recent years is popularized, high frequency, high speed, low-power consumption are adapted to
SiGe technique just slowly replace Si technique status.So it is advantageous to explore ESD protection new construction of the design based on SiGe technique
In the reliability for improving the integrated circuit based on SiGe technique.
Under SiGe technique, SiGe Heterojunction Bipolar Transistors HBT device architecture is generallyd use to carry out ESD protection.
Basic HBT device architecture is as shown in Figure 1, comprising:
P-type silicon substrate 110；
N-shaped buried layer 120 is formed on the substrate 110；
N-shaped well region 130 is formed on the N-shaped buried layer 120；
The two sides of N-shaped well region 130 on the N-shaped buried layer 120 are respectively equipped with N-shaped heavily doped region 141 and 142, the region
141 and region 142 be connected with collector；
A p-type SiGe layer 150 is formed above the N-shaped well region 130, which is connected with base stage；
A N-shaped polysilicon region 160, and the polysilicon region 160 and emitter phase are formed in the SiGe layer 150
Even；
Usually as ESD protective device in use, the emitter of HBT is grounded, collector connect chip input/output terminal or
Power end, base stage floating.When the esd pulse being positive relative to ground comes the input/output port or power port of chip, HBT
Collector junction it is reverse-biased, emitter junction positively biased；When esd pulse voltage is greater than the open base collector junction avalanche breakdown voltage BV of HBTCEO
When, a large amount of electron hole pair generates near the collector junction of HBT；Wherein, electronics passes through N-shaped well region 130, N-shaped buried layer area
120, N-shaped heavily doped region 141 and 142 flows out collector, and hole then passes through the emitter junction outflow emitter of positively biased；In this way, ESD
Electric current just passes through HBT device and releases.When the esd pulse being negative relative to ground comes the input/output port or power end of chip
Mouthful when, the collector junction positively biased of HBT, emitter junction is reverse-biased；When esd pulse voltage is greater than the open base emitter junction avalanche breakdown of HBT
Voltage BVECOWhen, a large amount of electron hole pair generates near the emitter junction of HBT；Wherein, electronics passes through N-shaped polysilicon region
160 outflow emitters, and hole then passes through the collector junction outflow collector of positively biased；It is let out in this way, ESD electric current just passes through HBT device
It bleeds off.Under normal conditions, the BV of HBTECOBV can be much smaller thanCEO；Therefore, use the HBT of base stage floating as ESD protective device
When, trigger voltage when coping with positive and negative esd pulse has biggish difference, it can not achieve identical bi-directional ESD protective capability,
It is easy to cause the ESD damage of internal circuit.
In view of the above-mentioned problems, the present invention put forward it is a kind of based on SiGe Heterojunction Bipolar Transistors HBT device architecture
The SCR device structure of bi-directional symmetrical；The structure is not only symmetrical in structure, for positive esd pulse and negative in ESD protective capability
Esd pulse relieving capacity having the same, i.e., it is functionally also symmetrical.
Summary of the invention
It is identical double it is an object of the invention to can not achieve for existing SiGe Heterojunction Bipolar Transistors HBT device
The problem of to ESD protective capability, provides a kind of bi-directional symmetrical based on SiGe Heterojunction Bipolar Transistors HBT device architecture
SCR device；The structure is not only symmetrical in structure, is also able to achieve identical bi-directional ESD protection.The technical solution adopted by the present invention
Are as follows:
One kind being based on the novel bidirectional ESD protective device of germanium silicon (SiGe) Heterojunction, comprising:
The first conduction type silicon substrate,
Second of conduction type buried layer is formed on the first described conduction type silicon substrate,
Second of conduction type well region is formed on second of conduction type buried layer,
Two of symmetrical distribution the first conduction type SiGe layers are formed on second of conduction type well region,
It is respectively formed N number of second of conductivity type polysilicon layer in the first each conduction type SiGe layer, N is positive whole
Number, wherein N number of second of conductivity type polysilicon layer jointed anode formed in the first conduction type SiGe layer of left side, it is right
N number of second of conductivity type polysilicon layer connection cathode formed in the first conduction type SiGe layer of side.
Further, the first conduction type SiGe layer of the left side is connected by first resistor with anode, the right side
The first conduction type SiGe layer is connected by second resistance with cathode, and the resistance value phase of the first resistor and second resistance
Together.
The present invention provides a kind of SCR structure for the protection of novel bi-directional ESD based on Ge-Si heterojunction technique, the structure
Based on the basic structure of SiGe heterojunction bipolar transistor HBT, two-way full symmetric SCR structure is constituted；When the SCR device
The minus earth of structure, it is positive esd pulse electric current which, which can both release relative to ground, and can also release is relative to ground
Negative esd pulse electric current has two-way identical ESD protective capability.
Detailed description of the invention
Fig. 1 is basic SiGe Heterojunction Bipolar Transistors HBT device architecture schematic diagram.
Fig. 2 is the novel bi-directional ESD of embodiment 1 protection SCR device structural schematic diagram.
Fig. 3 is the novel bi-directional ESD of embodiment 2 protection SCR device structural schematic diagram.
Fig. 4 is the novel bi-directional ESD of embodiment 3 protection SCR device structural schematic diagram.
Specific embodiment
The following describes the present invention in detail with reference to the accompanying drawings and specific embodiments.
Embodiment 1
The SCR structure for the protection of novel bi-directional ESD based on Ge-Si heterojunction technique, structure are provided in the present embodiment
And equivalent circuit is as shown in Fig. 2, the structure is the single emitter bi-directional symmetrical SCR device of base stage floating, comprising:
P-type silicon substrate 110；
N-shaped buried layer 120 is formed on the p-type silicon substrate 110；
N-shaped well region 130 is formed on the N-shaped buried layer 120；
130 upper left of N-shaped well region forms a p-type SiGe layer 151；
A N-shaped polysilicon region 161 is formed in the SiGe layer 151, and the polysilicon region 161 is connected with anode；
130 upper right of N-shaped well region forms a p-type SiGe layer 152；
A N-shaped polysilicon region 162 is formed in the SiGe layer 152, and the polysilicon region 162 is connected with cathode；
The p-type SiGe layer 151 and the symmetrical setting of p-type SiGe layer 152, the two-way SCR structure are one
It is made of N-shaped polysilicon region 161, p-type SiGe layer 151, N-shaped well region 130, p-type SiGe layer 152 and N-shaped polysilicon region 162
Five layers of npnpn structure.
It can see by its equivalent circuit diagram, which is by parasitic npn1 transistor, parasitic npn2 transistor
It being constituted with parasitic pnp transistor, wherein npn1 is made of N-shaped polysilicon region 161, p-type SiGe layer 151 and N-shaped well region 130,
Npn2 is made of N-shaped polysilicon region 162, p-type SiGe layer 152 and N-shaped well region 130, and pnp is by p-type SiGe layer 151, N-shaped well region
130 and p-type SiGe layer 152 constitute.
Usually as ESD protective device in use, the minus earth of SCR, anode connect the input/output terminal or power supply of chip
End.When the esd pulse being positive relative to ground comes the input/output port or power port of chip, N-shaped polysilicon region 161
The pn-junction formed with p-type SiGe layer 151 is reverse-biased, the pn-junction positively biased that the well region 130 of p-type SiGe layer 151 and N-shaped is formed, the trap of N-shaped
The pn-junction that area 130 and p-type SiGe layer 152 are formed is reverse-biased, and the pn-junction of p-type SiGe layer 152 and the formation of N-shaped polysilicon region 162 is just
Partially.When esd pulse voltage is greater than the open base emitter junction avalanche breakdown voltage BV of npn1ECO1With the open base current collection of npn2
Tie avalanche breakdown voltage BVCEO2The sum of when, a large amount of electron hole pair is attached in the emitter junction of npn1 pipe and the collector junction of npn2 pipe
Close to generate to form current channel, ESD electric current just passes through the SCR device and releases.When the esd pulse being negative relative to ground comes
To chip input/output port or power port when, the pn-junction that N-shaped polysilicon region 161 and p-type SiGe layer 151 are formed is just
Partially, the pn-junction that the well region 130 of p-type SiGe layer 151 and N-shaped is formed is reverse-biased, what the well region 130 and p-type SiGe layer 152 of N-shaped were formed
The pn-junction that pn-junction positively biased, p-type SiGe layer 152 and N-shaped polysilicon region 162 are formed is reverse-biased.When esd pulse voltage is greater than npn1's
Open base collector junction avalanche breakdown voltage BVCE01With the open base emitter junction avalanche breakdown voltage BV of npn2ECO2The sum of when,
A large amount of electron hole pair generates to form current channel, ESD near the collector junction of npn1 pipe and the emitter junction of npn2 pipe
Electric current just passes through the SCR device and releases.As can be seen from the above analysis, since the structure of parasitic npn1 pipe and npn2 pipe is
Symmetrically, and the structure of parasitism pnp pipe is also symmetrical.Therefore, use the symmetrical SCR device as ESD protective device,
Trigger voltage when coping with the esd pulse of positive negative sense is consistent, and can be realized identical bi-directional ESD protective capability.
Embodiment 2
The SCR structure for the protection of novel bi-directional ESD based on Ge-Si heterojunction technique, structure are provided in the present embodiment
As shown in figure 3, the structure is the multi-emitter bi-directional symmetrical SCR device structure of base stage floating, p-type SiGe described in structure
N number of N-shaped polysilicon region 161,163 is formed on layer 151 ..., 16 (2N+1), and whole polysilicon regions and sun
Extremely it is connected；N number of N-shaped polysilicon region 162,164 is formed in the p-type SiGe layer 152 ..., 16 (2N), and it is described complete
Portion's polysilicon region is connected with cathode；
The difference of the structure and the single emitter bi-directional symmetrical SCR device structure of base stage floating shown in Fig. 2 is only that
The number of emitter region pole item is different, its working principle is that identical.Under conditions of identical emitter area, using multi-emitting
The structure of pole item can effectively avoid emitter junction edge-crowding effect of current in bipolar transistor, so that device is with bigger
Emitter current is improved the ESD protective capability of device.
Embodiment 3
The SCR structure for the protection of novel bi-directional ESD based on Ge-Si heterojunction technique, structure are provided in the present embodiment
And equivalent circuit is as shown in figure 4, the structure is the single emitter bi-directional symmetrical SCR device that base stage is connected with emitter by resistance
Part structure, p-type SiGe layer described in structure 151 are connected by resistance R1 with anode, and the p-type SiGe layer 152 passes through resistance
R2 and cathode phase, and resistance R1, R2 resistance value is equal.
It can see from its equivalent circuit diagram, which is by parasitic npn1 transistor, parasitic npn2 transistor
It is constituted with parasitic pnp transistor；Wherein, npn1 is made of N-shaped polysilicon region 161, p-type SiGe layer 151 and N-shaped well region 130,
Npn2 is made of N-shaped polysilicon region 162, p-type SiGe layer 152 and N-shaped well region 130, and pnp is by p-type SiGe layer 151, N-shaped well region
130 and p-type SiGe layer 152 constitute；The base stage of parasitic npn1 pipe is connected by resistance R1 with emitter, the base stage of parasitic npn2 pipe
It is connected by resistance R2 with emitter, and the resistance value of R2 and R2 is equal.
Usually as ESD protective device in use, the minus earth of SCR, anode connect the input/output terminal or power supply of chip
End.When the esd pulse being positive relative to ground comes the input/output port or power port of chip, resistance R1, parasitism pnp pipe
A parasite current channel is formed with resistance R2.When the open base collector junction snowslide that esd pulse voltage is greater than parasitism pnp pipe is hit
Wear voltage BVCEOWhen, which just has electric current to flow to cathode from anode, and ESD electric current just passes through the SCR device and releases.Together
Reason, when the esd pulse being negative relative to ground comes the input/output port or power port of chip, and esd pulse voltage is greater than
When parasitic pnp pipe emitter junction avalanche breakdown voltage, electric current flows to anode from cathode in parasitic path, and ESD electric current just passes through the SCR
Device is released.As can be seen from the above analysis, as long as the resistance value of resistance R1 and R2 is identical, and the structure pair of parasitism pnp pipe
Claim, uses the symmetrical SCR device as ESD protective device, trigger voltage when coping with the esd pulse of positive negative sense is consistent
, and can be realized identical ESD protective capability.Meanwhile by adjusting the resistance value of resistance R1 and R2, the adjustable SCR device
The trigger voltage of part.
Bi-directional symmetrical SCR device structure shown in Fig. 4 can equally use the structure of multi-emitter item, working principle
It is identical as structure shown in Fig. 4, it just repeats no more here.
Finally, it is stated that above example is only to illustrate technical solution of the present invention rather than limits, although referring to preferable reality
The present invention is described for example, those skilled in the art should understand that, technical solution of the present invention can be carried out
Modification or equivalent replacement should all cover and want in right of the invention without departing from the objective and range of technical solution of the present invention
It asks in range.
Claims (2)
1. a kind of bidirectional ESD protective device based on Ge-Si heterojunction technique, comprising:
The first conduction type silicon substrate,
Second of conduction type buried layer is formed on the first described conduction type silicon substrate,
Second of conduction type well region is formed on second of conduction type buried layer,
Two of symmetrical distribution the first conduction type SiGe layers are formed on second of conduction type well region,
It is respectively formed N number of second of conductivity type polysilicon layer in the first each conduction type SiGe layer, N is positive integer,
In, N number of second of conductivity type polysilicon layer jointed anode formed in the first conduction type SiGe layer of left side, right side first
N number of second of conductivity type polysilicon layer connection cathode formed in kind conduction type SiGe layer.
2. by the bidirectional ESD protective device based on Ge-Si heterojunction technique described in claim 1, which is characterized in that the left side
The first conduction type SiGe layer is connected by first resistor with anode, the first conduction type SiGe layer of the right side passes through the
Two resistance are connected with cathode, and the first resistor is identical as the resistance value of second resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510976592.5A CN105374816B (en) | 2015-12-23 | 2015-12-23 | A kind of bidirectional ESD protective device based on Ge-Si heterojunction technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510976592.5A CN105374816B (en) | 2015-12-23 | 2015-12-23 | A kind of bidirectional ESD protective device based on Ge-Si heterojunction technique |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105374816A CN105374816A (en) | 2016-03-02 |
| CN105374816B true CN105374816B (en) | 2019-02-15 |
Family
ID=55376851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510976592.5A Active CN105374816B (en) | 2015-12-23 | 2015-12-23 | A kind of bidirectional ESD protective device based on Ge-Si heterojunction technique |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105374816B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108598076A (en) * | 2018-04-10 | 2018-09-28 | 电子科技大学 | A kind of adjustable ESD protective device of trigger voltage based on Ge-Si heterojunction technique |
| CN110459594B (en) * | 2019-08-29 | 2024-04-12 | 成都矽能科技有限公司 | Embedded isolation ring silicon controlled rectifier capable of being used for electrostatic discharge protection |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101281899A (en) * | 2008-05-16 | 2008-10-08 | 浙江大学 | PMOS pipe built-in bidirectional thyristor electrostatic protection device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7932582B2 (en) * | 2008-06-18 | 2011-04-26 | National Semiconductor Corporation | Compact dual direction BJT clamps |
| US20120153347A1 (en) * | 2010-12-17 | 2012-06-21 | National Semiconductor Corporation | ESD clamp with auto biasing under high injection conditions |
-
2015
- 2015-12-23 CN CN201510976592.5A patent/CN105374816B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101281899A (en) * | 2008-05-16 | 2008-10-08 | 浙江大学 | PMOS pipe built-in bidirectional thyristor electrostatic protection device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105374816A (en) | 2016-03-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100490151C (en) | Controlled silicon structure used for CMOS electrostatic discharge protection | |
| CN101840918B (en) | Silicon controlled rectifier electro-static discharge protective circuit structure triggered by diode | |
| CN101826523A (en) | Silicon controlled rectifier electrostatic discharge protection circuit structure triggered by grid controlled diode | |
| CN104716132B (en) | The thyristor and its circuit of a kind of low trigger voltage and high maintenance voltage | |
| CN111668209B (en) | Low-leakage silicon controlled rectifier for low-voltage ESD protection | |
| CN103165600B (en) | A kind of esd protection circuit | |
| CN105374816B (en) | A kind of bidirectional ESD protective device based on Ge-Si heterojunction technique | |
| CN104103635B (en) | ESD-protection structure | |
| CN110491875A (en) | A kind of bidirectional triode thyristor electrostatic protection device | |
| CN102315258B (en) | Parasitic thyristor and electrostatic protection circuit | |
| CN112563261B (en) | High-voltage protection integrated circuit of Complementary Metal Oxide Semiconductor (CMOS) auxiliary trigger Selective Catalytic Reduction (SCR) structure | |
| CN105374817B (en) | A kind of SCR device based on Ge-Si heterojunction technique | |
| CN102693980B (en) | A kind of controllable silicon ESD-protection structure of low trigger voltage | |
| CN110828453B (en) | Embedded P + injection segmented asymmetric silicon controlled rectifier electrostatic discharge device | |
| CN209374445U (en) | A kind of two-way SCR semiconductor protection device of novel low trigger voltage | |
| CN104183593B (en) | ESD-protection structure | |
| CN109638013A (en) | A kind of continuously adjustable SCR esd discharge structure of trigger voltage and its triggering implementation method | |
| CN102544068A (en) | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes | |
| CN107579065A (en) | A kind of high maintenance voltage thyristor electrostatic protection device | |
| CN102244076B (en) | Electrostatic discharge protective device for radio frequency integrated circuit | |
| CN103545306B (en) | ESD protection circuit | |
| CN209104152U (en) | A kind of SCR esd discharge structure that trigger voltage is continuously adjustable | |
| CN206602111U (en) | For the reversed flow restriction without internal source of stable pressure integrated circuit | |
| CN207250515U (en) | A kind of high maintenance voltage thyristor electrostatic protection device | |
| CN104241265A (en) | Electrostatic discharge protection structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |