CN105355176B - 显示面板与数组栅极驱动电路 - Google Patents
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- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G09G2300/0404—Matrix technologies
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- G09G2310/00—Command of the display device
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- G09G2310/0243—Details of the generation of driving signals
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Abstract
本案涉及一种显示面板,具有一显示区与一扇出区,与一数组栅极驱动电路,所述数组栅极驱动电路包括多级预充电模块,用于在所述扇出区将所述数组栅极驱动电路中相邻两扫描线的输出端分别连接于所述显示区对应的相邻两扫描线输出,每一级所述预充电模块包括一第一薄膜晶体管、一第二薄膜晶体管、一第三薄膜晶体管、一第四薄膜晶体管、一第五薄膜晶体管以及一第六薄膜晶体管。
Description
技术领域
本案涉及一种显示面板与数组栅极驱动电路,特别是用于薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display,TFT-LCD)的显示面板与数组栅极驱动电路。
背景技术
传统的TFT-LCD显示面板使用GOA(Gate On Array,栅级驱动芯片集成于数组基板)的基本架构如图1所示,显示面板1中包含显示区10、扇出区11、源极薄膜上芯片(Source-Chip On Film,S-COF)12、印刷电路板(Printed Circuit Board,PCB)13,数组栅极驱动电路会被设置于显示区与扇出区之间。
传统液晶面板的栅极驱动(gate driver)扫描薄膜晶体管(TFT)的栅极,透过数据线给像素电极充电。液晶在像素电场的作用下发生旋转而旋光以进行显示。而长的充电时间导致长的液晶响应时间,让像素电极间的互扰(crosstalk)现象加重。
因此,需要提出新的显示面板与数组栅极驱动电路,提高像素充电速度。
发明内容
本发明在传统数组栅极驱动电路中栅极侧的扇出区(Fan Out Area)增加额外逻辑单元,以实现相邻行的栅极线之间进行预充电(Precharge),以提高高像素充电速度。
本发明的一实施例提出一种显示面板,具有一显示区与一扇出区,与一数组栅极驱动(Gate On Array,GOA)电路,包括多级预充电模块,用于在所述扇出区将所述数组栅极驱动电路中相邻两扫描线的输出端分别连接于所述显示区对应的相邻两扫描线输出,每一级所述预充电模块包括一第一薄膜晶体管,所述第一薄膜晶体管的一源极与栅极连接于所述扫描线的一第一输出端,一漏极连接于一第一栅极线输出;一第二薄膜晶体管,所述第二薄膜晶体管的一栅极连接于所述扫描线的所述第一输出端,一漏极连接于上一级的所述预充电模块;一第三薄膜晶体管,所述第三薄膜晶体管的一栅极连接于所述扫描线的所述第一输出端,一漏极连接于所述第一栅极线输出;一第四薄膜晶体管,所述第四薄膜晶体管的一漏级连接于于所述第三薄膜晶体管的一源极;一栅极连接于所述扫描线的一第二输出端,一源极连接于一第二栅极线输出;一第五薄膜晶体管,所述第五薄膜晶体管的一栅极连接于所述扫描线的所述第二输出端,一源极连接于所述第二输出端,一漏极连接于所述第二栅极线输出;以及一第六薄膜晶体管,所述第六薄膜晶体管的一栅极连接于所述扫描线的所述第二输出端,一漏极连接于所述第二栅极线输出,一源极连接于下一级的所述预充电模块。
较佳地,当所述第一栅极输出端为高电压准位,所述第二栅极输出端为低电压准位时,所述第一薄膜晶体管、所述第三薄膜晶体管,与所述第四薄膜晶体管是被导通的,所述第二薄膜晶体管、所述第五薄膜晶体管,与所述第六薄膜晶体管是被关断的,且所述第一栅极线输出与所述第二栅极线输出都是高电压准位。
较佳地,当所述第一栅极输出端为低电压准位,所述第二栅极输出端为高电压准位时,所述第一薄膜晶体管、所述第三薄膜晶体管,与所述第四薄膜晶体管是被关断的,所述第二薄膜晶体管、所述第五薄膜晶体管,与所述第六薄膜晶体管是被导通的,且所述第一栅极线输出是低电压准位,所述第二栅极线输出是高电压准位。
较佳地,当所述第一栅极输出端与所述第二栅极输出端都为低电压准位时,所述第一薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管,与所述第六薄膜晶体管是被关断的,所述第二薄膜晶体管与所述第四薄膜晶体管是被导通的,且所述第一栅极线输出与所述第二栅极线输出都是低电压准位。
本发明在数组栅极驱动电路架构中实现预充电,加快充电速度,缩短液晶响应时间,减少像素电极间的互扰(crosstalk)现象。
为使本发明的上述目的、特征和优点能更明显易懂,下文特举较佳实施例并配合附图做详细说明。
附图说明
图1是传统栅极驱动面板的架构示意图;
图2是依据本发明一实施例的预充电模块电路图;以及
图3是本发明所述实施例中的预充电模块中栅极线讯号波形图。
具体实施方式
以下各实施例的说明是参考附加的图式,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。
如图1的显示面板架构,本发明的一实施例揭露了一显示面板1,具有一显示区10与一扇出区11,与一数组栅极驱动(Gate On Array,GOA)电路(无图标),数组栅极驱动电路被设置于显示区10与扇出区11,包括多级预充电模块14(无图示),图2中有预充电模块14的电路图,用于在所述扇出区11将所述数组栅极驱动电路中相邻两扫描线的输出端分别连接于所述显示区10对应的相邻两扫描线输出。请参照图2,图2是依据本发明一实施例的预充电模块14的电路图,如图2所示,每一级所述预充电模块14包括一第一薄膜晶体管M1,所述第一薄膜晶体管M1的一源极与栅极连接于所述扫描线的一第一栅极输出端G_OUT1,一漏极连接于一第一栅极线输出GL_OUT1;一第二薄膜晶体管M2,所述第二薄膜晶体管M2的一栅极连接于所述扫描线的所述第一栅极输出端G_OUT1,一漏极连接于上一级的所述预充电模块(无图标);一第三薄膜晶体管M3,所述第三薄膜晶体管M3的一栅极连接于所述扫描线的所述第一栅极输出端G_OUT1,一漏极连接于所述第一栅极线输出GL_OUT1;一第四薄膜晶体管M4,所述第四薄膜晶体管M4的一漏级连接于于所述第三薄膜晶体管M3的一源极;一栅极连接于所述扫描线的一第二栅极输出端G_OUT2,一源极连接于一第二栅极线输出GL_OUT2;一第五薄膜晶体管M5,所述第五薄膜晶体管M5的一栅极连接于所述扫描线的所述第二栅极输出端G_OUT2,一源极连接于所述第二栅极输出端G_OUT2,一漏极连接于所述第二栅极线输出GL_OUT2;以及一第六薄膜晶体管M6,所述第六薄膜晶体管M6的一栅极连接于所述扫描线的所述第二栅极输出端G_OUT2,一漏极连接于所述第二栅极线输出GL_OUT2,一源极连接于下一级的所述预充电模块(无图标)。
其中,当所述第一栅极输出端G_OUT1为高电压准位VH,所述第二栅极输出端G_OUT2为低电压准位VL时,所述第一薄膜晶体管M1、所述第三薄膜晶体管M3,与所述第四薄膜晶体管M4是被导通的,所述第二薄膜晶体管M2、所述第五薄膜晶体管M5,与所述第六薄膜晶体管M6是被关断的,且所述第一栅极线输出GL_OUT1与所述第二栅极线输出GL_OUT2都是高电压准位VH。当所述第一栅极输出端G_OUT1为低电压准位VL,所述第二栅极输出端G_OUT2为高电压准位VH时,所述第一薄膜晶体管M1、所述第三薄膜晶体管M3,与所述第四薄膜晶体管M4是被关断的,所述第二薄膜晶体管M2、所述第五薄膜晶体管M5,与所述第六薄膜晶体管M6是被导通的,且所述第一栅极线输出GL_OUT1是低电压准位VL,所述第二栅极线输出GL_OUT2是高电压准位VH。当所述第一栅极输出端G_OUT1与所述第二栅极输出端G_OUT2都为低电压准位VL时,所述第一薄膜晶体管M1、所述第三薄膜晶体管M3、所述第五薄膜晶体管M5,与所述第六薄膜晶体管M6是被关断的,所述第二薄膜晶体管M2与所述第四薄膜晶体管M4是被导通的,且所述第一栅极线输出GL_OUT1与所述第二栅极线输出GL_OUT2都是低电压准位VL。
请参照图3,图3是本发明所述实施例中的预充电模块14中栅极线讯号波形图。如图3所示,分别是所述第一栅极线输出GL_OUT1与第二栅极线输出GL_OUT2的波形。如图3所示,在GL_OUT1与GL_OUT2的充电波形会部分重迭,也就是说第二栅极线会在第一栅极线充电完成前开始充电,让充电效率提高,让本发明在数组栅极驱动电路架构中实现预充电,加快充电速度,缩短液晶响应时间,减少像素电极间的互扰(crosstalk)现象。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。
Claims (8)
1.一种显示面板,具有一显示区与一扇出区,与一数组栅极驱动(Gate On Array,GOA)电路,其特征在于,包括:
多级预充电模块,用于在所述扇出区将所述数组栅极驱动电路中相邻两扫描线的输出端分别连接于所述显示区对应的相邻两扫描线输出,每一级所述预充电模块包括:
一第一薄膜晶体管,所述第一薄膜晶体管的一源极与栅极连接于所述扫描线的一第一栅极输出端,一漏极连接于一第一栅极线输出端;
一第二薄膜晶体管,所述第二薄膜晶体管的一栅极连接于所述扫描线的第一栅极输出端,一漏极连接于上一级的所述预充电模块;
一第三薄膜晶体管,所述第三薄膜晶体管的一栅极连接于所述扫描线的第一栅极输出端,一漏极连接于所述第一栅极线输出端;
一第四薄膜晶体管,所述第四薄膜晶体管的一漏级连接于所述第三薄膜晶体管的一源极;一栅极连接于所述扫描线的一第二栅极输出端,一源极连接于一第二栅极线输出端;
一第五薄膜晶体管,所述第五薄膜晶体管的一栅极连接于所述扫描线的第二栅极输出端,一源极连接于第二栅极输出端,一漏极连接于所述第二栅极线输出端;以及
一第六薄膜晶体管,所述第六薄膜晶体管的一栅极连接于所述扫描线的第二栅极输出端,一漏极连接于所述第二栅极线输出端,一源极连接于下一级的所述预充电模块。
2.如权利要求1所述的显示面板,其特征在于,当所述第一栅极输出端为高电压准位,所述第二栅极输出端为低电压准位时,所述第一薄膜晶体管、所述第三薄膜晶体管,与所述第四薄膜晶体管是被导通的,所述第二薄膜晶体管、所述第五薄膜晶体管,与所述第六薄膜晶体管是被关断的,且所述第一栅极线输出端与所述第二栅极线输出端都是高电压准位。
3.如权利要求1所述的显示面板,其特征在于,当所述第一栅极输出端为低电压准位,所述第二栅极输出端为高电压准位时,所述第一薄膜晶体管、所述第三薄膜晶体管,与所述第四薄膜晶体管是被关断的,所述第二薄膜晶体管、所述第五薄膜晶体管,与所述第六薄膜晶体管是被导通的,且所述第一栅极线输出端是低电压准位,所述第二栅极线输出端是高电压准位。
4.如权利要求1所述的显示面板,其特征在于,当所述第一栅极输出端与所述第二栅极输出端都为低电压准位时,所述第一薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管,与所述第六薄膜晶体管是被关断的,所述第二薄膜晶体管与所述第四薄膜晶体管是被导通的,且所述第一栅极线输出端与所述第二栅极线输出端都是低电压准位。
5.一种数组栅极驱动电路,用于一显示设备中,所述显示设备具有一显示区与一扇出区,其特征在于,包括:
多级预充电模块,用于在所述扇出区将数组栅极驱动电路中相邻两扫描线的输出端分别连接于所述显示区对应的相邻两扫描线输出,每一级所述预充电模块包括:
一第一薄膜晶体管,所述第一薄膜晶体管的一源极与栅极连接于所述扫描线的一第一栅极输出端,一漏极连接于一第一栅极线输出端;
一第二薄膜晶体管,所述第二薄膜晶体管的一栅极连接于所述扫描线的第一栅极输出端,一漏极连接于上一级的所述预充电模块;
一第三薄膜晶体管,所述第三薄膜晶体管的一栅极连接于所述扫描线的第一栅极输出端,一漏极连接于所述第一栅极线输出端;
一第四薄膜晶体管,所述第四薄膜晶体管的一漏级连接于于所述第三薄膜晶体管的一源极;一栅极连接于所述扫描线的一第二栅极输出端,一源极连接于一第二栅极线输出端;
一第五薄膜晶体管,所述第五薄膜晶体管的一栅极连接于所述扫描线的第二栅极输出端,一源极连接于第二栅极输出端,一漏极连接于所述第二栅极线输出端;以及
一第六薄膜晶体管,所述第六薄膜晶体管的一栅极连接于所述扫描线的第二栅极输出端,一漏极连接于所述第二栅极线输出端,一源极连接于下一级的所述预充电模块。
6.如权利要求5所述的数组栅极驱动电路,其特征在于,当所述第一栅极输出端为高电压准位,所述第二栅极输出端为低电压准位时,所述第一薄膜晶体管、所述第三薄膜晶体管,与所述第四薄膜晶体管是被导通的,所述第二薄膜晶体管、所述第五薄膜晶体管,与所述第六薄膜晶体管是被关断的,且所述第一栅极线输出端与所述第二栅极线输出端都是高电压准位。
7.如权利要求5所述的数组栅极驱动电路,其特征在于,当所述第一栅极输出端为低电压准位,所述第二栅极输出端为高电压准位时,所述第一薄膜晶体管、所述第三薄膜晶体管,与所述第四薄膜晶体管是被关断的,所述第二薄膜晶体管、所述第五薄膜晶体管,与所述第六薄膜晶体管是被导通的,且所述第一栅极线输出端是低电压准位,所述第二栅极线输出端是高电压准位。
8.如权利要求5所述的数组栅极驱动电路,其特征在于,当所述第一栅极输出端与所述第二栅极输出端都为低电压准位时,所述第一薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管,与所述第六薄膜晶体管是被关断的,所述第二薄膜晶体管与所述第四薄膜晶体管是被导通的,且所述第一栅极线输出端与所述第二栅极线输出端都是低电压准位。
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