CN105304514A - Process monitoring method after etching semiconductor deep hole - Google Patents
Process monitoring method after etching semiconductor deep hole Download PDFInfo
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- CN105304514A CN105304514A CN201410345705.7A CN201410345705A CN105304514A CN 105304514 A CN105304514 A CN 105304514A CN 201410345705 A CN201410345705 A CN 201410345705A CN 105304514 A CN105304514 A CN 105304514A
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Abstract
The invention provides a process monitoring method after etching a semiconductor deep hole. The process monitoring method comprises the following steps: a. providing a test structure having a predetermined shape and size; b. measuring the mass to the test structure to obtain a tolerance range; c. measuring the mass of a wafer to be monitored, comparing the mass of the wafer to be monitored with the tolerance range, if the mass value of the wafer to be monitored is within the tolerance range, deeming that the etching depth of the deep hole has meet the requirements; and if the mass value of the wafer to be monitored is not within the tolerance range, deeming that the etching depth of the deep hole does not meet the process requirements, and adjusting the etching process conditions. According to the process monitoring method provided by the invention, a scatheless high-precision mass measurement method is adopted, and the mass of the silicon deep hole after silicon etching is measured to indirectly characterize whether the etching depth of the silicon deep hole meets the process requirements. An entire wafer is measured, and no specific test structure is needed, thereby being convenient and quick; and the feedback result is intuitive, rapid and accurate, and no damage is generated to the wafer.
Description
Technical field
The present invention relates to semiconductor fabrication process, especially, relate to the process monitoring method after a kind of semiconductor deep hole etching.
Technical background
Along with the development of semiconductor technology, multi-chip stacked package has become the important application direction surmounting Moore's Law.Wherein, in multi-chip stacked package technique, deep hole silicon etching (throughsiliconvia, TSV) is carried out to silicon chip and has become one of requisite important process.The silicon deep-hole structures that TSV etching technics is formed is shown in Fig. 1.Wherein, require that the silicon etching degree of depth is comparatively large in a lot of application, vertical wide ratio even reaches 20:1.How to carry out Efficient Characterization to the degree of depth of etching, be the practical problem that TSV integrated technique faces.
Method sees the cross section of wafer after silicon deep hole etching by scanning electron microscopy the most intuitively, but this method has destructiveness to wafer, and feedback result is very slow, the effective monitoring to processing procedure when cannot be directly used in volume production.For this reason, be badly in need of one intuitively, to the undamaged method for rapidly monitoring of wafer, after judging silicon deep hole etching, whether the degree of depth of etching reaches technological requirement.
Summary of the invention
The invention provides the process monitoring method after a kind of semiconductor deep hole etching, adopt undamaged high accuracy quality method for measurement indirectly to characterize silicon deep hole etching depth and whether reach technological requirement, fast, accurately and do not damage crystal circle structure.Concrete, the method comprises the following steps:
A., the test structure with reservation shape and size is provided;
B. measure the quality of described test structure, obtain range of tolerable variance;
C. measure the quality of wafer to be monitored, and compare with described range of tolerable variance, if the mass value of wafer to be monitored is in range of tolerable variance, then think that the etching depth of deep hole reaches requirement; If not in range of tolerable variance, then the etching depth of deep hole does not reach technological requirement, needs to adjust etch technological condition.
Wherein, before step b, comprise step b1: for the wafer of given model, analyzed by scanning electron microscopy, after determining wafer silicon deep hole etching, whether depth bounds reaches technological requirement, if reach technological requirement, then carries out step b.
Wherein, the concrete grammar of described step b is: for the wafer of given model, measure this wafer deep hole multiple batches of etched after quality, obtain deep hole etched after the excursion of quality, and according to the measurement target of measurement result definition wafer quality after deep hole etching and range of tolerable variance.
Present invention also offers the process monitoring method after a kind of semiconductor deep hole etching, comprise the following steps:
A., the test structure with reservation shape and size is provided;
B. measure described test structure and etched the of poor quality of front and back at deep hole, obtain range of tolerable variance;
C. the of poor quality and described range of tolerable variance measured before and after wafer to be monitored etching compares, if wafer to be monitored etching front and back is of poor quality in range of tolerable variance, then thinks that the etching depth of deep hole reaches requirement; If not in range of tolerable variance, then the etching depth of deep hole does not reach technological requirement, needs to adjust etch technological condition.
Wherein, wherein before step b, comprise step b1: for the wafer of given model, analyzed by scanning electron microscopy, after determining wafer silicon deep hole etching, whether depth bounds reaches technological requirement, if reach technological requirement, then carries out step b.
Wherein, for given wafer, the ropy method of measurement of described test structure before and after deep hole has etched is:
D1. before deep hole etching, measure wafer quality, obtain the front value of wafer quality;
D2., after deep hole etching, measure wafer quality, be worth after obtaining wafer quality;
D4. quality difference is automatically calculated by quality measurement equipment.
Wherein, in described step b, for the wafer of given model, measure this wafer deep hole multiple batches of etched after of poor quality, obtain deep hole etched after ropy excursion, and according to measurement result definition wafer the measurement target of quality and range of tolerable variance after deep hole etching.
The present invention adopts undamaged high accuracy quality method for measurement, by measuring the quality after silicon deep hole silicon etching, indirectly characterizing silicon deep hole etching depth and whether reaching technological requirement.Wafer full wafer is measured, and does not need fc-specific test FC structure, convenient and swift; And feedback result is directly perceived, fast, accurately, and to wafer not damaged.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is according to the measurement structure in a specific embodiment of the present invention.
Embodiment
The invention provides the process monitoring method after semiconductor deep hole etching, adopt undamaged high accuracy quality method for measurement indirectly to characterize silicon deep hole etching depth and whether reach technological requirement, fast, accurately and do not damage crystal circle structure.For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
Disclosing hereafter provides many different embodiments or example is used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the various specific technique that the invention provides and the example of material, but those of ordinary skill in the art can recognize the property of can be applicable to of other techniques and/or the use of other materials.It should be noted that parts illustrated in the accompanying drawings are not necessarily drawn in proportion.Present invention omits the description of known assemblies and treatment technology and process to avoid unnecessarily limiting the present invention.
The present invention adopts undamaged high accuracy quality method for measurement, by measuring the quality after silicon deep hole silicon etching, indirectly characterizing silicon deep hole etching depth and whether reaching technological requirement, does not need to destroy wafer, simply rapidly.Deep-hole etching process in the present invention includes but not limited to integrated circuit (IC) chip stacked package, and any feature meets formation deep-hole structures and the method in the present invention all can be adopted to carry out process monitoring.Can be learnt by accompanying drawing 1, after silicon deep hole etching, wafer quality will obviously reduce, based on this kind of principle, the present invention, by by measuring the quality of wafer after silicon deep hole etching, monitoring silicon deep-hole etching process and whether reaching technological requirement, and then judging that whether this technique is qualified.Concrete, the method comprises the following steps:
First, the test structure with reservation shape and size is provided.Concrete, first: on substrate, form silicon deep hole etching needs hard mask or photoresist layer, conventional hard mask is silicon oxide layer; Use the object of hard mask to be to obtain the silicon deep hole of the larger degree of depth, otherwise need very thick photoresist, this is difficult to obtain good etching effect in a lithographic process; Preferably, in the present embodiment, what described mask adopted is hard mask; Next, described hard mask applies photoresist and exposure imaging; Then carry out hard mask etching, open hard mask, expose silicon substrate; After carry out silicon deep hole etching, remove photoresist cleaning after obtain need silicon deep hole figure.
Next, measure the quality of described test structure, obtain range of tolerable variance.Concrete, first measure and there is no the quality of figure wafer as preposition; The wafer (being namely not used in the wafer for subsequent use finally cutting into chip product) of then preparation test forms silicon deep-hole structures by flow process; Determine that the wafer of a certain product type (can be destructive SEM or TEM for print to test after silicon deep hole etching, after choosing those silicon deep holes etching, technique has met the requirements of wafer as sample, this experimental procedures can be described as DOE) residual mass of wafer, measure multiple batches of without after the data of figure wafer and silicon deep hole wafer multi-disc, obtain wafer quality reduction or the difference of mass change that silicon deep hole etching reaches technological requirement; And determine the rear Mass lost amount of wafer silicon deep hole etching or the excursion of residual mass.
Can reasonable definition wafer quality reduction or the measurement target of residual mass and error range according to the above results.In the present embodiment, DOE obtains the wafer of a certain product type, is 200.352g without figure wafer quality; After silicon deep hole etching, wafer quality is 154.532g; Of poor quality is 45.82g; Through DOE test, determine the wafer residual mass excursion 7.582g that silicon deep hole etching reaches technological requirement; Or ropy excursion is 1.756g; Then judge that standard that silicon deep hole etching reaches technological requirement is the quality of remaining structure as 154.532 ± 7.582g or 45.82 ± 1.582; Wherein, after DOE experiment purpose finds silicon deep hole to etch exactly, the ropy excursion of the excursion (SPEC) of wafer residual mass or wafer etching front and back.In practical application, the two chooses any one effect that can realize measuring.
Concrete, when etching single crystal silicon forms deep hole, the dry etching that sulphur fluorine-based plasma can be adopted to etch is to carry out silicon deep hole etching; Also can adopt the etching liquid wet etchings such as KOH, TAMH, can also be the mixing etching of these dry method, wet etching.Flow or concentration, air pressure etc. the parameter of choose reasonable etching raw material control etching speed, make the requirement reaching silicon deep hole etching depth and steepness within preset time.Dry run can be that the high speed under uniform temperature N2 environment dries, or carries out drying based on kalimeris Pueraria lobota Buddhist nun principle to wafer.
Next, then, service quality measurement equipment measures wafer quality, wafer quality and range of tolerable variance is compared, and judges whether silicon deep hole etching reaches technological requirement.Wherein, for given wafer, the ropy method of measurement of described test structure before and after deep hole has etched is: before deep hole etching, measure wafer quality, obtains the front value of wafer quality; After deep hole etching, measure wafer quality, be worth after obtaining wafer quality; Automatically quality difference is calculated by quality measurement equipment.
Wherein, in described step b, for the wafer of given model, measure this wafer deep hole multiple batches of etched after of poor quality, obtain deep hole etched after ropy excursion, and according to measurement result definition wafer the measurement target of quality and range of tolerable variance after deep hole etching.
If wafer quality value is in range of tolerable variance, then think that the etching depth of deep hole reaches requirement; If not in range of tolerable variance, then the etching depth of deep hole does not reach technological requirement, needs to adjust etch technological condition.Concrete, the preferred precision instrument of quality measurement equipment, such as mechanical precision balance, precise electronic balance, semi-automatic/electric light of automatically raising the price projection damping precision balance etc.Such as, if wafer residual mass (range of tolerable variance by above-mentioned, ± 7.582g) in error range, can think that silicon deep hole etching reaches technological requirement; If wafer quality is not in error range, then thinks that silicon deep hole etching does not reach technological requirement, need reprocessing again, also send processing line back to by this batch sample and carry out secondarily etched.
The present invention adopts undamaged high accuracy quality method for measurement, by measuring the quality after silicon deep hole silicon etching, indirectly characterizing silicon deep hole etching depth and whether reaching technological requirement.Wafer full wafer is measured, and does not need fc-specific test FC structure, convenient and swift; And feedback result is directly perceived, fast, accurately, and to wafer not damaged.
Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection range of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other examples, those of ordinary skill in the art should easy understand maintenance scope in while, the order of processing step can change.
In addition, range of application of the present invention is not limited to the technique of the specific embodiment described in specification, mechanism, manufacture, material composition, means, method and step.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique existed at present or be about to develop, mechanism, manufacture, material composition, means, method or step later, wherein their perform the identical function of the corresponding embodiment cardinal principle that describes with the present invention or obtain the identical result of cardinal principle, can apply according to the present invention to them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.
Claims (7)
1. the process monitoring method after semiconductor deep hole etching, comprises the following steps:
A., the test structure with reservation shape and size is provided;
B. measure the quality of described test structure, obtain range of tolerable variance;
C. measure the quality of wafer to be monitored, and compare with described range of tolerable variance, if the mass value of wafer to be monitored is in range of tolerable variance, then think that the etching depth of deep hole reaches requirement; If not in range of tolerable variance, then the etching depth of deep hole does not reach technological requirement, needs to adjust etch technological condition.
2. process monitoring method according to claim 1, wherein before step b, comprise step b1: for the wafer of given model, analyzed by scanning electron microscopy, after determining wafer silicon deep hole etching, whether depth bounds reaches technological requirement, if reach technological requirement, then carry out step b.
3. process monitoring method according to claim 1, the concrete grammar of described step b is: for the wafer of given model, measure this wafer deep hole multiple batches of etched after quality, obtain deep hole etched after the excursion of quality, and according to the measurement target of measurement result definition wafer quality after deep hole etching and range of tolerable variance.
4. the process monitoring method after semiconductor deep hole etching, comprises the following steps:
A., the test structure with reservation shape and size is provided;
B. measure described test structure and etched the of poor quality of front and back at deep hole, obtain range of tolerable variance;
C. the of poor quality and described range of tolerable variance measured before and after wafer to be monitored etching compares, if wafer to be monitored etching front and back is of poor quality in range of tolerable variance, then thinks that the etching depth of deep hole reaches requirement; If not in range of tolerable variance, then the etching depth of deep hole does not reach technological requirement, needs to adjust etch technological condition.
5. process monitoring method according to claim 4, wherein, wherein before step b, comprise step b1: for the wafer of given model, analyzed by scanning electron microscopy, after determining wafer silicon deep hole etching, whether depth bounds reaches technological requirement, if reach technological requirement, then carry out step b.
6. process monitoring method according to claim 4, wherein, for given wafer, the ropy method of measurement of described test structure before and after deep hole has etched is:
D1. before deep hole etching, measure wafer quality, obtain the front value of wafer quality;
D2., after deep hole etching, measure wafer quality, be worth after obtaining wafer quality;
D3. quality difference is automatically calculated by quality measurement equipment.
7. process monitoring method according to claim 4, in described step b, for the wafer of given model, measure this wafer deep hole multiple batches of etched after of poor quality, obtain deep hole etched after ropy excursion, and according to measurement result definition wafer the measurement target of quality and range of tolerable variance after deep hole etching.
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| CN201410345705.7A CN105304514A (en) | 2014-07-18 | 2014-07-18 | Process monitoring method after etching semiconductor deep hole |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111029271A (en) * | 2019-12-26 | 2020-04-17 | 华虹半导体(无锡)有限公司 | Method for monitoring depth of groove |
| CN111261538A (en) * | 2020-03-25 | 2020-06-09 | 长江存储科技有限责任公司 | Wafer detection method and detection equipment |
| CN112670197A (en) * | 2020-12-22 | 2021-04-16 | 中国电子科技集团公司第四十九研究所 | Method for detecting micro-size etching depth and uniformity of ICP (inductively coupled plasma) process |
| WO2022134563A1 (en) * | 2020-12-23 | 2022-06-30 | 长鑫存储技术有限公司 | Manufacturing procedure monitoring method and manufacturing procedure monitoring system |
| CN114988351A (en) * | 2022-03-03 | 2022-09-02 | 武汉大学 | DRIE process error monitoring system and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06124922A (en) * | 1992-10-13 | 1994-05-06 | Oki Electric Ind Co Ltd | Dry etching termination detector |
| CN102842518A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Monitoring method after removing polycrystalline silicon dummy gate |
| CN103299404A (en) * | 2010-12-16 | 2013-09-11 | 伊雷克托科学工业股份有限公司 | Closed-loop silicon etching control method and system |
-
2014
- 2014-07-18 CN CN201410345705.7A patent/CN105304514A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06124922A (en) * | 1992-10-13 | 1994-05-06 | Oki Electric Ind Co Ltd | Dry etching termination detector |
| CN103299404A (en) * | 2010-12-16 | 2013-09-11 | 伊雷克托科学工业股份有限公司 | Closed-loop silicon etching control method and system |
| CN102842518A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Monitoring method after removing polycrystalline silicon dummy gate |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111029271A (en) * | 2019-12-26 | 2020-04-17 | 华虹半导体(无锡)有限公司 | Method for monitoring depth of groove |
| CN111261538A (en) * | 2020-03-25 | 2020-06-09 | 长江存储科技有限责任公司 | Wafer detection method and detection equipment |
| CN111261538B (en) * | 2020-03-25 | 2022-11-04 | 长江存储科技有限责任公司 | Wafer detection method and detection equipment |
| CN112670197A (en) * | 2020-12-22 | 2021-04-16 | 中国电子科技集团公司第四十九研究所 | Method for detecting micro-size etching depth and uniformity of ICP (inductively coupled plasma) process |
| CN112670197B (en) * | 2020-12-22 | 2023-07-28 | 中国电子科技集团公司第四十九研究所 | Method for detecting micro-size etching depth and uniformity of ICP process |
| WO2022134563A1 (en) * | 2020-12-23 | 2022-06-30 | 长鑫存储技术有限公司 | Manufacturing procedure monitoring method and manufacturing procedure monitoring system |
| CN114988351A (en) * | 2022-03-03 | 2022-09-02 | 武汉大学 | DRIE process error monitoring system and method |
| CN114988351B (en) * | 2022-03-03 | 2024-03-26 | 武汉大学 | DRIE process error monitoring system and method |
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