CN112670197A - Method for detecting micro-size etching depth and uniformity of ICP (inductively coupled plasma) process - Google Patents
Method for detecting micro-size etching depth and uniformity of ICP (inductively coupled plasma) process Download PDFInfo
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Abstract
A method for detecting micro-size etching depth and uniformity of an ICP (inductively coupled plasma) process relates to a method for detecting micro-size etching depth and uniformity of the ICP process. The method solves the problems of large measurement error, inconvenience in continuous etching, time and labor waste of the conventional method for detecting the depth and uniformity of the micro-size silicon microstructure etched by the ICP process. Determining the corrosion depth of the back surface of the wafer; etching the back surface of each unit of the wafer into a slope structure of 54.74 degrees by adopting an anisotropic wet method according to the determined etching depth; aligning the area to be etched with the slope structure by a double-sided photoetching alignment technology; and in the area to be etched of the wafer, etching the fixed line width structure by adopting an ICP (inductively coupled plasma) process, wherein no new etching structure is generated, the maximum depth of the ICP process in the etching width is calculated by utilizing the etching depth corresponding to the finally-generated etching structure, and the etching uniformity of the ICP process in the etching width is calculated. The method is suitable for detecting the etching depth and uniformity of the micro size in the ICP process.
Description
Technical Field
The invention relates to a method for detecting micro-size etching depth and uniformity by an ICP (inductively coupled plasma) process.
Background
With the development of an integration process and a micro-nano system technology, the characteristic size and the volume of a device are smaller and smaller, such as a resonance sensor, a comb tooth structure capacitance sensor and the like, and a microstructure processing technology with a high aspect ratio (the ratio of the groove depth to the groove width) is a key means for manufacturing the sensor. The emergence of the silicon deep etching technology-ICP (inductively coupled plasma) technology enables the technology to process very fine and complex MEMS structures. By adjusting the technological parameters such as the technological pressure, the gas flow, the bias power, the etching time and the like, the high structure aspect ratio (more than 20:1) can be obtained. However, due to the principle of the technology, there is a "lag effect", that is, the etching rate is reduced with the increase of the aspect ratio, and the reason for this effect is that the transportation of the etching example to the etching surface and the products escaping from the etching surface, etc. is difficult; shielding of ions and neutral ions; the distribution of the electric field on the etching surface is changed; difficulty in surface diffusion, etc. In order to observe the etching depth of a structure with a tiny size (< 5 μm), a common method is to use a cutting tool to cut the microstructure at the etching position, and then observe and measure the microstructure under an SEM (scanning electron microscope). Due to the fact that the mechanical rigidity of the microstructure is small, the scribing method has the problems that operation is not easy, positioning is difficult, the structure is damaged, and continuous etching cannot be carried out after scribing, so that the method is large in measurement error and inconvenient for carrying out technological tests of etching, observation and re-etching continuously. For the etching depth uniformity under the condition, the mode of repeatedly cutting and measuring by taking more measuring points is only adopted, and time and labor are wasted.
Disclosure of Invention
The invention aims to solve the problems of large measurement error, inconvenience in continuous etching, time and labor waste and the like of the conventional method for detecting the depth and uniformity of the micro-size silicon microstructure etched by the ICP (inductively coupled plasma) process, and provides a method for detecting the depth and uniformity of the micro-size etching of the ICP process.
The invention relates to a method for detecting micro-size etching depth and uniformity of an ICP (inductively coupled plasma) process, which comprises the following specific steps:
determining the corrosion depth of the back surface of a wafer according to the depth-width ratio rule of an etching line of an ICP process and the width of a line of a pattern to be etched;
secondly, etching the back surface of each unit of the wafer into a 54.74-degree slope structure by adopting an anisotropic wet method according to the etching depth determined in the first step;
aligning the area to be etched with the slope structure by a double-sided photoetching alignment technology;
step four, etching a fixed line width structure in a region to be etched of the wafer by adopting an ICP (inductively coupled plasma) process, observing whether an etched transparent line exists in a slope structure on the back of the wafer or not after etching is finished, if so, executing step five, otherwise, continuing etching until an etched structure is generated, and executing step five;
and step five, after the etching time T is continued, judging whether a new etching structure is generated, if so, continuing to etch the time T, judging whether the new etching structure is generated again until no new etching structure is generated after the time T, and calculating the maximum depth of the ICP process in the etching width by using the etching depth corresponding to the finally-generated etching structure.
And step six, calculating the etching uniformity of the ICP process at the width by using the etching depths of different wafer unit lines.
Further, in the first step, the method for determining the etching depth of the back surface of the wafer according to the depth-to-width ratio rule of the etching line of the ICP process comprises:
according to the depth-to-width ratio rule of the etched lines of the ICP process, the shortest distance of the etching depth of the lines to be detected is estimated, and the etching depth of the back of the wafer is made to be the shortest distance between the thickness of the wafer and the estimated etching depth of the lines to be detected.
Further, in the fifth step, the method for calculating the maximum depth of the ICP process at the etching width by using the etching depth corresponding to the finally appeared etched structure includes:
wherein, N is the number of lines from the line corresponding to the bottom angle position of the inclined plane to the last line etched through in the area to be etched, and L isLine stripIs the width of the line, LDistance between each otherIs the line spacing, HEtching ofDepth of etching, HThickness of the sheetIs the wafer thickness.
Further, in the sixth step, the method for calculating the uniformity of the ICP process during the etching of the aspect ratio by using the etching depths of the lines of different wafer units comprises the following steps:
finally, the lines A and B are etched through by using different units of the wafer, and the etching depth difference H is obtainedABAnd (3) calculating:
wherein HABIs the difference in depth of the etch between the A and B lines, HAIs the etching depth of A line, HBThe etching depth of the line B; when the difference of etching depth HABThe uniformity is best at 0.
The invention can simply and conveniently measure the maximum depth value and the etching depth uniformity which can be achieved by processing the micro-size silicon microstructure by adopting the ICP process. The process scheme is simple and the operation is easy. Meanwhile, the method provides possibility for the automatic test of the wafer level etching depth uniformity measurement, namely if the scanning extraction of the number of the whole etched structures can be realized, the automatic test of the etching depth of the whole wafer can be realized, the wafer does not need to be cut, and the depth can be detected while etching is carried out.
Drawings
FIG. 1 is a schematic view of a 54.74 degree slope etched from the back side of a wafer according to the present invention;
FIG. 2 is a schematic view of an area to be etched;
FIG. 3 is a schematic diagram illustrating the ICP etching of a wafer when the wafer is not etched through;
FIG. 4 is a schematic diagram of a line etch-through occurring during ICP etching of a wafer;
FIG. 5 is a schematic diagram of two line cuts occurring during ICP etching of a wafer;
FIG. 6 is a schematic drawing showing dimension marking of an ICP etched wafer;
FIG. 7 is a schematic diagram of a wafer etched using the method of an embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The first embodiment is as follows: the present embodiment is described below with reference to fig. 1 to 6, and the method for detecting the etching depth and uniformity of the micro-size in the ICP process in the present embodiment includes the following specific steps:
determining the corrosion depth of the back surface of a wafer according to the depth-width ratio rule of an etching line of an ICP process and the width of a line of a pattern to be etched;
secondly, etching the back surface of each unit of the wafer into a 54.74-degree slope structure by adopting an anisotropic wet method according to the etching depth determined in the first step;
aligning the area to be etched with the slope structure by a double-sided photoetching alignment technology;
step four, etching a fixed line width structure in a region to be etched of the wafer by adopting an ICP (inductively coupled plasma) process, observing whether an etched transparent line exists in a slope structure on the back of the wafer or not after etching is finished, if so, executing step five, otherwise, continuing etching until an etched structure is generated, and executing step five;
and step five, after the etching time T is continued, judging whether a new etching structure is generated, if so, continuing to etch the time T, judging whether the new etching structure is generated again until no new etching structure is generated after the time T, and calculating the maximum depth of the ICP process in the etching width by using the etching depth corresponding to the finally-generated etching structure.
And step six, calculating the etching uniformity of the ICP process at the width by using the etching depths of different wafer unit lines.
The invention can place a pattern with the size of 282 (thickness/sqrt (2)) mum on the front surface of a 4-inch wafer with the thickness of 400μm, can place at least 28 units (5μm considering the equal width of the space and the structure) on a micro-size structure (less than 5μm), and can place an etching depth step with the size of 7μm (5 sqrt (2)), thereby meeting the requirement of etching observation. And aligning the pattern to be etched with the slope structure by double-sided alignment lithography (as shown in FIG. 2). Then, processing a microstructure (as shown in figure 3) on the micro-size pattern by an ICP (inductively coupled plasma) process, taking out the wafer after the process is finished, observing the condition of an etching observation surface, judging whether a completely etched structure is generated or not, and if not, continuing to etch until the completely etched structure is generated; if (as in fig. 4), the etching is continued until no new etched structure is generated (as in fig. 5) after a sufficient time (obtained by amplifying by 2 times according to the etching depth step value and the etching rate), the etching depth corresponding to the finally-generated etched structure is the maximum depth which can be reached by the process under the line size. The uniformity of the etching depth can be calculated by observing the difference of the number of the etched structures generated at different positions on the wafer.
Further, in the first step, the method for determining the etching depth of the back surface of the wafer according to the depth-to-width ratio rule of the etching line of the ICP process comprises:
according to the depth-to-width ratio rule of the etched lines of the ICP process, the shortest distance of the etching depth of the lines to be detected is estimated, and the etching depth of the back of the wafer is made to be the shortest distance between the thickness of the wafer and the estimated etching depth of the lines to be detected.
In the embodiment, because the slope surfaces at other angles of the monocrystalline silicon material have a very low KOH wet etching rate, and the speed of forming the included angle of 54.74 degrees between the crystal surfaces is high, the observation rate can be increased by adopting the slope at the angle of 54.74 degrees as the observation slope.
Further, in the fifth step, the method for calculating the maximum depth of the ICP process at the etching width by using the etching depth corresponding to the finally appeared etched structure includes:
wherein, N is the number of lines from the line corresponding to the bottom angle position of the inclined plane to the last line etched through in the area to be etched, and L isLine stripIs the width of the line, LDistance between each otherIs the line spacing, HEtching ofDepth of etching, HThickness of the sheetIs the wafer thickness.
Further, in the sixth step, the method for calculating the uniformity of the ICP process during the etching of the aspect ratio by using the etching depths of the lines of different wafer units comprises the following steps:
finally, the lines A and B are etched through by using different units of the wafer, and the etching depth difference H is obtainedABAnd (3) calculating:
wherein HABIs the difference in depth of the etch between the A and B lines, HAIs the etching depth of A line, HBThe etching depth of the line B; when the difference of etching depth HABThe uniformity is best at 0.
In this embodiment, the lines a and the lines B are the lines etched through at the end of different wafer units.
The specific embodiment is as follows: this embodiment is described with reference to fig. 7;
selecting a monocrystalline silicon (100) material with the thickness of 400 mu m, oxidizing, growing SiO2/SiN by LPCVD, carrying out single-sided photoetching on the back side to form an anisotropic etching pattern, removing SiO2/SiN on the back side by RIE (reactive ion etching), carrying out anisotropic wet etching on KOH, carrying out double-sided alignment photoetching, forming a micro-size etching pattern on the front side, using the photoresist as a mask, carrying out ICP (inductively coupled plasma) etching process on the front side, observing whether a through etching structure is generated by using a microscope in the etching process, and judging and calculating according to the above contents to finally obtain the etching depth and uniformity.
The specific manufacturing steps are as follows:
1. and (3) oxidation: the oxidation thickness was 360nm using an L4514-3/QXG type oxidation oven.
LPCVD: the silicon nitride thickness was 600nm using TS6303 LPCVD.
3. Photoetching: and performing single-side photoetching by using an EVG-620 photoetching machine to obtain a photoresist AZ 1500.
RIE: and etching the silicon by using a PHANTOM II type etching machine to remove SiO 2/SiN.
KOH wet etching: heating to 80 ℃ by using 39% by weight of KOH solution, and etching to the depth of 360-370 mu m.
6. Photoetching: and performing double-sided alignment photoetching by using an EVG-620 photoetching machine, and photoresist AZ 1500.
7. Back ICP etching: using AZ1500 photoresist as a mask, Alcatel 601E type ICP etching machine was used.
8. And (4) checking: using STM-6OLYMPUS measuring microscope, turn on front and back light sources simultaneously and observe whether there is a structure etched through.
9. And calculating the etching depth and the uniformity according to the method.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.
Claims (4)
1. A method for detecting micro-size etching depth and uniformity of an ICP process is characterized by comprising the following specific steps:
determining the corrosion depth of the back surface of a wafer according to the depth-width ratio rule of an etching line of an ICP process and the width of a line of a pattern to be etched;
secondly, etching the back surface of each unit of the wafer into a 54.74-degree slope structure by adopting an anisotropic wet method according to the etching depth determined in the first step;
aligning the area to be etched with the slope structure by a double-sided photoetching alignment technology;
step four, etching a fixed line width structure in a region to be etched of the wafer by adopting an ICP (inductively coupled plasma) process, observing whether an etched transparent line exists in a slope structure on the back of the wafer or not after etching is finished, if so, executing step five, otherwise, continuing etching until an etched structure is generated, and executing step five;
and step five, after the etching time T is continued, judging whether a new etching structure is generated, if so, continuing to etch the time T, judging whether the new etching structure is generated again until no new etching structure is generated after the time T, and calculating the maximum depth of the ICP process in the etching width by using the etching depth corresponding to the finally-generated etching structure.
And step six, calculating the etching uniformity of the ICP process at the width by using the etching depths of different wafer unit lines.
2. The method for detecting the etching depth and the uniformity of the micro-size in the ICP process as claimed in claim 1, wherein the method for determining the etching depth of the back surface of the wafer according to the depth-to-width ratio rule of the etching line in the ICP process in the step one comprises the following steps:
according to the depth-to-width ratio rule of the etched lines of the ICP process, the shortest distance of the etching depth of the lines to be detected is estimated, and the etching depth of the back of the wafer is made to be the shortest distance between the thickness of the wafer and the estimated etching depth of the lines to be detected.
3. The method for detecting the etching depth and the uniformity of the micro-size of the ICP process as recited in claim 2, wherein the method for calculating the maximum depth of the ICP process in the etching width by using the etching depth corresponding to the last occurring etched structure in the step five comprises the following steps:
wherein, N is the number of lines from the line corresponding to the bottom angle position of the inclined plane to the last line etched through in the area to be etched, and L isLine stripIs the width of the line, LDistance between each otherIs the line spacing, HEtching ofDepth of etching, HThickness of the sheetIs the wafer thickness.
4. The method for detecting the micro-size etching depth and the uniformity of the ICP process as claimed in claim 3, wherein in the sixth step, the etching depth of lines of different wafer units is utilized, and the method for calculating the uniformity of the ICP process in the etching of the aspect ratio comprises the following steps:
finally, the lines A and B are etched through by using different units of the wafer, and the etching depth difference H is obtainedABAnd (3) calculating:
wherein HABIs the difference in depth of the etch between the A and B lines, HAIs the etching depth of A line, HBThe etching depth of the line B; when the difference of etching depth HABThe uniformity is best at 0.
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| CN102446749A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Method for achieving accurate graphic positioning during observation using scanning electron microscope |
| CN105304514A (en) * | 2014-07-18 | 2016-02-03 | 中国科学院微电子研究所 | Process monitoring method after etching semiconductor deep hole |
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| CN102446749A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Method for achieving accurate graphic positioning during observation using scanning electron microscope |
| CN105304514A (en) * | 2014-07-18 | 2016-02-03 | 中国科学院微电子研究所 | Process monitoring method after etching semiconductor deep hole |
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