CN106024758A - Advanced control method of polysilicon gate critical dimension - Google Patents
Advanced control method of polysilicon gate critical dimension Download PDFInfo
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- CN106024758A CN106024758A CN201610510996.XA CN201610510996A CN106024758A CN 106024758 A CN106024758 A CN 106024758A CN 201610510996 A CN201610510996 A CN 201610510996A CN 106024758 A CN106024758 A CN 106024758A
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- Prior art keywords
- semiconductor
- polycrystalline silicon
- advanced
- control method
- grid electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
The present invention provides an advanced control method of polysilicon gate critical dimension. The method is used for carrying out processing control on a semiconductor device when a polysilicon gate film structure is processed. The method includes the following steps that: a test semiconductor pattern control wafer is provided, wherein the test semiconductor pattern control wafer is used for simulating processing parameters for testing the semiconductor device; test semiconductor processing is performed on the test semiconductor pattern control wafer in the semiconductor device; the current processing parameters of the semiconductor device are obtained based on the test semiconductor processing; the current process parameters are updated to an advanced processing process control system; and the advanced processing process control system controls the semiconductor device based on the current processing parameters to process the polysilicon gate film structure. With the advanced control method of the invention adopted, the stability of semiconductor processing can be controlled under a condition that the processing parameters of the semiconductor device shift, and the problem of the stability of semiconductor processing of semiconductor devices in different batches and before and after equipment cavity maintenance can be solved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to the advanced person of a kind of critical size of polycrystalline silicon grid electrode
Control method.
Background technology
Along with integrated circuit technique enter the super large-scale integration epoch, the process of integrated circuit to
65nm and smaller size of structural development, IC chip function and performance constantly strengthen and
Feature sizes of semiconductor devices constantly reduces so that integrated circuit production line cost of investment becomes the highest
High, thus the accurate control of semiconductor technology is just particularly important, especially to quasiconductor between different batches
Batch part (Run-to-Run, the R2R) technology stability of device.
After semiconductor technology enters 65nm and smaller szie, process window during semiconductor device fabrication becomes
Obtain more and more less, IDE and detection equipment are proposed tightened up process control needs.In the past
Statistical Process Control (Statistical Process Control, be called for short SPC) and independent to certain parameter
Control method the most do not adapt to current process specifications.In order to improve production efficiency of equipment, make technique
Production line possesses extendability, motility, improves product quality and seriality, Advanced process control
(Advanced Process Control is called for short APC) obtains concern and the further investigation of people day by day.
Advanced process control system system combines SPC and controls with feedback, utilizes process data data in the past,
According to the suitable model of target selection reached required for last and control strategy, further combined with front together
Semiconductor substrate parameter prediction in operation goes out device parameter or the technique of next batch semiconductor processes
Parameter is arranged, timely rectification error, reduces because board is aging, material lifetime or the change of surrounding regulation
The equipment drift caused.Utilize advanced process control system to unite, help to ensure that semiconductor equipment and process
And the good stable operation of equipment, reduce the variation of semiconductor device output, improve the equipment of semiconductor equipment
The finished product yield of utilization ratio and semiconductor device.
As a example by polysilicon gate critical feature size controls, owing to critical size of polycrystalline silicon grid electrode is to device
The electric property of part has vital impact, prior art after semiconductor technology enters into 65nm,
It is widely used APC system critical size of polycrystalline silicon grid electrode is controlled, high stability many to obtain
Polysilicon gate critical dimension line width size.
The control parameter of polysilicon gate critical feature size is mainly by now widely used APC system
Horizontal stroke is controlled by being worth the change of ADI (After Develop Inspection, ADI) before polysilicon gate
The stability of value (After Etch Inspection, AEI) after the modification time has reached polysilicon gate.
These bases that arrange controlling parameter are regulation and control quantitative on the basis of setting fixing lateral etch rate
The lateral etching time.But this control calculates etch period under obtaining fixing etch rate, for
During the drift of etching apparatus generation etch rate, just it is difficult to control to the stability of critical size of polycrystalline silicon grid electrode.
Accordingly, it would be desirable to the control method of a kind of semiconductor technology Advanced process control, it is possible at semiconductor equipment
Technological parameter drift about in the case of, control semiconductor technology stability, especially between different batches
The particularly stability of the semiconductor technology before and after etching cavity maintaining.
Summary of the invention
The problem that the present invention solves there is provided the advanced control method of a kind of critical size of polycrystalline silicon grid electrode,
The stability of semiconductor technology in the case of the technological parameter of semiconductor equipment drifts about, can be controlled,
Solve between different batches and the stability problem of semiconductor technology before and after equipment cavity maintaining.
In order to solve the problems referred to above, the present invention provides the Dynamic matrix control side of a kind of critical size of polycrystalline silicon grid electrode
Method, for semiconductor equipment being carried out technology controlling and process when polysilicon gate membrane structure carries out technique, including:
Thering is provided test semiconductor figure control wafer, described test semiconductor figure control wafer is partly led for simulation test
The technological parameter of body equipment；
Described test semiconductor figure control wafer is carried out by described semiconductor equipment test semiconductor technology；
The current process parameter of described semiconductor equipment is obtained based on described test semiconductor technology；
Described current process parameter is updated to advanced technologies Process Control System；
Described advanced technologies Process Control System is based on semiconductor equipment described in described current process state modulator
Polysilicon gate membrane structure is carried out technique.
Alternatively, described semiconductor equipment is etching apparatus, and polysilicon gate membrane structure is for being set in turn in
Silicon oxide layer in Semiconductor substrate, polycrystalline silicon gate layer, hard mask layer, bottom anti-reflection layer, photoresist
Layer.
Alternatively, described current process parameter is the etch rate of etching apparatus.
Alternatively, the number of described test semiconductor figure control wafer is 3-5.
Alternatively, the number of described test semiconductor figure control wafer is 3.
Alternatively, described test semiconductor figure control wafer reusable edible.
Alternatively, the current process parameter of described semiconductor figure control wafer is etch rate, described etch rate
By testing bottom anti-reflection layer critical dimension line width change before and after etching technics, etching technics time
Calculate and obtain.
Alternatively, described critical dimension line width utilizes optics live width measuring instrument or critical size scanning electron to show
Micro mirror is measured and is obtained.
Alternatively, the structure in described test semiconductor figure control wafer has identical with polysilicon gate very thin films
Bottom anti-reflective Rotating fields, figure and density.
Alternatively, described based on current process parameter for based on current process parameter and combine quasiconductor and set
Standby process parameter drift amount carries out quasiconductor work to the polycrystalline silicon gate layer in polysilicon gate membrane structure
Skill.
Compared with prior art, present invention have the advantage that
The advanced control method of the critical size of polycrystalline silicon grid electrode that the present invention provides, utilizes test quasiconductor figure
Shape control wafer is for the technological parameter of simulation test semiconductor equipment, it is thus achieved that the current process ginseng of semiconductor equipment
To described, number, treats that process semiconductor substrate carries out semiconductor technology based on current process parameter, solves and partly lead
In the case of the technological parameter of body equipment drifts about, how to control the stability problem of semiconductor technology, carry
The stability of the semiconductor technology between high different batches and before and after etching cavity maintaining.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the advanced control method of the critical size of polycrystalline silicon grid electrode of the present invention.
Fig. 2 is the polysilicon gate membrane structure schematic diagram of one embodiment of the invention.
Fig. 3-Fig. 4 is that the present invention utilizes test semiconductor figure control wafer to carry out the work of simulation test semiconductor equipment
The principle explanation schematic diagram of skill parameter.
Detailed description of the invention
The advanced control method of existing critical size of polycrystalline silicon grid electrode is typically to join in the technique of semiconductor equipment
Pre-set in the case of number is constant and control parameter.But in practice, in semiconductor processes,
Most of semiconductor production equipment processes can regard non-linear process, quasiconductor as from the angle controlled
The technological parameter of equipment can over time and technique is drifted about, the advanced person arranged based on constant rate of speed
Carry out semiconductor technology under the control of the control parameter of technical process, frequently can lead to produce between different batches
The appearance larger difference of product.In order to ensure the yield of the semiconductor device ultimately formed and control cost, advanced
Process control technology is increasingly being applied to the impact that abatement apparatus characteristic drift brings.But half
Implement Advanced process control during semiconductor process and also deposit problems with:
(1) in semiconductor processes the technological parameter of a lot of semiconductor equipments all exist gradual drift and
Sudden change drift.As a example by polycrystalline silicon gate grid etching process, in etching process, etch by-products can be gradually deposited at
Gradual drift is formed in etching cavity inner wall surface；And more renew when cavity maintaining or clean after
After internal wall member, etching apparatus can form step disturbance, thus causes sudden change drift.Above-mentioned also become drift and
Sudden change drift can cause technological parameter the most constant.
(2) technique of semiconductor device manufactures process is a series of batch process, in every batch half
In semiconductor process, device controller is required for setting corresponding control parameter and other technological parameters.Same half
Conductor device is possibly used for different operations or produces different products so that processing parameter is necessary
Change frequently.Therefore, the technological parameter of semiconductor equipment is not constant.
In above-mentioned two situations, how to carry out the setting of the control parameter of advanced technologies process control, to solve
In semiconductor processes, technological parameter drift and parameter set the impact changed semiconductor technology, especially
It is that technological parameter drift and parameter set changes in 65nm and the manufacture of smaller szie semiconductor technology
In the case of semiconductor technology impact is become apparent from, how to carry out semiconductor technology Advanced process control
Control method.
In order to solve the problems referred to above, the present invention provides the Dynamic matrix control side of a kind of critical size of polycrystalline silicon grid electrode
Method, refer to shown in Fig. 1, and Fig. 1 is the advanced control method of the critical size of polycrystalline silicon grid electrode of the present inventionSchematic flow sheet, described method includes:
Step S1, it is provided that test semiconductor figure control wafer, described test semiconductor figure control wafer is used for simulating
The technological parameter of test semiconductor equipment；
Step S2, tests described test semiconductor figure control wafer in described semiconductor equipment and partly leads
Body technology；
Step S3, obtains the current process parameter of described semiconductor equipment based on described test semiconductor technology；
Step S4, is updated to advanced technologies Process Control System by described current process parameter；
Step S5, described advanced technologies Process Control System is based on described in described current process state modulator half
Conductor device carries out technique to polysilicon gate membrane structure.
Below in conjunction with specific embodiment, technical scheme is further elaborated.
As an embodiment, described semiconductor equipment is etching apparatus.With reference to the polysilicon shown in Fig. 2
Grid membrane structure schematic diagram.Polysilicon membrane structure is arranged in Semiconductor substrate 10, from bottom to top,
Described polysilicon membrane structure includes: the silicon oxide layer 11 that is arranged in Semiconductor substrate, polysilicon gate
Layer 12, hard mask layer 13, bottom anti-reflection layer 14, photoresist layer 15.Described polycrystalline silicon gate layer 12
To will perform etching under control by the advanced technologies Process Control System of the present invention follow-up.
In other examples, the advanced control method of the critical size of polycrystalline silicon grid electrode of the present invention also may be used
For controlling other semiconductor equipments.
In order to ensure the accuracy of the current process parameter finally obtained, test quasiconductor of the present invention
Structure in figure control wafer and polysilicon gate very thin films have identical bottom anti-reflective Rotating fields, figure with
And density.In order to ensure the accuracy of the current process parameter finally obtained, described test semiconductor figure control
Structure on sheet and polysilicon gate very thin films have identical bottom anti-reflective Rotating fields, figure and density.
Refer to the present invention shown in Fig. 3-Fig. 4 utilizes test semiconductor figure control wafer to carry out simulation test quasiconductor and set
The principle explanation schematic diagram of standby technological parameter.Test semiconductor figure control wafer includes: Semiconductor substrate 20,
Be set in turn in silicon oxide layer 21 in Semiconductor substrate 20, polycrystalline silicon gate layer 22, hard mask layer 23,
Bottom anti-reflection layer 24, photoresist layer 25.
As an embodiment, test semiconductor figure control is after etching through etching apparatus, by various surveys
Amount means, it is possible to obtain the current process parameter of etching apparatus.In the present embodiment, described current process parameter
For etch rate.Therefore, the present invention tests the etching speed of etching apparatus by test semiconductor figure control wafer
Rate.
Specifically, described etch rate is by testing quasiconductor control wafer bottom anti-reflection layer at etching technics
Critical dimension line width change front and back, etching technics Time Calculation obtain.Described critical dimension line width can be in order to
Obtain with optics wire width measuring instrument or critical size scanning electron microscopy measurement.Before etching technics, test
ADI it is worth before polysilicon gate；After etching technics terminates, after test polysilicon gate, it is worth AEI.Pass through polycrystalline
The skew of semiconductor equipment during the difference prediction polysilicon gate process of the front value of silicon gate and rear value, and
In advance this skew is adjusted, during to polysilicon gate process, utilizes the technique ginseng more optimized
Number carries out technique.The number of test semiconductor figure control wafer Semiconductor substrate of the present invention is 3-5.
Described test quasiconductor is used for testing semiconductor figure control wafer and carries out testing semiconductor technology.Test quasiconductor
Number is unsuitable too much, and too much semiconductor figure control wafer not only wastes production capacity, and can make by test half
The current process parameter that conductor fig control wafer obtains is inaccurate.The number of test semiconductor figure control wafer is the most not
The most very few, if only testing a piece of, it is not enough to obtain technological parameter accurately.As preferred embodiment.Institute
The number stating semiconductor figure control wafer is 3.
The present invention forms quasiconductor in the structure testing the test semiconductor figure control wafer of etching apparatus
Film layer structure, described semiconductor film Rotating fields can utilize dry method to remove photoresist after a procedure and remove and be again coated with
Glue and development exposure, thus described test semiconductor figure control wafer can recycle.
To sum up, the advanced control method of the critical size of polycrystalline silicon grid electrode that the present invention provides, utilize test partly to lead
Volume graphic control wafer is for the technological parameter of simulation test semiconductor equipment, it is thus achieved that the current work of semiconductor equipment
Skill parameter, carries out semiconductor technology based on current process parameter to described polysilicon gate, solves quasiconductor
In the case of the technological parameter of equipment drifts about, how to control the stability problem of semiconductor technology, improve
The stability of the semiconductor technology between different batches and before and after etching cavity maintaining.
Therefore, above-mentioned preferred embodiment is only technology design and the feature of the explanation present invention, its object is to allow
Person skilled in the art will appreciate that present disclosure and implements according to this, can not limit this with this
The protection domain of invention.All equivalence changes made according to spirit of the invention or modification, all should contain
Within protection scope of the present invention.
Claims (10)
1. an advanced control method for critical size of polycrystalline silicon grid electrode, for entering at polysilicon gate membrane structure
During row technique, semiconductor equipment is carried out technology controlling and process, it is characterised in that including:
Thering is provided test semiconductor figure control wafer, described test semiconductor figure control wafer sets for simulation test quasiconductor
Standby technological parameter；
Described test semiconductor figure control wafer is carried out by described semiconductor equipment test semiconductor technology；
The current process parameter of described semiconductor equipment is obtained based on described test semiconductor technology；
Described current process parameter is updated to advanced technologies Process Control System；
Described advanced technologies Process Control System based on semiconductor equipment described in described current process state modulator to many
Polysilicon gate membrane structure carries out technique.
2. the advanced control method of critical size of polycrystalline silicon grid electrode as claimed in claim 1, it is characterised in that
Described semiconductor equipment is etching apparatus, and polysilicon gate membrane structure is for being set in turn in quasiconductor lining
Silicon oxide layer at the end, polycrystalline silicon gate layer, hard mask layer, bottom anti-reflection layer, photoresist layer.
3. the advanced control method of critical size of polycrystalline silicon grid electrode as claimed in claim 2, it is characterised in that
Described current process parameter is the etch rate of etching apparatus.
4. the advanced control method of critical size of polycrystalline silicon grid electrode as claimed in claim 1 or 2, its feature exists
In, the number of described test semiconductor figure control wafer is 3-5.
5. the advanced control method of critical size of polycrystalline silicon grid electrode as claimed in claim 4, it is characterised in that
The number of described test semiconductor figure control wafer is 3.
6. the advanced control method of critical size of polycrystalline silicon grid electrode as claimed in claim 2, it is characterised in that
Described test semiconductor figure control wafer reusable edible.
7. the advanced control method of critical size of polycrystalline silicon grid electrode as claimed in claim 6, it is characterised in that
The current process parameter of described semiconductor figure control wafer is etch rate, and described etch rate is by test
Bottom anti-reflection layer critical dimension line width before and after etching technics changes, etching technics Time Calculation obtains
?.
8. the advanced control method of critical size of polycrystalline silicon grid electrode as claimed in claim 7, it is characterised in that
Described critical dimension line width utilizes optics live width measuring instrument or critical size scanning electron microscopy measurement to obtain
?.
9. the advanced control method of critical size of polycrystalline silicon grid electrode as claimed in claim 2, it is characterised in that
Structure in described test semiconductor figure control wafer and polysilicon gate very thin films have identical bottom anti-reflective
Penetrate Rotating fields, figure and density.
10. the advanced control method of critical size of polycrystalline silicon grid electrode as claimed in claim 2, its feature exists
In, described is based on current process parameter and the work that combines semiconductor equipment based on current process parameter
Skill parameter shift amount carries out semiconductor technology to the polycrystalline silicon gate layer in polysilicon gate membrane structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610510996.XA CN106024758A (en) | 2016-06-30 | 2016-06-30 | Advanced control method of polysilicon gate critical dimension |
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| CN201610510996.XA CN106024758A (en) | 2016-06-30 | 2016-06-30 | Advanced control method of polysilicon gate critical dimension |
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| CN201610510996.XA Pending CN106024758A (en) | 2016-06-30 | 2016-06-30 | Advanced control method of polysilicon gate critical dimension |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113506759A (en) * | 2021-06-28 | 2021-10-15 | 上海华虹宏力半导体制造有限公司 | Forming method of critical dimension on-line monitoring structure |
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| CN1837997A (en) * | 2005-03-07 | 2006-09-27 | 台湾积体电路制造股份有限公司 | Etching operation management systems and methods, and electronic device manufactured thereby |
| CN1905134A (en) * | 2005-07-25 | 2007-01-31 | 台湾积体电路制造股份有限公司 | Controlling method for gate formation of semiconductor device |
| CN101329986A (en) * | 2007-06-21 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Etching method |
| CN101673659A (en) * | 2008-09-10 | 2010-03-17 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting measurement stability of tester tables |
| CN101834114A (en) * | 2009-03-11 | 2010-09-15 | 台湾积体电路制造股份有限公司 | Advanced process control method for gate profile and system for fabricating integrated circuit |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1837997A (en) * | 2005-03-07 | 2006-09-27 | 台湾积体电路制造股份有限公司 | Etching operation management systems and methods, and electronic device manufactured thereby |
| CN1905134A (en) * | 2005-07-25 | 2007-01-31 | 台湾积体电路制造股份有限公司 | Controlling method for gate formation of semiconductor device |
| CN101329986A (en) * | 2007-06-21 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Etching method |
| CN101673659A (en) * | 2008-09-10 | 2010-03-17 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting measurement stability of tester tables |
| CN101834114A (en) * | 2009-03-11 | 2010-09-15 | 台湾积体电路制造股份有限公司 | Advanced process control method for gate profile and system for fabricating integrated circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113506759A (en) * | 2021-06-28 | 2021-10-15 | 上海华虹宏力半导体制造有限公司 | Forming method of critical dimension on-line monitoring structure |
| CN113506759B (en) * | 2021-06-28 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | Forming method of key dimension on-line monitoring structure |
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Application publication date: 20161012 |