CN105258795B - A kind of electric capacity trans-impedance amplifier circuit with pure digi-talization output for faint light detection - Google Patents

Abstract

The invention belongs to the field of light detection, in particular to a capacitive transimpedance amplifier circuit with pure digital output for weak light detection, including a signal generation circuit, a CTIA-based light detection circuit and a two-stage inverter, which are connected in sequence, The signal generation circuit includes a sampling signal SELECT circuit and a square wave reset signal RESET circuit. The input terminal of the sampling signal SELECT circuit inputs an initial square wave signal, and the initial square wave signal is sent to an input end of an exclusive OR gate after passing through the first delay unit. The other input terminal of the OR gate is the initial square wave signal, and the pulse signal output by the XOR gate is ANDed with the initial square wave signal to obtain the sampling signal SELECT, and the square wave reset signal RESET is obtained from the initial square wave signal through the three-stage delay unit . Beneficial effects of the present invention: through the novel CTIA structure, pure digital output can be realized when weak light is detected, which is convenient for subsequent circuits to process.

Description

A Capacitive Transimpedance Amplifier with Purely Digital Output for Faint Light Detection circuit

technical field

The invention belongs to the field of light detection, in particular to a capacitive transimpedance amplifier circuit with pure digital output for weak light detection.

Background technique

With the maturity of microelectronics technology, there are more and more ways to acquire sensitive information for integrated circuits and information systems, which can generally be divided into non-invasive attacks and intrusive attacks. Among them, the intrusive attack destroys the chip package by opening the cover, drilling, corrosion and other means, and uses technologies such as photography and microprobes to extract important information such as layout and passwords, and the destruction of the package will expose the chip to light. under. Therefore, in order to enhance the anti-attack capability of chips or systems, weak light detectors are often designed to sense information such as cover opening and drilling, and provide early warning signals for chips or systems.

Considering that opening the cover and drilling may occur under weak light intensity, the designed photodetector must realize an alarm signal when the light intensity is greater than a certain weak light intensity. However, under weak light, the generated photocurrent is small, and the dark current has a great influence on it. Therefore, the structure of capacitive transimpedance amplifier (CTIA) is considered to realize the detection of light intensity.

A common CTIA-based photodetection circuit is shown in Figure 1. It is a reset-integral photodetection circuit composed of an operational amplifier, a feedback capacitor, and a switch. When light is irradiated, since the built-in electric potential field generates a photo-generated voltage inside the PN junction, if the PN junction is connected to the circuit, a phenomenon of photo-generated current will appear. The principle is briefly described as follows: when the RESET signal is high, the switch S ₀ is turned on and enters the reset mode, and the capacitor C ₀ is reset. At this time, the SELECT is low, the switch S ₁ is turned off, and the previous integration period is saved on C ₁ When the RESET signal is low, the switch S ₀ is disconnected, the SELECT signal is high, the switch S ₀ is closed, and enters the integral mode, and the voltage on C ₁ continues to rise until the next reset cycle begins. Common based on The output waveform of the photodetection circuit of CTIA is shown in Fig. 2 . In order to convert the waveform into a high-low level signal, two _- stage inverters are usually added behind the switch S1 as shown in Figure 3. The light intensity is reflected in the duty cycle of the PWM signal. The larger the duty cycle, the greater the light intensity. stronger. The output of this structure is a square wave with a duty ratio of 50% at the critical light intensity, and the output is low level when the light intensity is below the critical light intensity. The output waveform is shown in Fig. 4 .

Compared with the CTIA-based light detection circuit, the circuit structure after adding two-stage inverter has the advantage that the output signal is digital PWM. However, since the purpose of this circuit is to detect weak light, in order to facilitate the processing of the alarm signal by the subsequent circuit, the ideal output alarm signal is a pure digital output, while the PWM signal needs to use a counter to convert the duty ratio information into a high level or Low-level signals, while doing so increases the complexity of the system on the one hand, and increases the power consumption of the system on the other hand. Therefore, there is a need for a new CTIA structure with purely digital output for weak light detection.

Contents of the invention

To solve the above problems, the present invention provides a capacitive transimpedance amplifier circuit with pure digital output for weak light detection.

Technical scheme of the present invention: a capacitive transimpedance amplifier circuit with pure digital output for weak light detection, characterized in that it includes a signal generation circuit, a CTIA-based light detection circuit and a two-stage inverter, the signal generation The circuit, the photodetection circuit of the basic CTIA and the two-stage inverter are connected in sequence, and the signal generation circuit includes a SELECT circuit for generating a spike-like sampling signal and a RESET circuit for a square-wave reset signal.

The input terminal of the sampling signal SELECT circuit inputs an initial square wave signal, and the initial square wave signal is sent to an input terminal of an XOR gate after passing through a first-stage delay sheet, and the other input terminal of the XOR gate is The initial square wave signal, the output of the XOR gate is a pulse signal, the frequency of the pulse signal is twice that of the initial square wave signal, and the pulse width of the pulse signal is determined by the first delay unit Described pulse signal and described initial square wave signal do and operation again and obtain sampling signal SELECT, and described sampling signal SELECT has the same frequency with described initial square wave signal, described sampling signal SELECT and described initial square wave signal The rising edges arrive at the same time.

The input terminal of the square wave reset signal RESET circuit inputs the initial square wave signal, and the initial square wave signal generates a square wave reset signal RESET signal through the first delay unit, the second delay unit and the third delay unit, The time difference between the rising edge of the square wave reset signal RESET and the falling edge of the sampling signal SELECT is the delay caused by the second delay unit and the third delay unit.

The first delay unit, the second delay unit and the third delay unit are the same unit or different units. Beneficial effects of the present invention: through the novel CTIA structure, pure digital output can be realized when weak light is detected, which is convenient for subsequent circuits to process.

Description of drawings

Figure 1 is a schematic diagram of the structure of a common CTIA-based photodetection circuit.

Figure 2 is the output waveform of Figure 1.

FIG. 3 is a schematic structural diagram of a CTIA structure with two stages of inverters.

FIG. 4 is the output waveform of FIG. 3 .

Fig. 5 is a structural schematic diagram of the circuit of the present invention.

Fig. 6 is a timing diagram of the present invention under strong light.

Fig. 7 is a timing diagram of the present invention under weak light.

Fig. 8 is a timing diagram of the present invention in the absence of light.

FIG. 9 is a schematic structural diagram of the signal generating circuit of the present invention.

FIG. 10 is a schematic structural diagram of the delay unit in FIG. 9 .

detailed description

A specific embodiment of the present invention will be described below in conjunction with accompanying drawing 1 .

The invention relates to a capacitive transimpedance amplifier circuit with pure digital output for weak light detection, which is characterized in that it includes a signal generation circuit, a CTIA-based light detection circuit and a two-stage inverter, a signal generation circuit, and a basic CTIA The light detection circuit and the two-stage inverters are connected in sequence.

The signal generating circuit includes a sampling signal SELECT circuit and a square wave reset signal RESET circuit for generating sharp pulses. The input terminal of the sampling signal SELECT circuit inputs the initial square wave signal, and the initial square wave signal is sent to one input terminal of the XOR gate after passing through the first stage of delay, and the other input terminal of the XOR gate is the initial square wave signal. The output of the OR gate is a pulse signal, the frequency of the pulse signal is twice that of the initial square wave signal, and the pulse width of the pulse signal is determined by the first delay unit; the pulse signal is ANDed with the initial square wave signal to obtain the sampling signal SELECT, and the sampling The signal SELECT has the same frequency as the original square wave signal, and the sampling signal SELECT arrives at the same time as the rising edge of the original square wave signal.

The square wave reset signal RESET circuit input input the initial square wave signal, the initial square wave signal passes through the first delay unit, the second delay unit and the third delay unit to generate a square wave reset signal RESET signal, the square wave reset signal RESET The time difference between the rising edge and the falling edge of the sampling signal SELECT is the delay caused by the second delay unit and the third delay unit. The first delay unit, the second delay unit and the third delay unit are the same unit or different units.

Specifically, Fig. 5 is a structural schematic diagram of the circuit of the present invention, a capacitive transimpedance amplifier circuit with a pure digital output for weak light detection, including a signal generation circuit, a CTIA-based light detection circuit and a two-stage inverter, and the signal generation The circuit is used to generate a sharp pulse sampling signal SELECT circuit and a delayed square wave reset signal RESET circuit. The flipping voltage of the first-stage inverter is V _TH .

Fig. 6 is a timing diagram of the present invention under strong light, Fig. 7 is a timing diagram of the present invention under weak light, and Fig. 8 is a timing diagram of the present invention under no light. At the time T1, the reset signal RESET becomes high, the switch _S0 is closed, the voltage across the capacitor _C0 is reset, both are V _REF , at this time _S1 is in the disconnected state, and _{C1 maintains} the voltage value at the previous moment, so _The output value V _OUT will remain unchanged during the reset phase; at T ₂ time, the reset signal RESET changes from high level to low level, the reset switch S ₀ is turned off, and enters the integration phase. The photocurrent generated by the PN junction will be integrated through C ₀ , causing the output voltage V _C0 of A ₁ to rise. At this time, because the switch S ₁ is disconnected, the voltage V _C1 on C ₁ still maintains the original value; at T ₃ At this moment, the sampling signal SELECT becomes high level, the switch S ₁ is closed, and the charges of the capacitors C ₀ and C ₁ are redistributed, so that the instantaneous V _C0 and V _C1 are equal and equal to a value between the two; _At T4 moment, the sampling signal SELECT becomes low, the switch S1 is turned off, since the reset signal RESET is still low, the photocurrent continues to charge _C0 , so V _C0 continues to rise, while V _{C1 stops} rising and remains at _T4 moment The value of is unchanged. _At time T5, the reset signal RESET becomes high, V _C0 becomes V _REF again, and V _C1 remains. If the photogenerated current is large enough, V _C1 will be greater than the threshold voltage V _TH of A ₂ before T ₄ , making the output V _OUT a high level and maintaining the whole cycle. The structure follows I*T/2=Q=C*U, where I is the size of the photocurrent generated by the photodiode, which is determined by the light intensity and the area of the diode, and T/2 is the integration time, that is, the half cycle , Q is the change of the charge at both ends of the capacitor, C is the capacitance of the capacitor C ₀ , and U is the change of the voltage difference between the two ends of the capacitor C ₀ . When I in the formula is the photocurrent generated by the threshold light intensity, U is V _TH -V _REF . The size of C is closely related to the sensitivity of the photodetector. When U and T are constant, the smaller C is, the smaller I is, and the more sensitive the detector is. The size of the photocurrent generated by the PN junction can be adjusted by adjusting the size of the integrating capacitor, the area of the PN junction, V _TH -V _REF and the period of the RESET square wave signal, so that the structure can detect weak critical light.

As shown in Figure 9, the structural schematic diagram of the signal generating circuit of the present invention, the sampling signal SELECT input is an initial square wave signal, and the initial square wave signal is sent to one input end of the XOR gate after passing through the first stage delay unit, and the other side of the XOR gate The input end is the initial square wave signal, and the output of the XOR gate is a pulse signal whose frequency is twice the frequency of the initial square wave signal, and the pulse width is determined by the delay unit. The pulse signal and the initial square wave signal are ANDed, and the sampling signal SELECT with the same frequency as the initial square wave signal is obtained, and the sampling signal SELECT arrives at the same time as the rising edge of the initial square wave signal; the square wave reset signal RESET circuit is the initial The square wave signal passes through the first delay unit, the second delay unit, and the third delay unit to generate a square wave reset signal RESET, and the time difference between the rising edge of the square wave reset signal RESET and the falling edge of the sampling signal SELECT Delay caused by two delay units. As shown in the delay unit in Figure 10, the main delay elements are R and C, and the delay time τ≈R*C. By setting the values of R and C reasonably, a certain delay time can be obtained. The three-level delay units shown in Figure 9 are the same, but in actual situations, the R and C values in the three-level delay units can be different, and by reasonably adjusting the R and C values of the delay units at all levels, it can be obtained The preset spike width T ₄ -T ₃ and the time interval T ₅ -T ₄ between the falling edge of the spike pulse and the rising edge of the RESET signal.

In a specific working process, a CLK clock signal and a V _REF reference voltage need to be provided from the outside. When actually testing the weak critical light, the threshold light intensity of the weak critical light can be adjusted by adjusting the frequency of the CLK signal and the size of V _REF . The frequency of CLK should be selected properly, if it is too large, it will increase the power consumption of the system, if it is too small, it will increase the response time of the photodetector. When testing after setting the critical threshold light intensity, if the light intensity exceeds the threshold light intensity, it will output a high level, and if the light intensity is less than the threshold light intensity, it will output a low level.

An example of the present invention has been described in detail above, but the content described is only a preferred embodiment of the present invention and cannot be considered as limiting the implementation scope of the present invention. All equivalent changes and improvements made according to the application scope of the present invention shall still belong to the scope covered by the patent of the present invention.

Claims (2)

1. A capacitive transimpedance amplifier circuit with pure digital output for faint light detection, characterized in that it comprises a signal generation circuit, a CTIA-based light detection circuit and a two-stage inverter, the signal generation circuit, the The CTIA-based photodetection circuit is sequentially connected to the two-stage inverter, and the signal generation circuit includes a sampling signal SELECT circuit and a square wave reset signal RESET circuit for generating sharp pulses; The input terminal of the sampling signal SELECT circuit inputs an initial square wave signal, and the initial square wave signal is sent to an input terminal of an exclusive OR gate after passing through the first delay unit, and the other input terminal of the exclusive OR gate is the input terminal of the exclusive OR gate. The initial square wave signal, the XOR gate output is a pulse signal, the frequency of the pulse signal is twice that of the initial square wave signal, and the pulse width of the pulse signal is determined by the first delay unit; The pulse signal is then ANDed with the initial square wave signal to obtain a sampling signal SELECT, the sampling signal SELECT has the same frequency as the initial square wave signal, and the rising of the sampling signal SELECT and the initial square wave signal arrive at the same time; The input terminal of the square wave reset signal RESET circuit inputs the initial square wave signal, and the initial square wave signal generates a square wave reset signal RESET signal through the first delay unit, the second delay unit and the third delay unit, The time difference between the rising edge of the square wave reset signal RESET and the falling edge of the sampling signal SELECT is the delay caused by the second delay unit and the third delay unit. 2. A capacitive transimpedance amplifier circuit with a pure digital output for weak light detection according to claim 1, characterized in that the first delay unit, the second delay unit and the first delay unit The three delay units are the same unit or different units.