CN204666814U - Integrating circuit and proximity test chip - Google Patents
Integrating circuit and proximity test chip Download PDFInfo
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- CN204666814U CN204666814U CN201520385063.3U CN201520385063U CN204666814U CN 204666814 U CN204666814 U CN 204666814U CN 201520385063 U CN201520385063 U CN 201520385063U CN 204666814 U CN204666814 U CN 204666814U
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Abstract
Disclose a kind of integrating circuit, first switch of described integrating circuit is to the closed or disconnection under control of the control signal of the 5th switch, make described integrating circuit carry out first time integration to input current in the flrst mode, under the second mode second time integration carried out to described input current and deduct the result of first time integration.Also disclose a kind of proximity test chip and comprise light emitting diode, photodiode, described integrating circuit, analog to digital converter and control circuit, described proximity test chip can eliminate the interference of surround lighting effectively, improve accuracy of detection, be not only applicable to the situation that object distance is nearer, be also applicable to the situation that object distance is far away.
Description
Technical field
The utility model relates to analogue signal circuit field, is specifically related to a kind of integrating circuit and a kind of proximity test chip.
Background technology
Proximity test chip can detect the existence of an object, and the distance of this proximity test chip of this object distance.The application of proximity test chip is very extensive, and the staff as speed detection, automatic faucet detects, the Auto-counting of object or inspection on travelling belt, and the paper rim detection etc. of printer.
The proximity test chip of photo-electric, when detecting target object, is first launched to target object and is detected light (being generally infrared light), then detected the intensity of the detection light that target object is reflected back by photodiode.Photodiode produces photocurrent after illumination is penetrated, and the distance of the intensity of photocurrent and target object distance proximity test chip is inversely proportional to, and target object is nearer, and photocurrent is stronger, and target object is far away, and photocurrent is more weak.
But in actual applications, be irradiated to and photodiode is not only the detection light that target object reflects, also comprise surround lighting (as sunlight, light etc.).The serious interference of surround lighting affects the precision of proximity test chip and the judgement to target object distance.
Utility model content
In view of this, the utility model proposes a kind of integrating circuit and the proximity test chip based on described integrating circuit, effectively can eliminate the interference components of surround lighting, improve the precision of proximity test chip, be not only applicable to the situation of target object close together, be also applicable to the situation that object distance is far away.
First aspect, the utility model proposes a kind of integrating circuit, have input end and output terminal, described integrating circuit comprises: the first operational amplifier, there is in-phase input end, inverting input and output terminal, the in-phase input end ground connection of described first operational amplifier; Second operational amplifier, has in-phase input end, inverting input and output terminal, the in-phase input end ground connection of described second operational amplifier, and the output terminal of described second operational amplifier is the output terminal of described integrating circuit; First switch, between the inverting input being connected to described first operational amplifier and the input end of described integrating circuit; 5th switch, between the inverting input being connected to described second operational amplifier and the input end of described integrating circuit; 3rd switch, between the output terminal being connected to described first operational amplifier and intermediate ends; First electric capacity, between the inverting input being connected to described first operational amplifier and described intermediate ends; 4th switch, between the inverting input being connected to described second operational amplifier and described intermediate ends; Second switch, is connected between the inverting input of described first operational amplifier and the output terminal of described first operational amplifier; Second electric capacity, is connected between the inverting input of described second operational amplifier and the output terminal of described second operational amplifier; Described first switch is to the closed or disconnection under control of the control signal of the 5th switch, make described integrating circuit carry out first time integration at first mode to input current, the second pattern to described input current carry out second time integration and deduct first time integration result.
Preferably, the output voltage of described integrating circuit after a described first mode and the second pattern is:
wherein, t0 and t1 is respectively start time and the finish time of described first mode, t1 and t2 is respectively start time and the finish time of described second pattern, and C2 is the capacitance of described second electric capacity, and i (t) is described input current.
Preferably, described integrating circuit also comprises: the 6th switch, is connected between the inverting input of described first operational amplifier and the output terminal of described first operational amplifier; 7th switch, between the output terminal being connected to described first operational amplifier and described intermediate ends; 8th switch, is connected between the inverting input of described second operational amplifier and the output terminal of described second operational amplifier; Described 6th switch, the 7th switch and the 8th switch are closed under four-mode, and disconnect under described first mode, the second pattern, the 3rd pattern, described integrating circuit is in described four-mode before the sample phase of each sense cycle starts.
Second aspect, the utility model proposes a kind of proximity test chip, for detecting the distance of target object, comprising: photodiode; Light emitting diode, for launching detection light; Integrating circuit, described integrating circuit comprises: the first operational amplifier, has in-phase input end, inverting input and output terminal, the in-phase input end ground connection of described first operational amplifier; Second operational amplifier, has in-phase input end, inverting input and output terminal, the in-phase input end ground connection of described second operational amplifier, and the output terminal of described second operational amplifier is the output terminal of described integrating circuit; First switch, between the inverting input being connected to described first operational amplifier and the input end of described integrating circuit; 5th switch, between the inverting input being connected to described second operational amplifier and the input end of described integrating circuit; 3rd switch, between the output terminal being connected to described first operational amplifier and intermediate ends; First electric capacity, between the inverting input being connected to described first operational amplifier and described intermediate ends; 4th switch, between the inverting input being connected to described second operational amplifier and described intermediate ends; Second switch, is connected between the inverting input of described first operational amplifier and the output terminal of described first operational amplifier; Second electric capacity, is connected between the inverting input of described second operational amplifier and the output terminal of described second operational amplifier; Described first switch is to the closed or disconnection under control of the control signal of the 5th switch, make described integrating circuit carry out first time integration at first mode to input current, the second pattern to described input current carry out second time integration and deduct first time integration result; Analog to digital converter, for being converted to digital signal by the output signal of described integrating circuit; Control circuit, for generation of multiple retiming clock signals of described proximity test chip, makes described integrating circuit switch between different mode.
Preferably, described light emitting diode is infrarede emitting diode.
Preferably, described integrating circuit also comprises: the 6th switch, is connected between the inverting input of described first operational amplifier and the output terminal of described first operational amplifier; 7th switch, between the output terminal being connected to described first operational amplifier and described intermediate ends; 8th switch, is connected between the inverting input of described second operational amplifier and the output terminal of described second operational amplifier; In described first mode and the second pattern, described 6th switch, the 7th switch, the 8th switch disconnect.
Preferably, the output voltage of described integrating circuit after a described first mode and the second pattern is: (i
2* T-i
1* T)/C2, wherein, C2 is the capacitance of described second electric capacity, and the time that described integrating circuit is in described first mode and the second pattern is respectively T, i
1for the photocurrent that described photodiode produces when described first mode, i
2for the photocurrent that described photodiode produces when described second pattern.
The utility model proposes a kind of integrating circuit and proximity test chip, effectively can eliminate the interference components of surround lighting, making when object proximity can the distance of judgment object more accurately, the utility model proposes a kind of integrating circuit and proximity test chip also has the simple feature of line construction, be not only applicable to the situation that object distance is nearer, be also applicable to the situation that object distance is far away.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the utility model embodiment, above-mentioned and other objects, features and advantages of the present utility model will be more clear, in the accompanying drawings:
Fig. 1 is the system principle schematic diagram of proximity test chip;
Fig. 2 is the circuit diagram of the integrating circuit of the utility model first embodiment;
Fig. 3 is the circuit diagram of the integrating circuit of the utility model second embodiment;
Fig. 4 a-4b is the sequential chart of the integrating circuit of the utility model second embodiment
Fig. 5 is the structural drawing of the proximity test chip of the utility model the 3rd embodiment; And
Fig. 6 is the working timing figure of the proximity test chip of the utility model the 3rd embodiment.
Embodiment
Based on embodiment, the utility model is described below, but the utility model is not restricted to these embodiments.In hereafter details of the present utility model being described, detailedly describe some specific detail sections.In addition, it should be understood by one skilled in the art that the accompanying drawing provided at this is all for illustrative purposes, and accompanying drawing is not necessarily drawn in proportion.Unless the context clearly requires otherwise, similar words such as " comprising ", " comprising " otherwise in whole instructions and claims should be interpreted as the implication that comprises instead of exclusive or exhaustive implication; That is, be the implication of " including but not limited to ".In description of the present utility model, it is to be appreciated that term " first ", " second " etc. are only for describing object, and instruction or hint relative importance can not be interpreted as.In addition, in description of the present utility model, except as otherwise noted, the implication of " multiple " is two or more.
Fig. 1 is the system principle schematic diagram of proximity test chip.Proximity test chip comprises infrarede emitting diode, photodiode and integrating circuit.Infrarede emitting diode is to object emission infrared light, and photodiode detects the infrared light be reflected by the object, and in actual applications, photodiode also can detect the infrared light in surround lighting.Photodiode produces photocurrent under the irradiation of reflected light and surround lighting, and flow into integrating circuit, integrating circuit carries out integration to photocurrent, and the size of integrating circuit Output rusults is inversely proportional to the distance of object distance proximity test chip.
Fig. 2 is the circuit diagram of the integrating circuit of the utility model first embodiment, and the integrating circuit of the first embodiment comprises: first integral module 100, second integral module 200, switch S 1, switch S 2 and switch S 3.Wherein, first integral module 100 comprises: the first operational amplifier Opam1, the first electric capacity C1, switch S 4 and switch S 5; Second integral module 200 comprises: the second operational amplifier Opam2 and the second electric capacity C2.In fig. 2, the output terminal of first integral module 100 is denoted as intermediate ends m.
First operational amplifier Opam1 has in-phase input end, inverting input and output terminal, the in-phase input end ground connection of the first operational amplifier Opam1; Second operational amplifier Opam2 has in-phase input end, inverting input and output terminal, the in-phase input end ground connection of the second operational amplifier Opam2, and the output terminal of the second operational amplifier Opam2 is as the output terminal of integrating circuit.
Between the inverting input that switch S 1 is connected to the first operational amplifier Opam1 and the input end of integrating circuit; Between the inverting input that switch S 2 is connected to the second operational amplifier Opam2 and the input end of integrating circuit; Between the output terminal that switch S 5 is connected to the first operational amplifier Opam1 and intermediate ends m; Between the inverting input that switch S 3 is connected to the second operational amplifier Opam1 and intermediate ends m; Between the inverting input that switch S 4 is connected to the first operational amplifier Opam1 and output terminal.
Between the inverting input that first electric capacity C1 is connected to the first operational amplifier Opam1 and intermediate ends m; Second electric capacity C2, between the inverting input being connected to the second operational amplifier Opam2 and output terminal.
The electric capacity related in all embodiments of the utility model can be thermometal electric capacity (MIM capacitor) or two polycrystalline electric capacity (PIP capacitor), switch can be single MOS switch also can be cmos switch, operational amplifier is any common operational amplifier meeting job requirement, as folding Operational Amplifier or telescopic operational amplifier etc.
The control method of the integrating circuit of the first embodiment is below described.Be first mode during t0 to t1, be the second pattern during t1 to t2.
In the flrst mode, switch S 1 and switch S 5 close, and rest switch disconnects, and the first operational amplifier Opam1 is to current i (t) integration flowing into integrating circuit input end, and in the t1 moment, the electric charge on the first electric capacity C1 is:
Under the second mode, switch S 4, switch S 3 and switch S 2 closes, and rest switch disconnects, and the second operational amplifier Opam2 is to current i (t) integration flowing into integrating circuit input end, first electric capacity C1 is reset simultaneously, and the Charger transfer on the first electric capacity C1 is on the second electric capacity C2.In the t2 moment, the electric charge on the first electric capacity C1 is that on the zero, second electric capacity C2, electric charge is:
The voltage of integrating circuit output terminal is:
Fig. 3 is the circuit diagram of the integrating circuit of the second embodiment of the present utility model, and the integrating circuit of the utility model second embodiment comprises: first integral module 100, second integral module 200, switch S 1, switch S 3 and switch S 2.Wherein, first integral module 100 comprises the first operational amplifier Opam1, the first electric capacity C1, switch S 4, switch S 5, switch S 6 and switch S 7; Second integral module 200 comprises: the second operational amplifier Opam2, the second electric capacity C2 and switch S 8.In figure 3, the output terminal of first integral module 100 is denoted as intermediate ends m.
First operational amplifier Opam1 has in-phase input end, inverting input and output terminal, the in-phase input end ground connection of the first operational amplifier Opam1; Second operational amplifier Opam2 has in-phase input end, inverting input and output terminal, the in-phase input end ground connection of the second operational amplifier Opam2, and the output terminal of the second operational amplifier Opam2 is as the output terminal of integrating circuit.
Between the inverting input that switch S 1 is connected to the first operational amplifier Opam1 and the input end of integrating circuit; Between the inverting input that switch S 2 is connected to the second operational amplifier Opam2 and the input end of integrating circuit; Between the output terminal that switch S 5 is connected to the first operational amplifier Opam1 and intermediate ends m; Between the inverting input that switch S 3 is connected to the second operational amplifier Opam1 and intermediate ends m; Between the inverting input that switch S 4 is connected to the first operational amplifier Opam1 and output terminal.
Between the inverting input that first electric capacity C1 is connected to the first operational amplifier Opam1 and intermediate ends m; Second electric capacity C2, between the inverting input being connected to the second operational amplifier Opam2 and output terminal.
Switch S 6 is connected between the inverting input of the first operational amplifier Opam1 and the output terminal of the first operational amplifier Opam1; Between the output terminal that switch S 7 is connected to the first operational amplifier Opam1 and intermediate ends m; Switch S 8 is connected between the inverting input of the second operational amplifier Opam2 and the output terminal of the second operational amplifier Opam2.
At work, switch S 1 to switch S 8 is closed or disconnection under the control of retiming clock signal ph1-ph3, and wherein, switch S 1 and switch S 5 are subject to the control action simultaneously of retiming clock signal ph1; Switch S 4, switch S 3 and switch S 2 are subject to the control action simultaneously of retiming clock signal ph2; Switch S 6 to switch S 8 is subject to the control action simultaneously of retiming clock signal ph3.
Fig. 4 a-4b is the sequential chart of the integrating circuit of the utility model second embodiment, and as shown in fig. 4 a, the retiming clock signal ph1-ph3 of integrating circuit as shown in Figure 4 b for the oscillogram of input current i (t) of integrating circuit.During t0 to t1, integrating circuit is in four-mode, it is sample phase from t1 to t5, during t5 to t6, integrating circuit is in the 3rd pattern, wherein, during t1 to t2, integrating circuit is in first mode, is switched to the second pattern at t2 moment integrating circuit, is switched to first mode at t3 moment integrating circuit, t4 moment integrating circuit is switched to the second pattern, and t2-t1=t3-t2=t4-t3=t5-t4=Δ t.The control method of the integrating circuit of the second embodiment is described in detail below with reference to Fig. 3 and Fig. 4 a-4b.
During t0 to t1, ph3 is high level, ph1 and ph2 is low level, and switch S 6, switch S 7 and switch S 8 closes, and the first to the 5th switch disconnects.Electric charge on first electric capacity C1 and the second electric capacity C2 resets, and integrating circuit resets.
During t1 to t2, ph1 is high level, ph3 and ph2 is low level, switch S 1 and switch S 5 close, and other switch disconnects, and the first operational amplifier Opam1 is to current i (t) integration flowing into integrating circuit input end, in the t2 moment, the electric charge on the first electric capacity C1 is:
During t2 to t3, ph2 is high level, ph1 and ph3 is low level, switch S 4 switch S 3 and switch S 2 close, other switch disconnects, second operational amplifier Opam2 is to current i (t) integration flowing into integrating circuit input end, and the first electric capacity C1 is reset simultaneously, and the Charger transfer on the first electric capacity C1 is on the second electric capacity C2.In the t3 moment, on the second electric capacity C2, electric charge is:
During t3 to t4, ph1 is high level, ph3 and ph2 is low level, switch S 1 and switch S 5 close, other switch disconnects, and the first operational amplifier Opam1 is to current i (t) integration flowing into integrating circuit input end, and the electric charge on the second electric capacity C2 remains unchanged, in the t4 moment, on the first electric capacity C1, electric charge is:
During t4 to t5, ph2 is high level, ph1 and ph3 is low level, switch S 4 switch S 3 and switch S 2 close, other switch disconnects, second operational amplifier Opam2 is to current i (t) integration flowing into integrating circuit input end, and the first electric capacity C1 is reset simultaneously, and the Charger transfer on the first electric capacity C1 is on the second electric capacity C2.In the t5 moment, on the second electric capacity C2, electric charge is:
During t5 to t6, ph1, ph2 and ph3 are low level, and all switches disconnect, and the voltage of integrating circuit output terminal remains unchanged:
Fig. 5 is the structural drawing of the proximity test chip of the 3rd embodiment of the present utility model.The proximity test chip of the utility model the 3rd embodiment comprises: the integrating circuit in infrared LED, LED driving, biasing circuit, control circuit, the second embodiment, analog to digital converter (Analog-Digital Converter, ADC), I
2c data-interface, register and photodiode.
LED drives for generation of the stable drive current I flowing through infrared LED
lED, LED drives and opens or closedown under the control of the second retiming clock signal CK2.Photodiode is irradiated to after the part of the infrared light that infrared LED sends is reflected by target object.The negative electrode of photodiode connects the input end of integrating circuit, and photodiode produces photocurrent under Infrared irradiation.The infrared light be irradiated on photodiode not only comprises the infrared light also comprised by the infrared light that target object reflects in surround lighting (as sunlight, light etc.), infrared light in surround lighting is stray light, affect the precision of proximity test chip, disturb the judgement to object distance.
Biasing circuit, for maintaining each end of the transistor in chip in working point.Package casing, for laying, fixing, seal, protect IC, package casing has transparent window above photodiode and light emitting diode.
The photocurrent integration that integrating circuit produces photodiode also converts voltage signal to, and the time of the first mode of integrating circuit equals the time of the second pattern, and the first to the 8th switch of integrating circuit is closed or disconnect under the control of multiple retiming clock signal.The voltage signal that analog to digital converter is used for integrating circuit exports is converted to digital signal and stored in register.Outside host computer passes through I
2c data-interface is from digital signal described in register read.
Control circuit, for generation of multiple retiming clock signals of the proximity test chip of the present embodiment, comprises reset timing clock signal RST, the first retiming clock signal CK1 and the second retiming clock signal CK2.In integrating circuit, switch S 1 and switch S 5 be closed or disconnection under the control of the first retiming clock signal CK1; Switch S 4, switch S 3 and switch S 2 be closed or disconnection under the control of the second retiming clock signal CK2; Switch S 6, switch S 7 and switch S 8 be closed or disconnection under the control of reset timing clock signal RST.
By pre-setting the switching times of sample phase between first mode and the second pattern of integrating circuit, proximity test chip can be made to be adapted to different target object distances.When the close together of target object, the infrared light reflected by target object is stronger, and charging rate is very fast, and the switching times between first mode and the second pattern can be little, even only needs to switch once; When target object distant, the infrared light reflected by target object is more weak, and charging rate is comparatively slow, at this moment needs switching between first mode and the second pattern repeatedly.If need switching between first mode and the second pattern N time in sample phase, wherein, N is odd number, the N of control circuit reading pre-stored from register, produces corresponding reset timing clock signal RST, the first retiming clock signal CK1 and the second retiming clock signal CK2 according to the value of N.
Fig. 6 is the sequential chart of the proximity test chip of the 3rd embodiment of the present utility model.The process of a sense cycle of the proximity test chip of the 3rd embodiment is described below in conjunction with Fig. 5 and Fig. 6.A sense cycle of the proximity test chip of the present embodiment comprises reseting stage, sample phase and maintenance stage, wherein, in sample phase, integrating circuit switches three times between the first mode and the second mode, and the time that integrating circuit is in first mode equals the time that integrating circuit is in the second pattern, is T at every turn at every turn.
It is reseting stage from t00 to t01, reset timing clock signal RST is high level, and the first retiming clock signal CK1 and the second retiming clock signal CK2 is low level, and switch S 1 to switch S 2 disconnects, switch S 6 to switch S 8 closes, and the electric charge at the first electric capacity C1, the second electric capacity C2 two ends resets.
Be first first mode, wherein t02=t01+T of sample phase from t01 to t02.Reset timing clock signal RST and the second retiming clock signal CK2 is low level, and the first retiming clock signal CK1 is high level, and switch S 1 and switch S 5 close, and rest switch disconnects, and infrared LED is closed, and does not launch infrared light.The photocurrent i1 flowing into integrating circuit input end is the photocurrent i that the interference Infrared irradiation photodiode in surround lighting produces
surround lighting.In the t02 moment, the electric charge that the first electric capacity C1 stores:
Q1=i
surround lighting* T.
Be first the second pattern, wherein t03=t02+T of sample phase from t02 to t03.Reset timing clock signal RST and the first retiming clock signal CK1 is low level, and the second retiming clock signal CK2 is high level, and switch S 4, switch S 3 and switch S 2 closes, and rest switch disconnects, and infrared LED is opened, and the drive current flowing through infrared LED is I
pEAK.The infrared light that infrared LED is launched is received by photodiode after target object reflection.The photocurrent i2 that now photodiode produces comprises the photocurrent i that surround lighting produces
surround lightingand target object reflects the photocurrent i of the infrared light generation come
reflected light.Photocurrent i2 charges to the second electric capacity C2, and meanwhile, the electric charge on the first electric capacity C1 is also transferred on the second electric capacity C2, and in the t03 moment, the electric charge on the first electric capacity C1 resets, and the electric charge that the second electric capacity C2 stores is:
Q2=(i
surround lighting+ i
reflected light) * T-Q1=i reflected light * T.
The first electric capacity C1 electric charge transferred on the second electric capacity C2 just in time counteracts the electric charge that the surround lighting composition in photocurrent i2 produces the second electric capacity C2 charging, and in the t03 moment, the output voltage of integrating circuit is:
Be second first mode, wherein t04=t03+T of sample phase during t03 to t04.Reset timing clock signal RST and the second retiming clock signal CK2 is low level, and the first retiming clock signal CK1 is high level, and switch S 1 and switch S 5 close, and rest switch disconnects, and infrared LED is closed, and does not launch infrared light.During t03 to t04, the first electric capacity C1 charges, and the electric charge that the second electric capacity C2 stores remains unchanged, and the output voltage of integrating circuit output terminal remains unchanged:
In the t04 moment, the electric charge on the first electric capacity C1 is:
Q1=i
surround lighting* T.
Be second the second pattern, wherein t05=t04+T of sample phase during t04 to t05.Reset timing clock signal RST and the first retiming clock signal CK1 is low level, and the second retiming clock signal CK2 is high level, and switch S 4, switch S 3 and switch S 2 closes, and rest switch disconnects, and infrared LED sends infrared light.Photocurrent second electric capacity C2 charges, and meanwhile, the electric charge on the first electric capacity C1 is also transferred on the second electric capacity C2, and in the t05 moment, the electric charge on the first electric capacity C1 resets, and the electric charge that the second electric capacity C2 stores is:
Q2=2*i
reflected light* T
The output voltage of integrating circuit output terminal is:
It is the maintenance stage during t05 to t06, reset timing clock signal RST, the first retiming clock signal CK1, the second retiming clock signal CK2 are low level, all switches all disconnect, and the electric charge that the second electric capacity C2 stores remains unchanged, and the voltage Vout of integrating circuit output terminal remains unchanged.In the maintenance stage, analog to digital converter converts Vout to digital signal, and stored in register.
The utility model proposes a kind of integrating circuit and proximity test chip, effectively can eliminate the interference components of surround lighting, making when object proximity can the distance of judgment object more accurately, the utility model proposes a kind of integrating circuit and proximity test chip also has the simple feature of line construction, be not only applicable to the situation that object distance is nearer, be also applicable to the situation that object distance is far away.
The foregoing is only preferred embodiment of the present utility model, be not limited to the utility model, to those skilled in the art, the utility model can have various change and change.All do within spirit of the present utility model and principle any amendment, equivalent replacement, improvement etc., all should be included within protection domain of the present utility model.
Claims (7)
1. an integrating circuit, has input end and output terminal, it is characterized in that, described integrating circuit comprises:
First operational amplifier, has in-phase input end, inverting input and output terminal, the in-phase input end ground connection of described first operational amplifier;
Second operational amplifier, has in-phase input end, inverting input and output terminal, the in-phase input end ground connection of described second operational amplifier, and the output terminal of described second operational amplifier is the output terminal of described integrating circuit;
First switch, between the inverting input being connected to described first operational amplifier and the input end of described integrating circuit;
5th switch, between the inverting input being connected to described second operational amplifier and the input end of described integrating circuit;
3rd switch, between the output terminal being connected to described first operational amplifier and intermediate ends;
First electric capacity, between the inverting input being connected to described first operational amplifier and described intermediate ends;
4th switch, between the inverting input being connected to described second operational amplifier and described intermediate ends;
Second switch, is connected between the inverting input of described first operational amplifier and the output terminal of described first operational amplifier;
Second electric capacity, is connected between the inverting input of described second operational amplifier and the output terminal of described second operational amplifier;
Described first switch is to the closed or disconnection under control of the control signal of the 5th switch, make described integrating circuit carry out first time integration at first mode to input current, the second pattern to described input current carry out second time integration and deduct first time integration result.
2. integrating circuit according to claim 1, is characterized in that, wherein, the output voltage of described integrating circuit after a described first mode and the second pattern is:
wherein, t0 and t1 is respectively start time and the finish time of described first mode, t1 and t2 is respectively start time and the finish time of described second pattern, and C2 is the capacitance of described second electric capacity, and i (t) is described input current.
3. integrating circuit according to claim 1, is characterized in that, described integrating circuit also comprises: the 6th switch, is connected between the inverting input of described first operational amplifier and the output terminal of described first operational amplifier;
7th switch, between the output terminal being connected to described first operational amplifier and described intermediate ends;
8th switch, is connected between the inverting input of described second operational amplifier and the output terminal of described second operational amplifier.
4. a proximity test chip, for detecting the distance of target object, is characterized in that, described proximity test chip comprises:
Photodiode;
Light emitting diode, for launching detection light;
Integrating circuit, described integrating circuit comprises: the first operational amplifier, has in-phase input end, inverting input and output terminal, the in-phase input end ground connection of described first operational amplifier; Second operational amplifier, has in-phase input end, inverting input and output terminal, the in-phase input end ground connection of described second operational amplifier, and the output terminal of described second operational amplifier is the output terminal of described integrating circuit; First switch, between the inverting input being connected to described first operational amplifier and the input end of described integrating circuit; 5th switch, between the inverting input being connected to described second operational amplifier and the input end of described integrating circuit; 3rd switch, between the output terminal being connected to described first operational amplifier and intermediate ends; First electric capacity, between the inverting input being connected to described first operational amplifier and described intermediate ends; 4th switch, between the inverting input being connected to described second operational amplifier and described intermediate ends; Second switch, is connected between the inverting input of described first operational amplifier and the output terminal of described first operational amplifier; Second electric capacity, is connected between the inverting input of described second operational amplifier and the output terminal of described second operational amplifier; Described first switch is to the closed or disconnection under control of the control signal of the 5th switch, make described integrating circuit carry out first time integration at first mode to input current, the second pattern to described input current carry out second time integration and deduct first time integration result;
Analog to digital converter, for being converted to digital signal by the output signal of described integrating circuit;
Control circuit, for generation of multiple retiming clock signals of described proximity test chip, makes described integrating circuit switch between different mode.
5. proximity test chip according to claim 4, is characterized in that, described light emitting diode is infrarede emitting diode.
6. proximity test chip according to claim 4, is characterized in that, described integrating circuit also comprises: the 6th switch, is connected between the inverting input of described first operational amplifier and the output terminal of described first operational amplifier;
7th switch, between the output terminal being connected to described first operational amplifier and intermediate ends;
8th switch, is connected between the inverting input of described second operational amplifier and the output terminal of described second operational amplifier;
In described first mode and the second pattern, described 6th switch, the 7th switch, the 8th switch disconnect.
7. proximity test chip according to claim 4, is characterized in that, the output voltage of described integrating circuit after a described first mode and the second pattern is: (i
2* T-i
1* T)/C2, wherein, C2 is the capacitance of described second electric capacity, and the time that described integrating circuit is in described first mode and the second pattern is respectively T, i
1for the photocurrent that described photodiode produces when described first mode, i
2for the photocurrent that described photodiode produces when described second pattern.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109596583A (en) * | 2018-11-23 | 2019-04-09 | 中国科学院苏州生物医学工程技术研究所 | Bioluminescence device for fast detecting |
| CN111465871A (en) * | 2017-12-15 | 2020-07-28 | 齐诺马蒂赛股份有限公司 | System and method for determining distance to an object |
| CN115561826A (en) * | 2022-10-21 | 2023-01-03 | 武汉市聚芯微电子有限责任公司 | Proximity detection circuit and proximity sensor |
| WO2024082599A1 (en) * | 2022-10-21 | 2024-04-25 | 武汉市聚芯微电子有限责任公司 | Proximity detection circuit and proximity sensor |
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2015
- 2015-06-05 CN CN201520385063.3U patent/CN204666814U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111465871A (en) * | 2017-12-15 | 2020-07-28 | 齐诺马蒂赛股份有限公司 | System and method for determining distance to an object |
| CN109596583A (en) * | 2018-11-23 | 2019-04-09 | 中国科学院苏州生物医学工程技术研究所 | Bioluminescence device for fast detecting |
| CN115561826A (en) * | 2022-10-21 | 2023-01-03 | 武汉市聚芯微电子有限责任公司 | Proximity detection circuit and proximity sensor |
| CN115561826B (en) * | 2022-10-21 | 2023-08-11 | 武汉市聚芯微电子有限责任公司 | Proximity detection circuit and proximity sensor |
| WO2024082599A1 (en) * | 2022-10-21 | 2024-04-25 | 武汉市聚芯微电子有限责任公司 | Proximity detection circuit and proximity sensor |
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