CN103487662B - Capacitive detection circuit - Google Patents
Capacitive detection circuit Download PDFInfo
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- CN103487662B CN103487662B CN201310314929.7A CN201310314929A CN103487662B CN 103487662 B CN103487662 B CN 103487662B CN 201310314929 A CN201310314929 A CN 201310314929A CN 103487662 B CN103487662 B CN 103487662B
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Abstract
The present invention relates to testing circuit, disclose a kind of capacitive detection circuit.This capacitive detection circuit, comprises integrating capacitor Ci, electric capacity Cs to be detected, current source A, operational amplifier A 0 and information processing chip, electric capacity Cs to be detected, integrating capacitor Ci is connected with the negative input end of operational amplifier A 0 respectively with one end of current source A, the other end ground connection of electric capacity Cs to be detected and current source A, the other end of integrating capacitor Ci is connected with the output terminal of operational amplifier A 0, the positive input terminal ground connection of operational amplifier A 0, after such connection circuit, a part is shifted by a current source A by the electric charge on electric capacity Cs to be detected, another part electric charge is then transferred on integrating capacitor Ci, the size △ Vout of operational amplifier A 0 output end voltage change in a charge transfer process so just can be reduced under the prerequisite additionally not increasing integrating capacitor Ci area, and then increase the capacitance value range detected, owing to not reducing detection voltage in testing process, also the decline of signal to noise ratio (S/N ratio) can not be caused.
Description
Technical field
The present invention relates to electronic applications, particularly capacitive detection circuit.
Background technology
At present, capacitive touch technology development rapidly, brings convenience to people's life, and first touch control detection Region dividing is some lattice points anyhow intersected by this technology, then by detecting the change of lattice point capacitance, the positional information of the touch point drawn.
If capacitive touch technology is classified according to specific implementation, then comprise electric capacity button, self-induction capacitance plate, Inductance and Capacitance is shielded.Wherein in electric capacity button and self-induction capacitance plate, its testing capacitance size conversion scope is very large, in some little touch circuit boards, self-induction capacitor's capacity only has a few pico farad, and at some large capacitance touch screens, or in large electric capacity button, its self-induction capacitance may reach pico farad up to a hundred.
The Cleaning Principle of traditional detection mode is: when integration starts, at first stage, as shown in Figure 1, and integrating capacitor Ci carries out clearing and resets, and electric capacity Cs to be detected is then charged to reference voltage Vref, and this stage can be referred to as sample phase.At second stage, by switch, the negative input end of Cs upper end with operational amplifier A 0 is connected, as shown in Figure 2.Suppose that operational amplifier is desirable, then, at the end of second stage, opamp input terminal voltage is equal; Now, sampling capacitance Cs two terminal potential is zero, and the electric charge namely on electric capacity Cs to be detected has all been transferred to integrating capacitor Ci, and this stage is called charge transfer phase or integration phase.Collectively Charger transfer cycle or be called integration period in this two stages, in actual use, Charger transfer repeatedly can be carried out as required, namely realize integration, it should be noted that first integration period that the clearing of integrating capacitor Ci only starts at integration occurs.According to principle of charge conservation, after each Charger transfer can be drawn, being changed to of op-amp output voltage:
Wherein Δ Vout is the change size that Charger transfer causes the output voltage of operational amplifier.This voltage swing is detected by analog to digital converter and is sent to digital circuit process, just can judge the capacitance of electric capacity Cs to be detected.
But, in actual applications, for improving antijamming capability, Vref gets height as far as possible, for aspect describes, assuming that the power supply of capacitive detection circuit is 3.3V, Vref is also 3.3V, this is very general in routine application, suppose that electric capacity to be detected is 100 pico farads, integrating capacitor is 20 pico farads, then the output voltage of operational amplifier that each migration period causes is changed to 16.5V, and this has seriously exceeded supply voltage value 3.3V.If go to reduce the output voltage change shifted and cause by the mode increasing integrating capacitor at every turn, the integrating capacitor guarantee of more than 100 pico farads is then needed once to shift the tolerance range that can not exceed operational amplifier, but the electric capacity realizing 100 pico farads needs very large area in integrated circuits.Even the area of 20 pf capacitance value is also considerable, if go to solve output voltage change problem too greatly by the mode increasing integrating capacitor, then during this circuit application situation that electric capacity Cs to be detected is very little in outside, each transfer causes the change of amplifier output voltage will be very small, can reduce the signal to noise ratio (S/N ratio) that amplifier exports like this.
As can be seen here, adopt traditional capacitance measurement technique, the scope of capacitance to be detected will be limited in the scope of about 3 pico farad ~ 30 pico farads.
Summary of the invention
The object of the present invention is to provide a kind of capacitive detection circuit, by additionally adding current source in circuit, this capacitive detection circuit also can be detected it when electric capacity to be detected is very large.
For solving the problems of the technologies described above, the invention provides a kind of capacitive detection circuit, comprising integrating capacitor, electric capacity to be detected, current source, operational amplifier and information processing chip;
One end of described electric capacity to be detected is connected with the negative input end of described operational amplifier, other end ground connection;
One end of described integrating capacitor is connected with the negative input end of described operational amplifier, and the other end is connected with the output terminal of described operational amplifier;
One end of described current source is connected with the negative input end of described operational amplifier, other end ground connection;
The positive input terminal ground connection of described operational amplifier;
One end of described signal processing chip is connected with the output terminal of described operational amplifier, and the other end exports the capacitance that described capacitive detection circuit detects.
Compared with prior art, capacitive detection circuit in the present invention adds a current source, this current source can be drawn or fill with the Partial charge sent on Cs, another part electric charge on Cs is then transferred on Ci, so just can reduce △ Vout under the prerequisite additionally not increasing integrating capacitor Ci area, and then increase the capacitance value range detected.And in testing process, do not reduce detection voltage, therefore can not cause the decline of signal to noise ratio (S/N ratio) yet.
Preferably, current source in the present invention rationally can arrange size of current and the service time of this current source in charge transfer process according to applicable cases, make △ Vout remain within the tolerance range of operational amplifier A 0, detect large-scale capacitance exactly further.
In addition, the present invention, according to charge-transfer theory, utilizes the capacitance of electric capacity to be detected described in following formulae discovery:
Vref*Cs＝ΔVout*Ci+I*T
Wherein, described Δ Vout is the size of the output end voltage change of described operational amplifier after a Charger transfer, described Vref is the reference voltage that described electric capacity to be detected is charged in sample phase, described Cs is the capacitance of described electric capacity to be detected, described Ci is the capacitance of described integrating capacitor, described I is the current value of described current source, and described T is the time that described current source is opened.
Because Δ Vout, Vref, Ci, I, T in above-mentioned formula are known number, the capacitance of electric capacity Cs to be detected therefore can be calculated very easily.
Further, the capacitive detection circuit in the present invention has two kinds of mode of operations, and a kind of is that Cs fills with the reverse integral pattern of power transmission lotus to Ci, and a kind of is the forward integral mode of Cs from Ci draw charge, and the scope of application is more extensive.
In addition, signal processing chip in the present invention in capacitive detection circuit also comprises analog to digital converter and digital circuit processor, the output end voltage of operational amplifier is carried out analog to digital conversion by this analog to digital converter, obtain the digital signal of this output end voltage, and this digital signal is flowed to digital circuit processor, this digital circuit processor according to formula Vref*Cs=Δ Vout*Ci+I*T, calculates the capacitance of electric capacity to be detected again.
Accompanying drawing explanation
Fig. 1 is the sample phase schematic diagram according to capacitive detection circuit in prior art;
Fig. 2 is the charge transfer phase schematic diagram according to capacitive detection circuit in prior art;
Fig. 3 is the sample phase schematic diagram of the capacitive detection circuit according to first embodiment of the invention;
Fig. 4 is the capacitive detection circuit schematic diagram according to first embodiment of the invention;
Fig. 5 is according to the forward integral mode capacitive detection circuit schematic diagram in second embodiment of the invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the embodiments of the present invention are explained in detail.But, persons of ordinary skill in the art may appreciate that in each embodiment of the present invention, proposing many ins and outs to make reader understand the application better.But, even without these ins and outs with based on the many variations of following embodiment and amendment, each claim of the application technical scheme required for protection also can be realized.
First embodiment of the present invention relates to a kind of capacitive detection circuit.Specifically as shown in Figure 3 and Figure 4.
This capacitive detection circuit comprises integrating capacitor Ci, electric capacity Cs to be detected, current source A, operational amplifier A 0 and information processing chip;
One end of electric capacity Cs to be detected is connected with the negative input end of operational amplifier A 0, other end ground connection;
One end of integrating capacitor Ci is connected with the negative input end of operational amplifier A 0, and the other end is connected with the output terminal of operational amplifier A 0;
One end of current source A is connected with the negative input end of operational amplifier A 0, other end ground connection;
The positive input terminal ground connection of operational amplifier A 0;
One end of signal processing chip is connected with the output terminal of operational amplifier A 0, the capacitance that other end output capacitance testing circuit detects.
In present embodiment, the testing process of electric capacity divides two stages specifically:
First stage, as shown in Figure 3, integrating capacitor Ci carries out clearing and resets, and electric capacity Cs to be detected is charged to reference voltage Vref, and this is consistent with traditional method;
Second stage, as shown in Figure 4, by switch by electric capacity Cs to be detected, integrating capacitor Ci is connected with the negative input end of operational amplifier A 0 respectively with one end of current source A, by the other end ground connection of electric capacity Cs to be detected and current source A, the output terminal of the other end of integrating capacitor Ci with operational amplifier A 0 is connected, and by the positive input terminal ground connection of operational amplifier A 0, after such connection circuit, a part is shifted by a current source A by the electric charge on electric capacity Cs to be detected, another part electric charge is then transferred on integrating capacitor Ci, this stage is called charge transfer phase or integration phase.
Suppose that operational amplifier A 0 is desirable, then at the end of second stage, operational amplifier A 0 input terminal voltage is equal, and now, electric capacity Cs two terminal potential to be detected is zero, and the electric charge namely on electric capacity Cs to be detected is all transferred on integrating capacitor Ci and current source A;
In above-mentioned subordinate phase, two-part Charger transfer causes the change of operational amplifier A 0 output end voltage Vout, export after operational amplifier A 0 is amplified, the size delta Vout that in a charge transfer process, operational amplifier A 0 output end voltage changes is received by the analog to digital converter in information processing chip, the digital circuit processor process in information processing chip is sent to after analog to digital conversion, this digital circuit processor, again according to charge-transfer theory, is obtained the capacitance of electric capacity Cs to be tested easily by expression formula Vref*Cs=Δ Vout*Ci+I*T.
Above-mentioned first stage and subordinate phase collectively Charger transfer cycle or be called integration period, in actual use, Charger transfer repeatedly can be carried out as required, namely integration is realized, it should be noted that first integration period that the clearing of integrating capacitor Ci only starts at integration occurs.
Because the capacitive detection circuit in the present embodiment adds a current source A, this current source A can draw or fill with the Partial charge sent on electric capacity Cs to be detected, another part electric charge on electric capacity Cs to be detected is then transferred on integrating capacitor Ci, the size △ Vout of operational amplifier A 0 output end voltage change in a charge transfer process so just can be reduced under the prerequisite additionally not increasing integrating capacitor Ci area, and then increase the capacitance value range of electric capacity Cs to be detected, and in testing process, do not reduce detection voltage, therefore can not cause the decline of signal to noise ratio (S/N ratio) yet.
For convenience of describing, suppose that the electric current of current source A is I herein, the time that current source is opened is T, according to charge-transfer theory, obtains following expression:
In expression formula, Δ Vout represents the size of operational amplifier A 0 output voltage change in a charge transfer process.Suppose that electric capacity Cs to be detected be 100pf, integrating capacitor Ci is 20pf, reference voltage Vref is 3.3V, and current source A current value I is taken as 150uA, and current source A opening time T is taken as 2us, then can obtain:
This is a rational magnitude of voltage.On the other hand, if when electric capacity Cs to be detected is less, we suitably can reduce current value I or the service time T of current source A, make △ Vout remain within the tolerance range of operational amplifier A 0, detect large-scale capacitance exactly further.
In the capacitance measurement process of reality, because Δ Vout, Vref, Ci, I, T in above-mentioned formula are known number, therefore can calculate the capacitance of electric capacity Cs to be detected very easily.
The second embodiment of the present invention relates to a kind of capacitive detection circuit, as Fig. 5.Second embodiment is roughly the same with the first embodiment, and key distinction part is: in the first embodiment, and electric capacity Cs to be detected fills with power transmission lotus to integrating capacitor Ci, is called reverse integral pattern; And in second embodiment of the invention, electric capacity Cs to be detected, from integrating capacitor Ci draw charge, is called forward integral mode.That is, in the present embodiment, the Partial charge on integrating capacitor Ci is filled with and is delivered on electric capacity Cs to be tested, and another part electric charge is shared by current source A.Its principle of work is identical with the first embodiment, does not repeat them here.
Persons of ordinary skill in the art may appreciate that the respective embodiments described above realize specific embodiments of the invention, and in actual applications, various change can be done to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (5)
1. a capacitive detection circuit, is characterized in that, comprises integrating capacitor Ci, electric capacity Cs to be detected, current source A, operational amplifier A 0 and signal processing chip;
One end of described electric capacity Cs to be detected is connected with the negative input end of described operational amplifier A 0, other end ground connection;
One end of described integrating capacitor Ci is connected with the negative input end of described operational amplifier A 0, and the other end is connected with the output terminal of described operational amplifier A 0;
One end of described current source A is connected with the negative input end of described operational amplifier A 0, other end ground connection;
The positive input terminal ground connection of described operational amplifier A 0;
One end of described signal processing chip is connected with the output terminal of described operational amplifier A 0, the capacitance of the electric capacity Cs to be detected that other end output detections arrives.
2. capacitive detection circuit according to claim 1, is characterized in that, size of current and the service time of described current source A can adjust in real time.
3. according to the capacitive detection circuit described in claim 1, it is characterized in that, described information processing chip, go out the capacitance of described electric capacity Cs to be detected according to following formulae discovery:
Vref*Cs＝ΔVout*Ci-I*T
Wherein, described Δ Vout is the output end voltage of described operational amplifier A 0 after a Charger transfer, described Vref is the reference voltage that described electric capacity to be detected is charged in sample phase, described Cs is the capacitance of described electric capacity to be detected, described Ci is the capacitance of described integrating capacitor, described I is the current value of described current source A, and described T is the time that described current source A opens.
4. the capacitive detection circuit according to claim 1 or 3, it is characterized in that, described capacitive detection circuit has two kinds of mode of operations, be that described electric capacity Cs to be detected fills with a reverse integral pattern for power transmission lotus to described integrating capacitor Ci, another kind is the forward integral mode of described electric capacity Cs to be detected from described integrating capacitor Ci draw charge.
5. capacitive detection circuit according to claim 1, is characterized in that, described signal processing chip comprises analog to digital converter and digital circuit processor;
One end of described analog to digital converter is connected with the output terminal of described operational amplifier, the other end is connected with the input end of described digital circuit processor, described analog to digital converter exports to described digital circuit processor after carrying out analog to digital conversion to the voltage that described operational amplifier exports;
Described digital circuit processor is used for, according to the digital signal after described analog to digital converter conversion, calculating the capacitance of described electric capacity Cs to be detected.
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| CN105024681A (en) * | 2015-06-25 | 2015-11-04 | 深圳市芯海科技有限公司 | Touch detection circuit capable of adjusting sensitivity and range |
| KR101972684B1 (en) | 2015-10-23 | 2019-04-25 | 선전 구딕스 테크놀로지 컴퍼니, 리미티드 | Capacitance detection sensors and related devices and systems |
| US10191589B2 (en) * | 2016-08-12 | 2019-01-29 | Stmicroelectronics Asia Pacific Pte Ltd | Sampling frequency and accumulator sweeping in a touch screen controller |
| CN107247190B (en) * | 2017-05-24 | 2019-09-10 | 欧常春 | A kind of capacitive detection circuit using charge zoom technology |
| CN107688798B (en) * | 2017-09-30 | 2023-10-17 | 苏州迈瑞微电子有限公司 | Charge type sensor, sensor array with charge type sensor and acquisition method of mismatch adjustment parameters of integrating circuit |
| CN108828322B (en) * | 2018-05-09 | 2024-02-06 | 江苏电子信息职业学院 | High-speed detection circuit of low-capacity capacitor |
| CN109342823B (en) * | 2018-09-29 | 2020-12-01 | 北京长城华冠汽车科技股份有限公司 | Measuring circuit and control method of Y capacitor and electric automobile |
| CN112485640B (en) * | 2020-11-18 | 2023-06-27 | 苏州华兴源创科技股份有限公司 | Method, device, equipment and storage medium for detecting built-in capacitor |
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