CN104316203A - Non-refrigeration infrared focal plane array driving control circuit integration design method - Google Patents
Non-refrigeration infrared focal plane array driving control circuit integration design method Download PDFInfo
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- CN104316203A CN104316203A CN201410557519.XA CN201410557519A CN104316203A CN 104316203 A CN104316203 A CN 104316203A CN 201410557519 A CN201410557519 A CN 201410557519A CN 104316203 A CN104316203 A CN 104316203A
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Abstract
The invention relates to a non-refrigeration infrared focal plane array driving control circuit integration design method which aims at overcoming the shortcomings that the existing non-refrigeration infrared focal plane array driving collection and temperature control circuit is complex in design, low in integration level and poor in flexibility. A field programmable gate array (FPGA) is utilized to achieve the non-refrigeration infrared focal plane array driving collection and temperature control circuit. The temperature control circuit enables all detection elements of the infrared focal plane array to be stabilized at reference temperature in the whole working process to improve the detection sensitivity of the infrared focal plane array. The FPGA logic control circuit is the core circuit for achieving driving, collection and temperature control of output signals of the whole infrared focal plane array, provides driving time sequence, collection time sequence and detector temperature control logic configuration time sequence of output signals of an infrared focal plane array detector to further process the follow-up infrared signals. The method has application and popularization value.
Description
Technical field
The present invention relates to uncooled infrared focal plane array thermal imaging field, specifically belong to infrared focal plane array driver' s timing, gather sequential and temperature Control timing sequence circuit design.
Background technology
Along with the development of infrared detection technique, requirement is proposed to the precision of infrared measurement of temperature and the quality of infrared imaging.Temperature taking process due to infra-red thermal imaging system can be subject to the impact of environmental factor and change, need to design a kind of flexible programmable temperature-control circuit for this reason and be operated in a certain stable temperature value with stable infrared detector, to improve temperature resolution and the detection sensitivity of detector; And the restriction of sensing circuit is carried by infrared focal plane detector, be difficult to directly read high-precision digital signal (as uncooled infrared focal plane array carries 6 position digital signal output functions), so additional A/D change-over circuit is a kind of inevitable choice to realize the collection of high precision infrared signal.The temperature-control circuit of existing infrared focal plane array seeker adopts the method for electric resistance partial pressure to produce fixed voltage value (the detector working temperature that different threshold voltages is corresponding different) usually, once resistance and voltage given, the voltage separated is fixed.If need to change control temperature, relevant voltage value needs to change, and bleeder circuit also wants corresponding adjustment, and this temperature-control circuit does not possess flexible programming ability, the poor universality of system.Propose to utilize FPGA device to drive infrared focal plane array for this reason herein, gather, temperature Control timing sequence carries out Integrated design, to realize the object of the small size of infra-red thermal imaging system control circuit, low-power consumption, low cost, high integration design.
Summary of the invention
The present invention is directed to infrared temperature control circuit in prior art and do not possess repetition programmability, the defects such as system design flexibility difference, provide a kind of uncooled infrared focal plane array to drive, gather and temperature-control circuit.Thermometric and imaging can be carried out to various thermal target object.Sequential control circuit of the present invention is made up of infrared signal time sequence driving circuit, temperature Control timing sequence circuit, A/D collection Control timing sequence circuit, fpga logic control circuit.The infrared energy that testee sends focuses on infrared focal plane array through infrared optical lens, convert infrared energy to electric signal by infrared focal plane array, and under the control of fpga logic sequential, driver output is carried out to video electrical signal by the sensing circuit of infrared focal plane array; Integrated operational amplifier amplifies the analog video signal exported, to meet the incoming video signal scope of A/D Acquisition Circuit; A/D Acquisition Circuit carries out analog to digital conversion to export discrete digital signal to video output signals under fpga logic sequential control; Under temperature-control circuit keeps the temperature of infrared focal plane array all detection units in the whole course of work to remain on a certain stationary temperature, with the image quality of the detection sensitivity and whole infra-red thermal imaging system that improve infrared focal plane array.Fpga logic control circuit is the core of whole infrared eye front-end controlling circuit, its produces the initial configuration sequential of the driver' s timing of infrared focal plane array seeker sensing circuit, acquisition control circuit sequential and temperature-control circuit, to export the simulating signal of certain amplitude, for the needs of follow-up A/D sampling and processing.The invention provides a kind of integral design method of uncooled infrared focal plane array Drive and Control Circuit, the peripheral components that the method needs is few, integrated level is high and flexible in programming, upgrading convenience, has promotion and application and be worth in infra-red thermal imaging system development.
Accompanying drawing explanation
Fig. 1 is infrared focal plane array sensing circuit (ROIC) driver' s timing oscillogram
Fig. 2 is infrared focal plane array front-end controlling circuit one-piece construction block diagram
Fig. 3 is fpga logic circuit integrating control schematic diagram
Fig. 4 is temperature-control circuit schematic diagram
Fig. 5 is the sequential that FPGA configures temperature control chip
Embodiment
Below in conjunction with accompanying drawing and instantiation, implementation method of the present invention is described.
Fig. 2 is infrared focal plane array front-end controlling circuit one-piece construction block diagram.Circuit is made up of crystal oscillating circuit, infrared optics part, infrared focal plane array seeker, temperature Control timing sequence circuit, A/D collection Control timing sequence circuit, fpga logic control module circuit.Crystal oscillating circuit adopts the passive crystal oscillator of 27MHz, and two are opened the electric capacity that shakes, for programming device provides input clock in addition; Detector adopts uncooled microbolometer focal plane arrays (FPA); A/D Acquisition Circuit adopts 16 the integrated chip VSP2566 carrying the single supply work of correlated-double-sampling; The thermoelectric cooling controller MAX1978 that temperature control circuit chip adopts MAXIN company to produce.
The infrared energy that testee sends focuses on infrared focal plane array seeker through infrared optical system, convert infrared energy to electric signal by infrared focal plane array seeker, and under the control of fpga logic control circuit, driver output is carried out to video electrical signal by the sensing circuit of infrared focal plane array seeker; Integrated operational amplifier amplifies the analog video signal exported, to meet the incoming video signal scope of A/D Acquisition Circuit; A/D Acquisition Circuit carries out analog to digital conversion to export discrete digital signal to video output signals under the control of fpga logic circuit; Temperature-control circuit keeps the temperature of infrared focal plane array all detection units in the whole course of work to keep at a constant temperature, with the image quality of the detection sensitivity and whole infra-red thermal imaging system that improve infrared focal plane array.Fpga logic control module circuit is the core of whole infrared eye front-end controlling circuit, its produces the initial configuration parameter of the driver' s timing of infrared focal plane array seeker sensing circuit, acquisition control circuit sequential and temperature-control circuit, to export the simulating signal of certain amplitude, for the needs of follow-up A/D sampling and processing.
Fig. 3 is fpga logic circuit integrating control schematic diagram.This control circuit primarily of frequency dividing circuit, detector time sequence driving circuit, temperature control initialization sequential circuit, A/D gather sequential circuit, integral time selection circuit, row field synchronization clock signal produces the formation such as circuit.
The clock signal of Fig. 3 peripheral crystal oscillator input obtains operating clock signals after FPGA divide by four circuit frequency division, this signal is as the master clock signal (as 6.75MHz signal) of infrared focal plane array seeker, and the reset of detector, integrated signal and initializing signal are all derive from master clock signal; The clock signal of the 6.75MHz that four frequency divisions obtain also can be used as the driver' s timing signal of control A/D Acquisition Circuit video data and the configuration signal of initialization A/D; The signal of the 6.75MHz that four frequency divisions obtain also can be used as the initializing signal of temperature control chip; The signal of the 6.75Hz that four frequency divisions obtain also can be used as A/D translated data output drive signal.The reset signal of front-end control infrared focal plane array seeker work, integrated signal and A/D collection signal all must strictly observe the requirement of infrared eye sensing circuit (ROIC) work schedule, just can collect infrared picture data effectively.The input signal that infrared eye wants normal need of work outside to provide three sequential to be strict with, i.e. master clock signal (TMC), integrated signal (INT), reset signal (RESET): TMC signal is the benchmark of whole circuit synchronization work, its dutycycle is 50%, and Pixel Information reads at the rising edge of each TMC signal.Rising edge and the negative edge time of TMC must be less than 10ns; The level value of INT signal changes at the rising edge of TMC signal, and its cycle must be greater than H+17 the TMC clock period (wherein H is line period signal), and the minimum integration time is 15 master clock cycles, and maximum integral time is H master clock cycle; RESET is the reset signal of ROIC circuit, each two field picture can only have a RESET signal, RESET signal must change state at the rising edge of TMC, the RESET signal period is at least greater than a TMC cycle, the negative edge of RESET signal must produce before the negative edge of INT signal, and the rising edge of RESET signal must occur in the INT negative edge after at least 15 TMC signal periods.
In Fig. 3, logical circuit specific works principle is as follows: after system electrification, FPGA first to outside input the active crystal oscillator of 27MHz carry out the major clock TMC signal that four frequency divisions obtain 6.75MHz, TMC signal synchronous under generate RESET signal, INT signal, row field sync signal and temperature control clock signal successively.Wherein TMC, RESET, INT signal sends into the strong and weak different voltage signal of amplitude that ROIC circuit could drive out each picture element corresponding successively according to the timing requirements of Fig. 1, A/D Acquisition Circuit be expert at field sync signal control under successively analog to digital conversion is carried out to the voltage signal of each pixel.AD7390C device in temperature control circuit major control Fig. 4 produces the magnitude of voltage of a certain setting, and concrete initialization sequential is see AD7390C device handbook.
The output signal (voltage signal that as infrared eye export be 0.8V ~ 4.2V) of operational amplifier in Fig. 3 to infrared focal plane array seeker adjusts the requirement meeting A/D Acquisition Circuit analog input voltage scope (-0.3V ~ 3.3V).Concrete A/D gathers sequential and produces as follows: if infrared focal plane array size is 384 × 288 picture dots, then every two field picture has 288 row, 384 row.So first FPGA generates some counters enter counting to TMC signal, after Counter Value reaches 384, produce a row signal (H), the linage-counter that recycling FPGA generates counts H, after linage-counter reaches 288, produce a column signal (V), the generative process of each width digital picture is all carry out analog to digital conversion generation by A/D successively under the control of TMC, H, V signal.
Fig. 4 is temperature-control circuit schematic diagram, and because non-refrigeration infrared detector inside is integrated with temperature sense resistance and refrigerant circuits, its temperature signal exported is directly inputted to the temperature input of temperature control chip MAX1978; By FPGA accurately control AD7390C device export setting magnitude of voltage, and output to MAX1978 temperature setting end, to realize the control to steady temperature in the infrared focal plane array course of work.If under the temperature value of the non-refrigerate infrared focal plane array seeker course of work is stabilized in certain temperature (as 25 DEG C), then its course of work is: in the infrared focal plane array course of work, the working temperature of its device itself converts corresponding voltage signal (calculating according to formula (1)) to by the output of VTEMP (temperature output) pin by the temperature sense resistance of its inside, and this voltage signal is input to the temperature input pin of MAX1978 in Fig. 4; And the magnitude of voltage corresponding to the temperature of 25 DEG C of setting produces (see hypomere content) by AD7390C and the temperature being input to MAX1978 sets end, inside differential amplifier through MAX1978 produces an output signal, infrared focal plane array seeker TEC-or TEC+ pin is sent to, to carry out refrigeration or heating to detector through pin OS1 or OS2 of MAX1978.When the temperature rise of detector itself is greater than set temperature value 25 DEG C, MAX1978 inputs a current signal by OUT A pin, and this signal comes from the TEC-pin of detector, to carry out refrigeration processes to detector; When the temperature rise of detector itself is less than set temperature value 25 DEG C, MAX1978 exports by OUT B pin the TEC+ pin that a current signal enters detector, to carry out heating process to detector, finally reach the working temperature of stability contorting infrared focal plane array seeker.The working temperature corresponding relation of the voltage that VTEMP pin exports and this province of infrared focal plane array device can be expressed with equation (1):
V0＝0.00645×T0-0.2 (1)
Wherein ,-0.00645 is the induction coefficient of infrared focal plane array seeker internal temperature inductive reactance, and unit is V/K; V0 is the output voltage of VTEMP pin, and the working temperature of to be V, T0 be this province of infrared focal plane array seeker of unit, unit is Kelvin (K).
Outside SDI, CLK, the LD tri-of chip AD7390C controls pin, and wherein SDI is serial data input pin, and CLK is clock input pin, and LD is for writing control pin.When LD is effective, the bit on SDI writes shift register successively under the driving of CLK signal.When LD is invalid, the data in shift register are written to analog to digital conversion register and carry out D/A conversion to export analog voltage signal.The specific works process that AD7390C chip produces magnitude of voltage corresponding to 25 DEG C of temperature is as follows: the relation of output voltage V1 and the SDI of AD7390C chip: V1=VRF × SDI/4096, wherein VRF is fixed voltage value, as long as the binary data of 25 DEG C of temperature corresponding voltage to be sent into the translation register of AD7390C here by SDI, the magnitude of voltage that can realize setting exports.25 DEG C being converted into kelvin degree is 303K, it is 1.735V that substitution formula (1) obtains magnitude of voltage, it is 2842 (being converted to scale-of-two is 101100011010) utilize FPGA a to produce Binary time and order writes AD7390C shift registers by 101100011010 that magnitude of voltage is converted to SDI value by recycling formula V1=VRF × SDI/4096, by the 1.735V analog voltage of the change and exportable setting that control its LD pin level.FPGA produces the sequential of binary one 01100011010 as shown in Figure 5.
Claims (3)
1. the integrated approach of a uncooled infrared focal plane array Drive and Control Circuit, it is characterized in that, it is made up of infrared focal plane array output signal driver circuit, A/D acquisition control circuit, precision temperature control configuration circuit, fpga logic control circuit, the infrared energy that testee sends focuses on the focal plane arrays (FPA) of infrared eye, convert infrared energy to electric signal by infrared focal plane array, and under the driving of fpga logic sequential, export infrared signal by the sensing circuit of infrared focal plane array; Integrated operational amplifier amplifies to vision signal the analog input voltage scope meeting A/D Acquisition Circuit; A/D Acquisition Circuit carries out analog to digital conversion to export discrete digital signal to output infrared signal under the control of fpga logic control circuit; Temperature-control circuit keeps the temperature of all detection units of infrared focal plane array to remain on a certain stable temperature value; Fpga logic control circuit produces the driver' s timing of infrared focal plane array seeker sensing circuit, the Control timing sequence of A/D Acquisition Circuit and the initial configuration sequential of temperature-control circuit.
2. the integrated approach of uncooled infrared focal plane array Drive and Control Circuit according to claim 1, it is characterized in that: the clock signal of fpga logic control circuit peripheral crystal oscillator input obtains operating clock signals after FPGA frequency dividing circuit frequency division, as the sensing circuit driver' s timing signal of infrared focal plane array seeker, the interface sequence control signal that the clock signal gathered as control A/D and A/D translation data export; As the initialization clock signal of temperature control chip.
3. the integrated approach of uncooled infrared focal plane array Drive and Control Circuit according to claim 1, the magnitude of voltage of the accurate control temperature control chip that it is characterized in that can being programmed by FPGA, reaches the object of flexible design.
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Cited By (9)
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| CN105466568A (en) * | 2015-12-24 | 2016-04-06 | 何兴扬 | Life entity detector and aircraft with life entity detector |
| CN106248218A (en) * | 2016-08-31 | 2016-12-21 | 宁波智轩物联网科技有限公司 | A kind of human body detection device and determination methods thereof |
| CN106706140A (en) * | 2017-01-19 | 2017-05-24 | 中国科学院上海技术物理研究所 | Portable infrared focal plane detector function test device |
| CN106787679A (en) * | 2016-12-21 | 2017-05-31 | 中国航天时代电子公司 | A kind of infrared focal plane array electric power management circuit |
| CN106959711A (en) * | 2017-05-11 | 2017-07-18 | 江苏北方湖光光电有限公司 | Suppress the control system and method for infrared focus plane temperature anomaly |
| CN107084797A (en) * | 2017-03-30 | 2017-08-22 | 智来光电科技（苏州）有限公司 | Domestic infrared detector simulation output self-adapting adjusting apparatus and its method of adjustment |
| CN111397737A (en) * | 2020-03-23 | 2020-07-10 | 重庆邮电大学 | DSP + FPGA's infrared imaging signal real-time processing system |
| CN113125011A (en) * | 2021-03-12 | 2021-07-16 | 中国科学院西安光学精密机械研究所 | Medium wave infrared Hadamard aperture coding spectrum high frame frequency imaging circuit |
| CN113176535A (en) * | 2021-04-27 | 2021-07-27 | 北京航空航天大学 | High-precision omnibearing infrared positioning module based on normalization algorithm |
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Cited By (13)
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| CN105466568A (en) * | 2015-12-24 | 2016-04-06 | 何兴扬 | Life entity detector and aircraft with life entity detector |
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| CN106787679B (en) * | 2016-12-21 | 2018-12-14 | 中国航天时代电子公司 | A kind of infrared focal plane array electric power management circuit |
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| CN107084797A (en) * | 2017-03-30 | 2017-08-22 | 智来光电科技（苏州）有限公司 | Domestic infrared detector simulation output self-adapting adjusting apparatus and its method of adjustment |
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| CN111397737A (en) * | 2020-03-23 | 2020-07-10 | 重庆邮电大学 | DSP + FPGA's infrared imaging signal real-time processing system |
| CN113125011A (en) * | 2021-03-12 | 2021-07-16 | 中国科学院西安光学精密机械研究所 | Medium wave infrared Hadamard aperture coding spectrum high frame frequency imaging circuit |
| CN113125011B (en) * | 2021-03-12 | 2022-07-19 | 中国科学院西安光学精密机械研究所 | Medium wave infrared Hadamard aperture coding spectrum high frame frequency imaging circuit |
| CN113176535A (en) * | 2021-04-27 | 2021-07-27 | 北京航空航天大学 | High-precision omnibearing infrared positioning module based on normalization algorithm |
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Application publication date: 20150128 |