CN105161498A - 薄膜晶体管及其制作方法、阵列基板以及显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板以及显示装置 Download PDF

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CN105161498A
CN105161498A CN201510479312.XA CN201510479312A CN105161498A CN 105161498 A CN105161498 A CN 105161498A CN 201510479312 A CN201510479312 A CN 201510479312A CN 105161498 A CN105161498 A CN 105161498A
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active layer
amorphous silicon
silicon material
substrate
grid
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CN105161498B (zh
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王祖强
杨玉清
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BOE Technology Group Co Ltd
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Priority to EP16832035.6A priority patent/EP3336897B1/en
Priority to US15/519,948 priority patent/US10128354B2/en
Priority to KR1020177009936A priority patent/KR101912760B1/ko
Priority to PCT/CN2016/070007 priority patent/WO2017020542A1/zh
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Abstract

本发明公开了一种薄膜晶体管及其制作方法、阵列基板以及显示装置，属于显示装置领域。所述薄膜晶体管制作方法，包括：提供一基板；在所述基板上依次制作栅极、栅极绝缘层、非晶硅材料有源层和盖帽层，所述盖帽层在远离所述非晶硅材料有源层的一面上形成有图案，所述图案由至少一条沿所述有源层的长度方向的凹槽和至少一条沿所述有源层的宽度方向的凹槽构成；对所述非晶硅材料有源层进行激光退火处理，使所述非晶硅材料有源层转化为低温多晶硅材料有源层；除去所述盖帽层。

Description

薄膜晶体管及其制作方法、阵列基板以及显示装置
技术领域
本发明涉及显示装置领域，特别涉及一种薄膜晶体管及其制作方法、阵列基板以及显示装置。
背景技术
在薄膜晶体管(ThinFilmTransistor，简称TFT)的制作工艺中，常采用低温多晶硅(LowTemperaturePolySilicon，简称LTPS)薄膜作为TFT中有源层的材料。
目前，TFT的制备过程中主要采用准分子激光退火法(ExcimerLaserAnnealing，简称ELA)来形成LTPS薄膜。其中，ELA法主要通过一定能量的准分子激光对非晶硅薄膜进行激光照射，利用激光光束的能量使非晶硅在高温下转变成LTPS。然而，由于非晶硅受到激光照射时，其内部各个区域受照射产生的温度是相同的，因此，晶化后的多晶硅晶粒在LTPS薄膜中的生长区域是随机的，这就使得LTPS薄膜中的晶粒尺寸大小不一，均匀性较差，使得TFT沟道(channel)中晶界较多，导致TFT导通时的漏电流较大，进而导致TFT的阈值电压不稳定，从而降低了TFT的整体电性能。
发明内容
本发明实施例提供了一种薄膜晶体管及其制作方法、阵列基板以及显示装置，使得TFT具有良好的电性能。所述技术方案如下：
第一方面，本发明实施例提供了一种薄膜晶体管制作方法，所述方法包括：
提供一基板；
在所述基板上依次制作栅极、栅极绝缘层、非晶硅材料有源层和盖帽层，所述盖帽层在远离所述非晶硅材料有源层的一面上形成有图案，所述图案由至少一条沿所述有源层的长度方向的凹槽和至少一条沿所述有源层的宽度方向的凹槽构成；
对所述非晶硅材料有源层进行激光退火处理，使所述非晶硅材料有源层转化为低温多晶硅材料有源层；
除去所述盖帽层。
在本发明实施例的一种实现方式中，所述在基板上依次制作栅极、栅极绝缘层、非晶硅材料有源层和盖帽层，包括：
在所述基板上制作栅极；
在所述栅极上制作栅极绝缘层；
在所述栅极绝缘层上依次形成非晶硅材料薄膜和氧化物薄膜；
采用构图工艺处理所述非晶硅材料薄膜和氧化物薄膜，得到所述非晶硅材料有源层和盖帽层。
在本发明实施例的另一种实现方式中，所述采用构图工艺处理所述非晶硅材料薄膜和氧化物薄膜，包括：
采用半色调掩膜工艺处理所述非晶硅材料薄膜和所述氧化物薄膜。
在本发明实施例的另一种实现方式中，所述氧化物薄膜为二氧化硅薄膜或者氧化铟锡薄膜。
在本发明实施例的另一种实现方式中，所述图案在所述基板的垂直方向上的投影位于所述栅极上。
在本发明实施例的另一种实现方式中，所述图案在所述基板的垂直方向上的投影的中心位于所述栅极的中心。
在本发明实施例的另一种实现方式中，所述盖帽层形成有所述凹槽的部分的厚度为2-5纳米，所述盖帽层未形成有所述凹槽的部分的厚度为10-30纳米。
在本发明实施例的另一种实现方式中，所述图案包括至少2条沿所述有源层的长度方向的凹槽和至少2条沿所述有源层的宽度方向的凹槽，且所述凹槽交点呈矩阵分布。
在本发明实施例的另一种实现方式中，任意两条相邻且平行的所述凹槽之间的距离为2-5微米。
在本发明实施例的另一种实现方式中，所述方法还包括：
在制作所述栅极前，在所述基板上制作一层缓冲层。
第二方面，本发明实施例提供了一种薄膜晶体管，包括基板、依次覆盖在所述基板上的栅极、栅极绝缘层和低温多晶硅材料有源层，所述低温多晶硅材料有源层包括第一区域和第二区域，所述第一区域在垂直于所述基板的方向上位于所述栅极的正上方，所述第一区域内的晶界将所述第一区域划分为多个第一子区域，所述第二区域内的晶界将所述第二区域划分为多个第二子区域，所述第一子区域大于所述第二子区域，所述多个第一子区域呈矩阵排列。
第三方面，本发明实施例提供了一种阵列基板，所述阵列基板包括如上所述的薄膜晶体管。
第四方面，本发明实施例提供了一种显示装置，所述显示装置包括如上所述的阵列基板。
本发明实施例提供的技术方案带来的有益效果是：
本发明实施例中，非晶硅在进行晶化时，由于盖帽层在图案处的厚度更薄，激光照射下的非晶硅材料薄膜先进入完全融化状态，使得形核中心位于图案形成的矩形的区域中央的正下方，而晶粒成长方向背离形核中心，于是在图案中凹槽的下方形成晶界，采用这种制作方法可以对LTPS薄膜中处于盖帽层下方的多晶硅中晶界数量、方向、位置等进行控制，从而减少TFT沟道中晶界的数量，减小TFT导通时的漏电流，从而提高TFT的整体电性能。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种薄膜晶体管制作方法的流程图；
图2是本发明实施例提供的另一种薄膜晶体管制作方法的流程图；
图2a是本发明实施例提供的薄膜晶体管在制作过程中的结构示意图；
图2b是本发明实施例提供的薄膜晶体管在制作过程中的结构示意图；
图2c是本发明实施例提供的薄膜晶体管在制作过程中的结构示意图；
图2d是本发明实施例提供的薄膜晶体管在制作过程中的结构示意图；
图2e是本发明实施例提供的薄膜晶体管在制作过程中的结构示意图；
图2f是本发明实施例提供的薄膜晶体管在制作过程中的结构示意图；
图2g是本发明实施例提供的晶粒生长方向图；
图2h是本发明实施例提供的薄膜晶体管在制作过程中的结构示意图；
图3是本发明实施例提供的一种薄膜晶体管的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。附图中各层薄膜的厚度和形状不反映阵列基板的真实比例，目的只是示意说明本发明内容。
图1是本发明实施例提供的一种薄膜晶体管制作方法的流程图，参见图1，该方法包括：
步骤101：提供一基板。
步骤102：在基板上依次制作栅极、栅极绝缘层、非晶硅材料有源层和盖帽层，盖帽层在远离非晶硅材料有源层的一面上形成有图案，图案由至少一条沿有源层的长度方向的凹槽和至少一条沿有源层的宽度方向的凹槽构成。
步骤103：对非晶硅材料有源层进行激光退火处理，使非晶硅材料有源层转化为低温多晶硅材料有源层。
步骤104：除去盖帽层。
本发明实施例中，非晶硅在进行晶化时，由于盖帽层在图案处的厚度更薄，激光照射下的非晶硅材料薄膜先进入完全融化状态，使得形核中心位于图案形成的矩形的区域中央的正下方，而晶粒成长方向背离形核中心，于是在图案中凹槽的下方形成晶界，采用这种制作方法可以对LTPS薄膜中处于盖帽层下方的多晶硅中晶界数量、方向、位置等进行控制，从而减少TFT沟道中晶界的数量，减小TFT导通时的漏电流，从而提高TFT的整体电性能。
图2是本发明实施例提供的另一种薄膜晶体管制作方法的流程图，参见图2，该方法包括：
步骤201：提供一基板。
其中，基板可为玻璃基板、透明塑料基板等。
步骤202：在基板上制作栅极。
如图2a所示，步骤201中提供的基板301可以事先覆盖有一缓冲层301A，然后再形成栅极302。因此，该方法还包括：在制作栅极前，在基板上制作一层缓冲层。其中，缓冲层具体可以为硅的氮化物(例如SiN)层或硅的氧化物(例如SiO2)层。
其中，栅极可以为金属栅极，制作栅极的过程可以包括：先在缓冲层上形成一层金属层，然后通过构图工艺处理该金属层，形成上述栅极。
步骤203：在栅极上制作栅极绝缘层。
如图2b所示，在栅极302上形成栅极绝缘层303。
其中，栅极绝缘层具体可以为硅的氮化物(例如SiN)层或硅的氧化物(例如SiO2)层。
步骤204：在栅极绝缘层上依次形成非晶硅材料薄膜和氧化物薄膜。
如图2c所示，在栅极绝缘层303上覆盖非晶硅材料薄膜3041和氧化物薄膜3051。
其中，氧化物薄膜为二氧化硅薄膜或者氧化铟锡(IndiumTinOxides，简称ITO)薄膜，或其他氧化物薄膜。
步骤205：采用构图工艺处理非晶硅材料薄膜和氧化物薄膜，得到非晶硅材料有源层和盖帽层。盖帽层在远离非晶硅材料有源层的一面上形成有图案，图案由至少一条沿有源层的长度方向的凹槽和至少一条沿有源层的宽度方向的凹槽构成。
如图2d所示，采用构图工艺处理非晶硅材料薄膜3041和氧化物薄膜3051后，得到非晶硅材料有源层3042和盖帽层305。
图2e是图2d所示的结构的立体示意图，如图2e所示，图案由至少一条沿有源层的沟道长度方向(即图中AA’方向)的凹槽a和至少一条沿有源层的沟道宽度方向(即图中BB’方向)的凹槽b构成。
本发明实施例中，有源层的长度方向与TFT通电后沟道的长度方向一致，有源层的宽度方向与TFT通电后沟道的宽度方向一致。沟道的长度方向即沟道区域中电流的流动方向，沟道的宽度方向则是沟道区域中垂直于沟道的长度方向的方向。
其中，步骤205中的构图工艺可以采用掩膜板光刻蚀工艺实现，盖帽层与有源层构图一步完成，没有增加额外刻蚀工艺。具体地步骤205可以包括：采用半色调掩膜(Halftone)工艺处理非晶硅材料薄膜和氧化物薄膜，得到非晶硅材料有源层和盖帽层。
具体地，图案在基板的垂直方向上的投影位于栅极上。即该图案与沟道区域对应，因为在本发明实施例中只需要改善有源层沟道区域的多晶硅中晶界数量，进而减少缺陷(defect)态数量，即可提高TFT的整体电性能。
进一步地，图案在基板的垂直方向上的投影的中心位于栅极的中心。
盖帽层形成有凹槽的部分的厚度为2-5纳米，盖帽层未形成有凹槽的部分的厚度为10-30纳米。本发明实施例通过上述盖帽层的厚度设置，保证激光在图案和非图案处的温度差异，从而对晶界的形成起诱导和引导作用。。
具体地，图案包括至少2条沿有源层的长度方向的凹槽和至少2条沿有源层的宽度方向的凹槽，且凹槽交点呈矩阵分布。
进一步地，在本发明实施例中，图案中凹槽数量，可以根据TFT的沟道宽度、长度而定，TFT的沟道宽度、长度数值越大，图案中凹槽数量越多。在本发明实施例中，任意两条相邻且平行的凹槽之间的距离可以为2-5微米。
其中，图案中凹槽的距离用于限定有源层中晶界的数量和排列，上述距离设置可以保证有源层中沟道区域的晶界数量少。
步骤206：对非晶硅材料有源层进行激光退火处理，使非晶硅材料有源层转化为低温多晶硅材料有源层。
如图2f所示，非晶硅材料有源层3042在激光照射下融化结晶形成低温多晶硅材料有源层304。
当激光照射到盖帽层时，非晶硅材料融化结晶在沟道长度方向(图2e中AA’方向)上，在靠近栅极边缘，由于坡度处非晶硅材料较厚，ELA照射时发生部分融化，此时会在AA’方向上形成了温度梯度，因此，晶粒生长从未完全融化部分向融化部分推进，形成垂直于沟道的晶界。
同时沟道宽度方向(图2e中BB’方向)上，沟道边缘的冷却速度快于中间部分，因此，沿BB’方向的也存在温度梯度，将导致晶粒生长从边缘向中间推进，形成平行于沟道方向的晶界。
另一方面，栅极上方的晶界是在盖帽层的图案作用下形成的。在晶化时，图案中的凹槽处较薄，先进入完全融化状态，于是形核中心位于凹槽分割的区域中央，晶粒生长方向背离形核中心，于是在凹槽下方形成晶界。
晶粒生长方向如图2g所示，在靠近栅极302边缘，晶粒304A生长从未完全融化部分向融化部分推进，形成垂直于沟道的晶界304B。另外，形核中心位于凹槽b分割的区域中央，晶粒304A生长方向背离形核中心，于是在凹槽b下方形成晶界304B。
步骤207：除去盖帽层。
如图2h所示，除去低温多晶硅材料有源层304上的盖帽层305。
具体地，在本发明实施例中可以采用刻蚀工艺去除盖帽层。
进一步地，该方法还包括：在有源层相对两侧制作源极和漏极。
本发明实施例中，非晶硅在进行晶化时，由于盖帽层在图案处的厚度更薄，激光照射下的非晶硅材料薄膜先进入完全融化状态，使得形核中心位于图案形成的矩形的区域中央的正下方，而晶粒成长方向背离形核中心，于是在图案中凹槽的下方形成晶界，采用这种制作方法可以对LTPS薄膜中处于盖帽层下方的多晶硅中晶界数量、方向、位置等进行控制，从而减少TFT沟道中晶界的数量，减小TFT导通时的漏电流，从而提高TFT的整体电性能。
本发明实施例提供了一种薄膜晶体管，包括基板、依次覆盖在基板上的栅极、栅极绝缘层和低温多晶硅材料有源层，低温多晶硅材料有源层包括第一区域和第二区域，第一区域在垂直于基板的方向上位于栅极的正上方，第一区域内的晶界将第一区域划分为多个第一子区域，第二区域内的晶界将第二区域划分为多个第二子区域，第一子区域大于第二子区域，多个第一子区域呈矩阵排列。
本发明实施例中，有源层中第一区域中第一子区域的数量大于第二区域中第二子区域的数量，由于第一子区域和第二子区域均由晶界划分而成，由此可知，第一区域中的晶界少于第二区域中的晶界，其中第一区域位于栅极的正上方，即为沟道区域，所以上述结构的薄膜晶体管中沟道区域的晶界数量少；沟道区域的晶界数量少，减小了TFT导通时的漏电流，从而提高TFT的整体电性能。
图3显示了本发明实施例提供的一薄膜晶体管的具体结构。图3是本发明实施例提供的一种薄膜晶体管的结构示意图。如图3所示，该薄膜晶体管采用图2提供的方法制成，具体包括：基板301、以及形成于基板301上的缓冲层301A、设置在缓冲层301A上的有源层栅极302、设置在栅极302上的栅极绝缘层303、设置在栅极绝缘层303上的有源层304、设置在有源层304相对两侧且与有源层304相接触的源极305和漏极306，有源层304为低温多晶硅材料有源层。低温多晶硅材料有源层304包括第一区域和第二区域，第一区域位于栅极302的正上方，第一区域内的晶界将第一区域划分为多个第一子区域，第二区域内的晶界将第二区域划分为多个第二子区域，第一子区域大于第二子区域，多个第一子区域呈矩阵排列。
本发明实施例中，有源层中第一区域中第一子区域的数量大于第二区域中第二子区域的数量，由于第一子区域和第二子区域均由晶界划分而成，由此可知，第一区域中的晶界少于第二区域中的晶界，其中第一区域位于栅极的正上方，即为沟道区域，所以上述结构的薄膜晶体管中沟道区域的晶界数量少；沟道区域的晶界数量少，减小了TFT导通时的漏电流，从而提高TFT的整体电性能。
本发明实施例还提供了一种阵列基板，该阵列基板包括前述任一实施例提供的薄膜晶体管。具体地，该阵列基板还包括设置在基板上的栅线、数据线及像素电极层等结构，该薄膜晶体管的漏极与像素电极层连接，薄膜晶体管的栅极与栅线连接，薄膜晶体管的源极与数据线连接。
其中，像素电极层可以为透明的导电金属氧化物层，例如ITO、氧化铟锌(IndiumZincOxides，简称IZO)等。
基于相同的发明构思，本发明实施例还提供了一种显示装置，该显示装置包括前述实施例提供的阵列基板。
在具体实施时，本发明实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

1.一种薄膜晶体管制作方法，其特征在于，所述方法包括：
提供一基板；
在所述基板上依次制作栅极、栅极绝缘层、非晶硅材料有源层和盖帽层，所述盖帽层在远离所述非晶硅材料有源层的一面上形成有图案，所述图案由至少一条沿所述有源层的长度方向的凹槽和至少一条沿所述有源层的宽度方向的凹槽构成；
对所述非晶硅材料有源层进行激光退火处理，使所述非晶硅材料有源层转化为低温多晶硅材料有源层；
除去所述盖帽层。
2.根据权利要求1所述的方法，其特征在于，所述在基板上依次制作栅极、栅极绝缘层、非晶硅材料有源层和盖帽层，包括：
在所述基板上制作栅极；
在所述栅极上制作栅极绝缘层；
在所述栅极绝缘层上依次形成非晶硅材料薄膜和氧化物薄膜；
采用构图工艺处理所述非晶硅材料薄膜和氧化物薄膜，得到所述非晶硅材料有源层和盖帽层。
3.根据权利要求2所述的方法，其特征在于，所述采用构图工艺处理所述非晶硅材料薄膜和氧化物薄膜，包括：
采用半色调掩膜工艺处理所述非晶硅材料薄膜和所述氧化物薄膜。
4.根据权利要求2所述的方法，其特征在于，所述氧化物薄膜为二氧化硅薄膜或者氧化铟锡薄膜。
5.根据权利要求1-4任一项所述的方法，其特征在于，所述图案在所述基板的垂直方向上的投影位于所述栅极上。
6.根据权利要求5所述的方法，其特征在于，所述图案在所述基板的垂直方向上的投影的中心位于所述栅极的中心。
7.根据权利要求1-4任一项所述的方法，其特征在于，所述盖帽层形成有所述凹槽的部分的厚度为2-5纳米，所述盖帽层未形成有所述凹槽的部分的厚度为10-30纳米。
8.根据权利要求1-4任一项所述的方法，其特征在于，所述图案包括至少2条沿所述有源层的长度方向的凹槽和至少2条沿所述有源层的宽度方向的凹槽，且所述凹槽交点呈矩阵分布。
9.根据权利要求8所述的方法，其特征在于，任意两条相邻且平行的所述凹槽之间的距离为2-5微米。
10.根据权利要求1-4任一项所述的方法，其特征在于，所述方法还包括：
在制作所述栅极前，在所述基板上制作一层缓冲层。
11.一种薄膜晶体管，包括基板、依次覆盖在所述基板上的栅极、栅极绝缘层和低温多晶硅材料有源层，其特征在于，所述低温多晶硅材料有源层包括第一区域和第二区域，所述第一区域在垂直于所述基板的方向上位于所述栅极的正上方，所述第一区域内的晶界将所述第一区域划分为多个第一子区域，所述第二区域内的晶界将所述第二区域划分为多个第二子区域，所述第一子区域大于所述第二子区域，所述多个第一子区域呈矩阵排列。
12.一种阵列基板，其特征在于，所述阵列基板包括如权利要求11所述的薄膜晶体管。
13.一种显示装置，其特征在于，所述显示装置包括如权利要求12所述的阵列基板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017020542A1 (zh) * 2015-08-03 2017-02-09 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板以及显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113394299A (zh) * 2021-06-16 2021-09-14 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制备方法、显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060276013A1 (en) * 2005-06-03 2006-12-07 Au Optronics Corp. Sequential lateral solidification mask
CN101202218A (zh) * 2007-12-19 2008-06-18 友达光电股份有限公司 应用于连续性侧向长晶技术的掩膜以及激光结晶方法
CN103700695A (zh) * 2013-12-25 2014-04-02 深圳市华星光电技术有限公司 低温多晶硅薄膜及其制备方法、晶体管
CN104538310A (zh) * 2015-01-16 2015-04-22 京东方科技集团股份有限公司 低温多晶硅薄膜的制备方法、tft、阵列基板及显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4101409B2 (ja) 1999-08-19 2008-06-18 シャープ株式会社 半導体装置の製造方法
JP4190798B2 (ja) * 2002-05-08 2008-12-03 Ｎｅｃ液晶テクノロジー株式会社 薄膜トランジスタ及びその製造方法
US6939754B2 (en) * 2003-08-13 2005-09-06 Sharp Laboratories Of America, Inc. Isotropic polycrystalline silicon and method for producing same
TWI228832B (en) * 2004-04-05 2005-03-01 Quanta Display Inc Structure of LTPS-TFT and fabricating method of channel layer thereof
KR101375834B1 (ko) * 2007-11-20 2014-03-18 삼성전자주식회사 다결정 실리콘 박막 및 이를 적용하는 박막 트랜지스터의제조방법
US7749820B2 (en) * 2008-03-07 2010-07-06 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, manufacturing method thereof, display device, and manufacturing method thereof
CN101834138A (zh) 2010-02-09 2010-09-15 广东中显科技有限公司 一种晶化薄膜的晶体管器件的制备方法
CN102610520A (zh) 2011-01-19 2012-07-25 广东中显科技有限公司 一种多晶硅薄膜晶体管的制备方法
CN103681776B (zh) * 2013-12-24 2017-11-07 京东方科技集团股份有限公司 低温多晶硅薄膜及其制备方法、薄膜晶体管和显示装置
CN105161498B (zh) 2015-08-03 2017-09-19 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板以及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060276013A1 (en) * 2005-06-03 2006-12-07 Au Optronics Corp. Sequential lateral solidification mask
CN101202218A (zh) * 2007-12-19 2008-06-18 友达光电股份有限公司 应用于连续性侧向长晶技术的掩膜以及激光结晶方法
CN103700695A (zh) * 2013-12-25 2014-04-02 深圳市华星光电技术有限公司 低温多晶硅薄膜及其制备方法、晶体管
CN104538310A (zh) * 2015-01-16 2015-04-22 京东方科技集团股份有限公司 低温多晶硅薄膜的制备方法、tft、阵列基板及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017020542A1 (zh) * 2015-08-03 2017-02-09 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板以及显示装置
US10128354B2 (en) 2015-08-03 2018-11-13 Boe Technology Group Co., Ltd. Thin film transistor, method for manufacturing the same, array substrate and display device

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