CN105097823A - Double-vertical-window three-buried layer SOI high-voltage device structure - Google Patents
Double-vertical-window three-buried layer SOI high-voltage device structure Download PDFInfo
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- CN105097823A CN105097823A CN201410216653.3A CN201410216653A CN105097823A CN 105097823 A CN105097823 A CN 105097823A CN 201410216653 A CN201410216653 A CN 201410216653A CN 105097823 A CN105097823 A CN 105097823A
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Abstract
The invention discloses a double-vertical-window three-buried layer SOI high-voltage device structure. The device structure is shown in Figure 1. Buried layers of the structure contain a three oxidation layer, the two windows do not be parallel to the buried layers or the first buried layer and the second buried layer are not on the same plane, and the first layer and the third layer are connected through silicon dioxide. Polycrystalline silicon is filled between the first and second buried oxide layers and the third buried oxide layer. The method improves a longitudinal breakdown voltage through enhancement of an electric field of the third buried oxide layer and silicon windows, capable of modulating a drift region electric field, of the first and second buried oxide layers.
Description
Technical field
The present invention relates to high tension apparatus field, particularly relate to many buried regions SOI high-voltage device structure.
Background technology
The structure of SOI uniqueness brings that isolation performance is good, leakage current is little, speed is fast, Flouride-resistani acid phesphatase and the advantage such as low in energy consumption, the potentiality of silicon integrated circuit technology are given full play to, particularly SOI high voltage integrated circuit has special role in Flouride-resistani acid phesphatase field, empty sky in future, is thus able to broad development and application.SOI lateral high-voltage device, as the foundation stone of high voltage integrated circuit, because dielectric layer prevents its depletion region to expand to substrate layer, such that the device commonly used is longitudinally withstand voltage only to be born by top layer silicon and dielectric layer.And because of the restriction isolated and dispel the heat, top layer silicon and dielectric layer all can not be too thick, simultaneously by interface without electric charge Gauss theorem, dielectric layer electric field during device breakdown is made to be only 3 times about 100V/ μm of silicon critical field, reach far away actual typical media material as the critical field 600V/ μm of SiO, so SOI lateral high-voltage device is longitudinally withstand voltage lower, limit the application and development of high voltage integrated circuit, drop into the bottleneck also not breaking through 600V of application at present.To this, lot of domestic and foreign scholar conduct in-depth research, and work at present mainly concentrates on and uses new device structure to improve longitudinal voliage.
Industry usually changes the doping content of regional or changes oxygen buried layer structure to increase the electric field strength of oxygen buried layer and to make electric field line evenly distribution, improves longitudinal puncture voltage.
Existing SOI high-voltage device structure is set forth below with the two buried regions SOI high tension apparatus of single window.
Fig. 1 is the structural representation of SOI high tension apparatus in prior art, and the buried regions of this structure comprises two-layer oxide layer, and the first oxygen buried layer has single window, fills polysilicon between two oxide layers.Ground floor buries oxygen and blocks the extraction of transverse electric field to the second oxygen buried layer and polysilicon interface inversion layer charge, and this inversion charge will strengthen the electric field of second layer oxygen buried layer greatly; The silicon window of the first oxygen buried layer can modulate drift region electric field simultaneously, thus can obtain higher puncture voltage.But relative to application request, the puncture voltage of this SOI high-voltage device structure still needs further raising.
Summary of the invention
The invention provides the structure of double window three layers of SOI high tension apparatus, to improve the puncture voltage of SOI device.
The invention provides the structure of double window three layers of SOI high tension apparatus, include three layers of oxygen buried layer and two windows, the oxygen buried layer of these two windows and level is angled.
Optionally, described angle is 90 ° or other angles (be less than 180 ° and be greater than 0 °).
Optionally, described front two-layer oxygen buried layer is interchangeable, and namely the first buried regions drops under the second buried regions.
Optionally, the vertical range between described front two-layer oxygen buried layer is variable.
Optionally, the articulamentum of ground floor and third layer is variable to the distance of device left margin.
Optionally, the polysilicon of filling can change other materials into.
Accompanying drawing explanation
Fig. 1 is the structural representation of single window SOI high tension apparatus;
Fig. 2 is the structural representation of double window SOI high tension apparatus.
Embodiment
Fig. 2 is double window three buried regions SOI high-voltage device structure schematic diagram in first embodiment of the invention, this structure employ window vertical with oxygen buried layer and structure before the two-layer oxygen that buries block the extraction of transverse electric field to the 3rd oxygen buried layer and polysilicon interface inversion layer charge, this inversion charge will strengthen the electric field of third layer oxygen buried layer greatly; The silicon window of the first oxygen buried layer can modulate drift region electric field simultaneously, thus can obtain higher longitudinal puncture voltage.
Claims (6)
1. the two buried regions SOI high-voltage device structure of double window, comprise the polysilicon layer between three layers of oxygen buried layer and oxygen buried layer, it is characterized in that not parallel with buried regions or the first buried regions of opened two windows (the first buried regions two ends respectively with the line at the second buried regions two ends) and the second buried regions not at grade, the filling polysilicon between or two layers and third layer buried regions.
2. the two buried regions SOI high-voltage device structure of double window as claimed in claim 1, it is characterized in that, described window and buried regions angulation are be greater than the angle that 0 ° is less than 180 °.
3. the two buried regions SOI high-voltage device structure of double window as claimed in claim 1, described front two-layer oxygen buried layer is interchangeable, and namely the first buried regions drops under the second buried regions.
4. the two buried regions SOI high-voltage device structure of double window as claimed in claim 1, the vertical range between described front two-layer oxygen buried layer is variable.
5. the two buried regions SOI high-voltage device structure of double window as claimed in claim 1, described ground floor and the articulamentum of third layer are variable to the distance of device left margin.
6. the two buried regions SOI high-voltage device structure of double window as claimed in claim 1, described polysilicon can change other materials into.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410216653.3A CN105097823A (en) | 2014-05-22 | 2014-05-22 | Double-vertical-window three-buried layer SOI high-voltage device structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410216653.3A CN105097823A (en) | 2014-05-22 | 2014-05-22 | Double-vertical-window three-buried layer SOI high-voltage device structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105097823A true CN105097823A (en) | 2015-11-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410216653.3A Pending CN105097823A (en) | 2014-05-22 | 2014-05-22 | Double-vertical-window three-buried layer SOI high-voltage device structure |
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| CN (1) | CN105097823A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7195962B2 (en) * | 2003-06-27 | 2007-03-27 | Electronics And Telecommunications Research Institute | Ultra short channel field effect transistor and method of fabricating the same |
| CN101419911A (en) * | 2007-10-26 | 2009-04-29 | 硅绝缘体技术有限公司 | Substrats SOI avec couche fine isolante enterree |
| CN101621064A (en) * | 2009-08-03 | 2010-01-06 | 中国科学院微电子研究所 | Silicon device on insulator and preparation method thereof |
| CN102130172A (en) * | 2010-12-23 | 2011-07-20 | 上海北京大学微电子研究院 | SOI (silicon-on-insulator) device structure |
-
2014
- 2014-05-22 CN CN201410216653.3A patent/CN105097823A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7195962B2 (en) * | 2003-06-27 | 2007-03-27 | Electronics And Telecommunications Research Institute | Ultra short channel field effect transistor and method of fabricating the same |
| CN101419911A (en) * | 2007-10-26 | 2009-04-29 | 硅绝缘体技术有限公司 | Substrats SOI avec couche fine isolante enterree |
| CN101621064A (en) * | 2009-08-03 | 2010-01-06 | 中国科学院微电子研究所 | Silicon device on insulator and preparation method thereof |
| CN102130172A (en) * | 2010-12-23 | 2011-07-20 | 上海北京大学微电子研究院 | SOI (silicon-on-insulator) device structure |
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Application publication date: 20151125 |
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