CN107369684A - A kind of semiconductor structure and its manufacture method - Google Patents
A kind of semiconductor structure and its manufacture method Download PDFInfo
- Publication number
- CN107369684A CN107369684A CN201710611685.7A CN201710611685A CN107369684A CN 107369684 A CN107369684 A CN 107369684A CN 201710611685 A CN201710611685 A CN 201710611685A CN 107369684 A CN107369684 A CN 107369684A
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- top layer
- type injection
- effect transistor
- injection region
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000002347 injection Methods 0.000 claims abstract description 67
- 239000007924 injection Substances 0.000 claims abstract description 67
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 229920005591 polysilicon Polymers 0.000 claims abstract description 42
- 230000005669 field effect Effects 0.000 claims abstract description 31
- 230000011218 segmentation Effects 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 239000002210 silicon-based material Substances 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 102100035767 Adrenocortical dysplasia protein homolog Human genes 0.000 description 3
- 101000929940 Homo sapiens Adrenocortical dysplasia protein homolog Proteins 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of semiconductor structure and its manufacture method, including polysilicon high-tension resistive and junction field effect transistor, described polysilicon high-tension resistive is integrated on the junction field effect transistor, and the both ends of the polysilicon high-tension resistive connect the N+ injection regions and top layer p-type injection region of the junction field effect transistor respectively；The polysilicon high-tension resistive is helical structure, and spiral is arranged between N+ injection regions and top layer p-type injection region.Polysilicon high-tension resistive is integrated on junction field effect transistor (JFET) by the present invention, and the drift region between the N+ injection regions and top layer p-type injection region of junction field effect transistor has voltage gradient poor, and it is breakdown to avoid oxide layer.Meanwhile polysilicon high-tension resistive is fabricated to helical structure by the present invention, has saved the size of silicon materials.
Description
Technical field
The present invention relates to a kind of technical field of semiconductor device, more particularly to a kind of semiconductor structure and its manufacture method.
Background technology
It is increasingly convex for the demand of reduction high-tension resistive size with the extensive use of high-tension resistive in integrated circuits
It is aobvious.For conventional polysilicon high-tension resistive, in order to reduce polysilicon high-tension resistive with the voltage difference of silicon below, it is necessary to will be more
The both positive and negative polarity of crystal silicon is electrically connected with silicon below respectively so that polysilicon and voltage ladder similar in the holding of silicon below
Degree distribution, and then avoid the breakdown of oxide layer.
In the above prior art, high pressure polysilicon resistance, and acquisition and electricity similar in the holding of silicon below to be made
Gradient distribution is pressed, generally requires the silicon of large-size, cost is higher.
It is by Deep N Well deep N-wells and Deep as shown in figure 1, illustrating the polysilicon high-tension resistive of prior art
PWell depths p-well is electrically connected with the both positive and negative polarity of polysilicon high-tension resistive respectively.As shown in Fig. 2 it is to realize above-mentioned polycrystalline silicon high-voltage
The simple domain of resistance, the polysilicon magnitude of voltage above its Deep N Well deep N-well is big, therefore its N+ injection region is to Deep N
The distance of Well deep N-well surroundings should identical (have enough pressure-resistant), it is necessary to waste compared with many areas.
The content of the invention
In view of this, it is an object of the invention to provide a kind of high semiconductor structure of integrated level and its manufacture method, it is used for
Solves the technical problem that large-size semi-conducting material is needed existing for prior art.
To achieve the above object, the invention provides a kind of semiconductor structure, including polysilicon high-tension resistive and junction type field
Effect transistor, described polysilicon high-tension resistive are integrated on the junction field effect transistor, the polysilicon high-tension electricity
The both ends of resistance connect the N+ injection regions and top layer p-type injection region of the junction field effect transistor respectively.
Optionally, the polysilicon high-tension resistive is helical structure, and spiral is arranged at N+ injection regions and top layer p-type injection region
Between.
Optionally, it is the drift region of junction field effect transistor between the N+ injection regions and top layer p-type injection region, it is described
Polysilicon high-tension resistive is positive pole close to one end of N+ injection regions, and one end close to top layer p-type injection region is negative pole.
Optionally, the lower section of the top layer p-type injection region is the raceway groove of junction field effect transistor.
Optionally, the top layer p-type injection region includes non-segment identifier and segment identifier, and described segment identifier is positioned at described overstepping one's bounds
The inner side in section area, the non-segment identifier lower section are the raceway groove of junction field effect transistor, are pressure-resistant drift region below segment identifier.
Optionally, the top layer p-type injection region is the complete area positioned at deep N-well top, and the bottom of the deep N-well is set
There are subsection part and non-subsection part, described subsection part is located at the outside of the non-subsection part, and the top of described subsection part is corresponding
The Outboard Sections of the top layer p-type injection region, the junction depth of subsection part are more shallow than the junction depth of non-subsection part.
The present invention also provides a kind of manufacture method of semiconductor structure, comprises the following steps：
Polysilicon high-tension resistive is integrated on junction field effect transistor, the both ends difference of the polysilicon high-tension resistive
Connect the N+ injection regions and top layer p-type injection region of the junction field effect transistor；
The polysilicon high-tension resistive is helical structure, is arranged between N+ injection regions and top layer p-type injection region.
Optionally, it is the drift region of junction field effect transistor between the N+ injection regions and top layer p-type injection region, it is described
Polysilicon high-tension resistive is positive pole close to one end of N+ injection regions, and one end close to top layer p-type injection region is negative pole.
The top layer p-type injection region includes non-segment identifier and segment identifier, and described segment identifier is located at the non-segment identifier
Inner side, the non-segment identifier lower section are the raceway groove of junction field effect transistor, are pressure-resistant drift region below segment identifier.
The top layer p-type injection region is the complete area positioned at deep N-well top, and the bottom of the deep N-well is provided with segmentation
Portion and non-subsection part, described subsection part are located at the outside of the non-subsection part, and the top of described subsection part corresponds to the top
The Outboard Sections of layer p-type injection region, the junction depth of subsection part are more shallow than the junction depth of non-subsection part.
Compared with prior art, the technical scheme of the present invention has advantages below：The present invention is by polysilicon high-tension resistive collection
Into on junction field effect transistor (JFET), the drift between the N+ injection regions and Ptop injection regions of junction field effect transistor
Area has voltage gradient poor, and it is breakdown to avoid oxide layer.Meanwhile polysilicon high-tension resistive is fabricated to spiral knot by the present invention
Structure, the size of silicon materials is saved.
Brief description of the drawings
Fig. 1 is the structural representation of prior art polysilicon high-tension resistive；
Fig. 2 is the circuit layout of prior art polysilicon high-tension resistive；
Fig. 3 is the structural representation of junction field effect transistor；
Fig. 4 is the circuit layout of junction field effect transistor；
Fig. 5 is the circuit layout of polysilicon high-tension resistive of the present invention；
Fig. 6 is the schematic structural view of the invention with special top layer p-type injection region；
Fig. 7 is the schematic structural view of the invention with special deep N-well.
Embodiment
The preferred embodiments of the present invention are described in detail below in conjunction with accompanying drawing, but the present invention is not restricted to these
Embodiment.The present invention covers any replacement made in the spirit and scope of the present invention, modification, equivalent method and scheme.
Thoroughly understand in order that the public has to the present invention, be described in detail in present invention below preferred embodiment specific
Details, and description without these details can also understand the present invention completely for a person skilled in the art.
More specifically description is of the invention by way of example referring to the drawings in the following passage.It should be noted that accompanying drawing is adopted
Non- accurately ratio is used with more simplified form and, only to convenience, lucidly aid in illustrating the embodiment of the present invention
Purpose.
As shown in figure 3, illustrating the concrete structure of junction field effect transistor, the N+ that positive pole is connected in JFET structures is utilized
The voltage gradient of drift region between injection region and top layer p-type injection region Ptop is poor, realizes the integrated of polysilicon high-tension resistive.
As shown in figure 4, illustrate the simple domain of junction field effect transistor (JFET) structure.Spiral is utilized in drift region
Structure design polysilicon high-tension resistive, the termination of N+ injection regions is will be close to as positive pole, will be close to and top layer p-type injection region Ptop
Termination as negative pole.
As shown in figure 5, illustrate the integrated polysilicon high-tension resistives of JFET.The polysilicon high-tension resistive is spiral knot
Structure, spiral are arranged between N+ injection regions and top layer p-type injection region.The lower section of the top layer p-type injection region is junction field
The raceway groove of transistor.In order to lift the breakdown voltage of raceway groove, top layer p-type can be injected and divide into segment identifier and non-segment identifier,
Or deep N-well is arranged to subsection part and non-subsection part.Fig. 6 and 7 are shown in drawings in detail and introduction respectively.
As shown in fig. 6, the polysilicon high-tension resistive with special top layer p-type injection region is illustrated, in above example knot
On the basis of structure, top layer p-type injection region is arranged to special structure, the top layer p-type injection region is including segment identifier and presumptuously
Section area, described segment identifier are located at the inner side of the non-segment identifier, are junction field effect transistor below the non-segment identifier
Raceway groove, segment identifier lower section is pressure-resistant drift region.Using the structure, can improve raceway groove breakdown voltage and drift region it is pressure-resistant
Value.
As shown in fig. 7, the polysilicon high-tension resistive with special deep N-well is illustrated, on the basis of above example structure
On, deep N-well deep N well are arranged to special structure, the deep N-well deep Nwell inject including the top layer p-type
Area is the complete area positioned at deep N-well top, and described complete area refers to without segmentation, and its width and area are more existing
There is technology big.The bottom of the deep N-well is provided with subsection part and non-subsection part, and described subsection part is located at the non-subsection part
Outside, the top of described subsection part corresponds to the Outboard Sections of the top layer p-type injection region, and the junction depth of subsection part is than non-segmentation
The junction depth in portion is shallow.It is identical with the effect of Fig. 7 schemes, you can to improve the pressure voltage of the breakdown voltage of raceway groove and drift region.
For the purpose of clarity, Fig. 6 and Fig. 7 do not illustrate high-tension resistive, but those of ordinary skill in the art can be according to this
The word description of specification, it can directly and unambiguously understand technical scheme.It is understood that Fig. 6 and
Fig. 7 is the further improvement on the basis of high-tension resistive is integrated on JFET.
Although embodiment is separately illustrated and illustrated above, it is related to the common technology in part, in ordinary skill
Personnel apparently, can be replaced and integrate between the embodiments, be related to one of embodiment and the content recorded is not known, then
Refer to another embodiment on the books.
Embodiments described above, the restriction to the technical scheme protection domain is not formed.It is any in above-mentioned implementation
Modifications, equivalent substitutions and improvements made within the spirit and principle of mode etc., should be included in the protection model of the technical scheme
Within enclosing.
Claims (10)
1. a kind of semiconductor structure, including polysilicon high-tension resistive and junction field effect transistor, described polysilicon high-tension electricity
Resistance is integrated on the junction field effect transistor, and the both ends of the polysilicon high-tension resistive connect the junction field respectively
The N+ injection regions and top layer p-type injection region of transistor.
2. semiconductor structure according to claim 1, it is characterised in that：The polysilicon high-tension resistive is helical structure,
Spiral is arranged between N+ injection regions and top layer p-type injection region.
3. semiconductor structure according to claim 2, it is characterised in that：The N+ injection regions and top layer p-type injection region it
Between be junction field effect transistor drift region, the polysilicon high-tension resistive is positive pole close to one end of N+ injection regions, close
One end of top layer p-type injection region is negative pole.
4. according to the semiconductor structure described in claim 1,2 or 3, it is characterised in that：The lower section of the top layer p-type injection region is
The raceway groove of junction field effect transistor.
5. semiconductor structure according to claim 4, it is characterised in that：The top layer p-type injection region includes non-segment identifier
And segment identifier, described segment identifier are located at the inner side of the non-segment identifier, are junction field effect transistor below the non-segment identifier
The raceway groove of pipe, segment identifier lower section is pressure-resistant drift region.
6. semiconductor structure according to claim 4, it is characterised in that：The top layer p-type injection region is in deep N-well
The complete area in portion, the bottom of the deep N-well are provided with subsection part and non-subsection part, and described subsection part is located at the non-segmentation
The outside in portion, the top of described subsection part correspond to the Outboard Sections of the top layer p-type injection region, and the junction depth of subsection part is than overstepping one's bounds
The junction depth in section portion is shallow.
A kind of 7. manufacture method of semiconductor structure, it is characterised in that：Comprise the following steps：
Polysilicon high-tension resistive is integrated on junction field effect transistor, the both ends of the polysilicon high-tension resistive connect respectively
The N+ injection regions and top layer p-type injection region of the junction field effect transistor；
The polysilicon high-tension resistive is helical structure, and spiral is arranged between N+ injection regions and top layer p-type injection region.
8. the manufacture method of semiconductor structure according to claim 7, it is characterised in that：The N+ injection regions and top layer P
It is the drift region of junction field effect transistor between type injection region, the polysilicon high-tension resistive is close to one end of N+ injection regions
Positive pole, one end close to top layer p-type injection region is negative pole.
9. the manufacture method of the semiconductor structure according to claim 7 or 8, it is characterised in that：The top layer p-type injection region
Including non-segment identifier and segment identifier, described segment identifier is located at the inner side of the non-segment identifier, is knot below the non-segment identifier
The raceway groove of type field-effect transistor, segment identifier lower section is pressure-resistant drift region.
10. the manufacture method of the semiconductor structure according to claim 7 or 8, it is characterised in that：The top layer p-type injection
Area is the complete area positioned at deep N-well top, and the bottom of the deep N-well is provided with subsection part and non-subsection part, described segmentation
Portion is located at the outside of the non-subsection part, and the top of described subsection part corresponds to the Outboard Sections of the top layer p-type injection region, point
The junction depth in section portion is more shallow than the junction depth of non-subsection part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710611685.7A CN107369684B (en) | 2017-07-25 | 2017-07-25 | Semiconductor structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710611685.7A CN107369684B (en) | 2017-07-25 | 2017-07-25 | Semiconductor structure and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN107369684A true CN107369684A (en) | 2017-11-21 |
| CN107369684B CN107369684B (en) | 2020-06-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710611685.7A Active CN107369684B (en) | 2017-07-25 | 2017-07-25 | Semiconductor structure and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151620A (en) * | 2020-10-27 | 2020-12-29 | 杰华特微电子（杭州）有限公司 | Junction field effect transistor with ESD protection structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104167435A (en) * | 2014-08-08 | 2014-11-26 | 无锡市晶源微电子有限公司 | On-chip high-voltage resistor with voltage dividing ring structure |
| CN104299993A (en) * | 2013-04-25 | 2015-01-21 | 成都芯源系统有限公司 | High voltage field effect transistor device |
-
2017
- 2017-07-25 CN CN201710611685.7A patent/CN107369684B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104299993A (en) * | 2013-04-25 | 2015-01-21 | 成都芯源系统有限公司 | High voltage field effect transistor device |
| CN104167435A (en) * | 2014-08-08 | 2014-11-26 | 无锡市晶源微电子有限公司 | On-chip high-voltage resistor with voltage dividing ring structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151620A (en) * | 2020-10-27 | 2020-12-29 | 杰华特微电子（杭州）有限公司 | Junction field effect transistor with ESD protection structure |
| CN112151620B (en) * | 2020-10-27 | 2022-07-19 | 杰华特微电子股份有限公司 | Junction field effect transistor with ESD protection structure |
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| Publication number | Publication date |
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| CN107369684B (en) | 2020-06-26 |
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Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030 Patentee after: Jiehuate Microelectronics Co.,Ltd. Address before: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030 Patentee before: JOULWATT TECHNOLOGY (HANGZHOU) Co.,Ltd. |
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