CN206490062U - Single programmable read-only storage based on CMOS technology - Google Patents
Single programmable read-only storage based on CMOS technology Download PDFInfo
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- CN206490062U CN206490062U CN201720138918.1U CN201720138918U CN206490062U CN 206490062 U CN206490062 U CN 206490062U CN 201720138918 U CN201720138918 U CN 201720138918U CN 206490062 U CN206490062 U CN 206490062U
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- memory device
- storage
- cmos technology
- programmable read
- single programmable
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Abstract
The utility model discloses a kind of single programmable read-only storage based on CMOS technology, due to being connected with differential pressure generator part between selecting pipe and memory device, it regard the pressure drop on differential pressure generator part as memory device body end and the voltage difference of source, it is used as floating gate PMOS body end and the source no longer equipotential of memory device, and body end current potential is higher than source, and another scheme is then to be parallel with electric capacity between floating gate PMOS grid end and source.In the case where PMOS floating booms do not store electric charge, the electric leakage under reduction logical zero state, without increasing technological process, saves cost.
Description
Technical field
The utility model is related to technical field of electronic devices, and in particular to a kind of single programmable based on CMOS technology is only
Read memory.
Background technology
In the prior art, a kind of common single programmable read-only storage (OTP EPROM) based on CMOS technology is set
Meter is as basic unit of storage with floating-gate device (NMOS or PMOS).Its operation principle is：Floating boom does not store electric charge, device initially
Part is obstructed, is logical zero state；Floating boom is allowed to store electric charge, device by programming (gate current such as produced with hot carrier in jection)
Conducting, is the state of logic 1.Because PMOS is for NMOS, the gate current of hot carrier in jection is easily produced, it is easy to program,
More commonly used so making memory cell of floating gate PMOS, it is easy to accomplish.If without using floating gate PMOS, but made of floating boom NMOS
Memory cell, then need to improve program voltage.By taking 5V CMOS technologies as an example：Floating gate PMOS program voltage is about 7-8V, and is floated
Grid NMOS program voltages are about 12V.
But in the CMOS technology of PMOS with buried channel is employed, as shown in figure 1, the body end of floating gate PMOS and the same current potential of source,
In such cases, even if PMOS floating boom does not store electric charge (logical zero state) initially, its initial electric leakage it is also larger (at room temperature for>
NA grades/um is wide), easily it is mistaken for turning on (state of logic 1).Common practice is independently added for the floating gate PMOS
One Channeling implantation, or stop the p-type injection of buried channel, to obtain relatively low electric leakage to avoid erroneous judgement, but which is added
Technological process, and poor controllability, cost are higher.
Utility model content
In view of this, the utility model provides a kind of single programmable read-only storage based on CMOS technology, not
The electrical leakage problems of floating boom are solved in the case of increasing technique, the technical problem to solve prior art presence, to reduce work
Skill cost, improves reliability.
Technical solution of the present utility model is to provide a kind of single programmable based on CMOS technology of following structure
Read-only storage, including selecting pipe and memory device, described selecting pipe are connected with memory device, the other end of the selecting pipe
As the anode connection terminal of read-only storage, the other end of the memory device as read-only storage negative pole connection end, and
It is provided with the end and sentences threshold currents source；Differential pressure generator part, the pressure difference are connected between described selecting pipe and memory device
The pressure drop produced on device is used as memory device body end and the voltage difference of source.
Alternatively, described differential pressure generator part at least includes a metal-oxide-semiconductor, and the grid of described metal-oxide-semiconductor is short with draining
Connect.
Alternatively, described differential pressure generator part also includes a controllable current source, and the two ends of the controllable current source connect
It is connected on the grid end of the metal-oxide-semiconductor and the negative pole connection end of read-only storage.
Alternatively, described differential pressure generator part includes the PMOS of multiple series connection or the NMOS tube of multiple series connection.
Alternatively, the pressure drop on the differential pressure generator part is between 0.6~1.2V.
Alternatively, described selecting pipe is the first PMOS, and described memory device is floating gate PMOS pipe, the floating boom
The body end of PMOS is connected with the anode connection terminal of the read-only storage.
Another technical solution of the present utility model is to provide a kind of read-only storage of the single programmable of following structure
Device, including selecting pipe and memory device, described selecting pipe are connected with memory device, and the other end of the selecting pipe is as read-only
The anode connection terminal of memory, the other end of the memory device as read-only storage negative pole connection end, and on the end
Provided with sentencing threshold currents source；Electric capacity is parallel between the grid end and source of described memory device.
Alternatively, the capacitor size is increased, can be further in the case where the floating boom of floating gate PMOS pipe does not store electric charge
Reduce its electric leakage.
Alternatively, described electric capacity is PIP capacitor, and described PIP capacitor is made up of following steps：The shape in P type substrate
Into place oxide layer, the first polysilicon layer is deposited in the place oxide layer, oxidation is formed on first polysilicon layer
Separation layer, deposits the second polysilicon layer in described oxidization isolation layer.
Alternatively, the length of the first described polysilicon layer is more than second polysilicon layer.In order to the extraction of electrode.
Using structure of the present utility model, compared with prior art, with advantages below：In the utility model, due to choosing
Select and differential pressure generator part be connected between pipe and memory device, using the pressure drop on differential pressure generator part as memory device body end with
The voltage difference of source, as floating gate PMOS body end and the source no longer equipotential of memory device, and body end current potential is higher than source,
Another scheme is then to be parallel with electric capacity between floating gate PMOS grid end and source.The situation of electric charge is not stored in PMOS floating booms
Under, the electric leakage under reduction logical zero state, without increasing technological process, saves cost.
Brief description of the drawings
Fig. 1 is the structural representation of the single programmable read-only storage based on CMOS technology in the prior art；
Fig. 2 is the structural representation of the single programmable read-only storage embodiment one based on CMOS technology in the utility model
Figure；
Fig. 3 is the structural representation of the single programmable read-only storage embodiment two based on CMOS technology in the utility model
Figure；
Electric leakages and the relation schematic diagram of the pressure difference of body end/source of the Fig. 4 for memory device；
Fig. 5 is the structural representation of the single programmable read-only storage embodiment three based on CMOS technology in the utility model
Figure；
Fig. 6 is the electric leakage of memory device and the relation of capacitor size；
Fig. 7 is the schematic diagram of PIP capacitor making step in the utility model.
Shown in figure：1st, selecting pipe, 1.1, selecting pipe control gate, 2, memory device, 2.1, floating boom, 3, sentence threshold currents source,
4th, differential pressure generator part, 5, controllable current source, 6, electric capacity.
Embodiment
Preferred embodiment of the present utility model is described in detail below in conjunction with accompanying drawing, but the utility model is not merely
It is limited to these embodiments.The utility model covers any replacement made in spirit and scope of the present utility model, modification, equivalent
Method and scheme.
Thoroughly understand in order that the public has to the utility model, in following the utility model preferred embodiment specifically
Understand concrete details, and description without these details can also understand that this practicality is new completely for a person skilled in the art
Type.
The utility model is more specifically described by way of example referring to the drawings in the following passage.It should be noted that, accompanying drawing
Use using more simplified form and non-accurately ratio, only to it is convenient, lucidly aid in illustrating the utility model
The purpose of embodiment.
With reference to shown in Fig. 2, single programmable read-only storage embodiment of the utility model based on CMOS technology is illustrated
One structure.The utility model includes selecting pipe 1 and memory device 2, and described selecting pipe 1 is connected with memory device 2, the choosing
The other end for selecting pipe 1 (is marked as the anode connection terminal of read-only storage in figure：Positive electrode), the memory device 2 it is another
Hold and (marked as the negative pole connection end of read-only storage in figure：Negative electrode), and provided with sentencing threshold currents source 3 on the end, according to
It is described to sentence the progress read operation of threshold currents source 3, with the state of decision logic 0 or 1.
It is connected between described selecting pipe 1 and memory device 2 on differential pressure generator part 4, the differential pressure generator part 4
Pressure drop is used as the body end of memory device 2 and the voltage difference of source.Described differential pressure generator part is described using a PMOS
The grid of PMOS and drain electrode short circuit, i.e. diode-connected, it would however also be possible to employ the PMOS of multiple series connection or multiple series connection
NMOS tube is realized.Described selecting pipe is the first PMOS, and described memory device is floating gate PMOS pipe, the floating gate PMOS
The body end of pipe is connected with the anode connection terminal of the read-only storage.Pressure drop on the differential pressure generator part is in 0.6~1.2V
Between, preferred 1V in the present embodiment.
Using the PMOS with buried channel of existing floating boom as memory cell, without increasing processing step, by sentencing threshold currents source 3
When reading floating gate PMOS electric current, keeping body terminal potential is higher than source 1V or so.This connected mode, because being used as the back of the body using body end
Grid (back gate) and produce bulk effect (body effect) improve threshold voltage, so as to reduce electric leakage.
With reference to shown in Fig. 3, single programmable read-only storage embodiment of the utility model based on CMOS technology is illustrated
Two structure.Embodiment two is the improvement carried out on the basis of embodiment one, and the main distinction is that differential pressure generator part is done
It is further to improve.
Described differential pressure generator part includes a controllable current source 5 and at least one metal-oxide-semiconductor, by the controllable current source
Two ends be connected to the grid end of the metal-oxide-semiconductor and the negative pole connection end of read-only storage.Although illustrate only a PMOS in figure
Pipe, can also be real still, as embodiment one, it would however also be possible to employ the PMOS of multiple series connection or the NMOS tube of multiple series connection
It is existing.The size of controllable current source 5 is controlled according to control signal, so as to adjust the pressure drop of whole differential pressure generator part.
With reference to shown in Fig. 4, the relation of the electric leakage of memory device and the pressure difference of body end/source is illustrated.As shown in Figure 4, float
The electric leakage of grid PMOS reduces with the increase of the pressure difference of body end/source, and preferably effect is obtained in 1V or so.
With reference to shown in Fig. 5, single programmable read-only storage embodiment of the utility model based on CMOS technology is illustrated
Three structure.Device is increased by the grid end in memory device and source, i.e., described memory device grid end and source it
Between be parallel with electric capacity 6.In the case where the floating boom of floating gate PMOS pipe does not store electric charge, electric capacity 6 can reduce the electric leakage of floating boom.It is floating
The grid end voltage of grid PMOS is together decided on by the pipe drain terminal, source voltage terminal, and is increased between grid end and source after electric capacity,
So that the pipe grid end voltage improve grid end voltage, so as to reduce electric leakage closer to source.
With reference to shown in Fig. 6, the manufacturing process of PIP capacitor in the utility model is illustrated.It will be appreciated from fig. 6 that with the electricity
Hold the increase of 6 sizes, capacitor size increase means that its capacitance accordingly increases, electric charge is not stored in the floating boom of floating gate PMOS pipe
In the case of, it can further reduce floating boom electric leakage.
With reference to shown in Fig. 7, described electric capacity is PIP capacitor, and described PIP capacitor is made up of following steps：In P type substrate
Upper formation place oxide layer, the first polysilicon layer is deposited in the place oxide layer, is formed on first polysilicon layer
Oxidization isolation layer, deposits the second polysilicon layer in described oxidization isolation layer.And the length of the first described polysilicon layer is big
In second polysilicon layer, in order to the extraction of electrode.
In addition, although embodiment is separately illustrated and illustrated above, but it is related to the common technology in part, in this area
Those of ordinary skill apparently, can be replaced and integrate between the embodiments, be related to one of embodiment and record is not known
Content, then refer to another embodiment on the books.
Embodiments described above, does not constitute the restriction to the technical scheme protection domain.It is any in above-mentioned implementation
Modifications, equivalent substitutions and improvements made within the spirit and principle of mode etc., should be included in the protection model of the technical scheme
Within enclosing.
Claims (10)
1. a kind of single programmable read-only storage based on CMOS technology, including selecting pipe and memory device, described selection
Pipe is connected with memory device, the other end of the selecting pipe as read-only storage anode connection terminal, the memory device
The other end as read-only storage negative pole connection end, and provided with sentencing threshold currents source on the end；It is characterized in that：
The pressure drop conduct on differential pressure generator part, the differential pressure generator part is connected between described selecting pipe and memory device
The voltage difference of memory device body end and source.
2. the single programmable read-only storage according to claim 1 based on CMOS technology, it is characterised in that：Described
Differential pressure generator part at least includes metal-oxide-semiconductor, the grid and drain electrode short circuit of described metal-oxide-semiconductor.
3. the single programmable read-only storage according to claim 2 based on CMOS technology, it is characterised in that：Described
Differential pressure generator part also includes controllable current source, the two ends of the controllable current source be connected to the metal-oxide-semiconductor grid end and
The negative pole connection end of read-only storage.
4. the single programmable read-only storage according to claim 2 based on CMOS technology, it is characterised in that：Described
Differential pressure generator part includes the PMOS of multiple series connection or the NMOS tube of multiple series connection.
5. the single programmable read-only storage based on CMOS technology according to Claims 2 or 3, it is characterised in that：Institute
The pressure drop on differential pressure generator part is stated between 0.6~1.2V.
6. the single programmable read-only storage based on CMOS technology according to claim 1-4 any one, its feature
It is：Described selecting pipe is the first PMOS, and described memory device is floating gate PMOS pipe, the body end of the floating gate PMOS pipe
It is connected with the anode connection terminal of the read-only storage.
7. a kind of single programmable read-only storage based on CMOS technology, including selecting pipe and memory device, described selection
Pipe is connected with memory device, the other end of the selecting pipe as read-only storage anode connection terminal, the memory device
The other end as read-only storage negative pole connection end, and provided with sentencing threshold currents source on the end；It is characterized in that：
Electric capacity is parallel between the grid end and source of described memory device.
8. the single programmable read-only storage according to claim 7 based on CMOS technology, it is characterised in that：Increase institute
Capacitor size is stated, in the case where the floating boom of floating gate PMOS pipe does not store electric charge, its electric leakage can be further reduced.
9. the single programmable read-only storage according to claim 8 based on CMOS technology, it is characterised in that：Described
Electric capacity is PIP capacitor, and described PIP capacitor is made up of following steps：Place oxide layer is formed in P type substrate, in the field
The first polysilicon layer is deposited in area's oxide layer, oxidization isolation layer is formed on first polysilicon layer, described oxidation every
The second polysilicon layer is deposited on absciss layer.
10. the single programmable read-only storage according to claim 9 based on CMOS technology, it is characterised in that：It is described
The first polysilicon layer length be more than second polysilicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201720138918.1U CN206490062U (en) | 2017-02-16 | 2017-02-16 | Single programmable read-only storage based on CMOS technology |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720138918.1U CN206490062U (en) | 2017-02-16 | 2017-02-16 | Single programmable read-only storage based on CMOS technology |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783868A (en) * | 2017-02-16 | 2017-05-31 | 杰华特微电子（张家港）有限公司 | Single programmable read-only storage based on CMOS technology |
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2017
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783868A (en) * | 2017-02-16 | 2017-05-31 | 杰华特微电子（张家港）有限公司 | Single programmable read-only storage based on CMOS technology |
| CN109326603A (en) * | 2017-02-16 | 2019-02-12 | 杰华特微电子（张家港）有限公司 | A kind of single programmable read-only memory based on CMOS technology |
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| GR01 | Patent grant | ||
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| AV01 | Patent right actively abandoned |
Granted publication date: 20170912 Effective date of abandoning: 20190716 |