CN102646709B

CN102646709B - Rapid super junction vertical double-diffused metal-oxide semiconductor field-effect transistor

Info

Publication number: CN102646709B
Application number: CN201210101011.XA
Authority: CN
Inventors: 孙伟锋; 祝靖; 张龙; 吴逸凡; 钱钦松; 陆生礼; 时龙兴
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2012-04-06
Filing date: 2012-04-06
Publication date: 2014-06-11
Anticipated expiration: 2032-04-06
Also published as: CN102646709A

Abstract

The invention relates to a rapid super junction vertical double-diffused metal-oxide semiconductor field-effect transistor, which comprises an N-type doped silicon substrate which is also used as a drain region, an N-type doped silicon epitaxial layer and a super junction structure. The N-type doped silicon epitaxial layer is arranged on the N-type doped silicon substrate. The super junction structure is arranged in an N-type silicon doped semiconductor region. The super junction structure consists of P-type pillars and N-type pillars which are arranged at intervals. A first P-type doped semiconductor region is formed on each P-type pillar and is arranged in the N-type doped silicon epitaxial layer. A second P-type highly-doped semiconductor contact region and an N-type highly-doped semiconductor source region are arranged in the first P-type doped semiconductor region. The rapid super junction vertical double-diffused metal-oxide semiconductor field-effect transistor is characterized in that a source buried layer is arranged on the surface of each N-type pillar, the source buried layer comprises a thin oxidation layer and polycrystalline silicon on the thin oxidation layer and a polycrystalline silicon gate is connected with source metal.

Description

A kind of rapid superjunction

Technical field

The invention belongs to semiconductor power device technology field, relate to the silicon high voltage power device processed of high-speed switch, be specially adapted to silicon ultra-junction longitudinal bilateral diffusion metal oxide processed field-effect transistor (Superjunction VDMOS, it is hyperconjugation VDMOS, all be abbreviated as hyperconjugation VDMOS once), in particular, relate to a kind of can high-speed switch, the structure of the silicon hyperconjugation VDMOS processed of ultra-low loss.

Background technology

At present, power device is more and more extensive in the application in the field such as daily life, production, particularly power metal oxide semiconductor field-effect transistor, because they have switching speed, less drive current, wider safety operation area faster, be therefore subject to numerous researchers' favor.Nowadays, power device is just towards improving operating voltage, increase operating current, reduce conducting resistance, accelerating switching speed and integrated future development.In numerous power metal oxide semiconductor field-effect transistor devices, especially in longitudinal power metal oxide semiconductor field-effect transistor, the invention of super pn junction p n power device, it overcomes the contradiction between conventional power metal oxide semiconductor field effect tube conducting resistance and puncture voltage, change conventional power device and relied on the withstand voltage structure of drift layer, but adopted a kind of " super-junction structure "---form that P type, N-type silicon semiconductor material are arranged alternately with each other in drift region.This Structure Improvement puncture voltage and conducting resistance be difficult for situation about simultaneously taking into account, in the time of off-state, because the depletion region electric field in P type post and N-type post produces mutual compensating effect, the doping content that makes P type post and N-type post can be done very highly and can not cause the decline of device electric breakdown strength.When conducting, the conducting resistance of the doping device of this high concentration obviously reduces.Due to this unique device structure of ultra-junction longitudinal double-diffusion metal-oxide-semiconductor field effect transistor, make its electrical property obviously be better than conventional power mos field effect transistor, therefore this technology is called the technical milestone of power metal oxide semiconductor field-effect transistor by people.

Power device not only gains great popularity in sophisticated technology fields such as national defence, space flight, aviations, and in industry, the fields such as civilian household electrical appliances are too by people are paid attention to.Growing along with power device, its reliability has also become the focus of people's common concern.Power device provides driving for electronic equipment provides the power supply of desired form and motor device, and almost all electronic equipments and motor device all need to use power device, so the research of device reliability is had to vital meaning.

The definition of reliability be product under defined terms and in official hour, complete the ability of predetermined function.So-called defined terms, mainly refers to use conditions and environment condition.Service condition refers to that those are by the stress condition that enters into product or material internal and work, as electric stress, chemical stress and physical stress.The scope of reliability test is very extensive, its objective is in order to examine the electronic products such as electronic devices and components may run into machinery, the environmental condition of various complexity in storage, transportation and the course of work.

But, in tradition ultra-junction longitudinal bilateral diffusion metal oxide semiconductor tube, because the concentration of drift region is far away higher than vertical double-diffused MOS field-effect transistor, make its grid parasitic capacitance very high, in devices switch process, affect switching speed and switching loss.

In addition, in traditional vertical double-diffused MOS field effect transistor, because switching speed is very fast, in the quick changes in voltage at the drain-source two ends of device, drain-source electric capacity produces very large drift current, flows through P type doped region, cause the conducting of device parasitic triode, component failure.

Summary of the invention

The invention provides a kind of rapid superjunction, related structure can reduce grid parasitic capacitance, and the switching speed of faster devices reduces the loss of devices switch process, and the unlatching of energy suppression device endoparasitism triode, the reliability of raising device.

The invention provides following technical scheme:

A kind of rapid superjunction, comprise: the double N-type doped silicon substrate of doing drain region, N-type doped epitaxial silicon layer, super-junction structure, described N-type doped epitaxial silicon layer is located in N-type doped silicon substrate, super-junction structure is located on N-type silicon doping semiconductor region, described super-junction structure is made up of spaced P type post and N-type post, on P type post, there is a P type doped semiconductor area, and a P type doped semiconductor area is positioned at N-type doped epitaxial layer, in a P type doped semiconductor area, be provided with the 2nd P type heavily-doped semiconductor contact zone and N-type heavily-doped semiconductor source region, above N-type post, be provided with gate oxide, above gate oxide, be provided with polysilicon gate, on polysilicon gate, be provided with the first type oxide layer, on the 2nd P type heavily-doped semiconductor contact zone and N-type heavily-doped semiconductor source region, be connected with source metal, at N-type post surfaced active utmost point buried regions, source electrode buried regions comprises the polysilicon on thin oxide layer and thin oxide layer, polysilicon gate is connected with source metal.

Compared with prior art, tool of the present invention has the following advantages:

1, structure of the present invention is provided with source electrode buried regions on traditional super-junction structure N-type post surface, and source electrode buried regions is positioned at grid oxic horizon below, and the oxide layer of source electrode buried regions makes polysilicon and the isolation of N-type post wherein, and the polysilicon in source electrode buried regions is connected with source metal.The structure of source electrode buried regions can make the parasitic capacitance of grid reduce, and has accelerated the switching speed of device, has reduced the switching loss of device.

2, structure of the present invention provides a current path for the charging of device endoparasitism electric capacity, the displacement current that the variation of drain electrode and source voltage causes in turn off process is understood some and is flow through source electrode buried regions, thereby reduce to flow through the electric current of P type doped region, make the more difficult unlatching of device endoparasitism triode, strengthened the reliability of device.

Accompanying drawing explanation

Fig. 1 is the structural representation of the related a kind of rapid superjunction of content of the present invention.

Fig. 2 is the structural representation of traditional ultra-junction longitudinal bilateral diffusion metal oxide semiconductor tube.

Fig. 3 is the displacement current path schematic diagram of the related a kind of rapid superjunction of content of the present invention.

Fig. 4 is the displacement current path schematic diagram of traditional ultra-junction longitudinal double-diffused metal oxide semiconductor.

Embodiment

A kind of rapid superjunction, comprise: the double N-type doped silicon substrate 1 of doing drain region, N-type doped epitaxial silicon layer 2, super-junction structure 3, described N-type doped epitaxial silicon layer 2 is located in N-type doped silicon substrate 1, super-junction structure 3 is located on N-type silicon doping semiconductor region 2, described super-junction structure 3 is made up of spaced P type post 4 and N-type post 5, on P type post, there is a P type doped semiconductor area 6, and a P type doped semiconductor area 6 is positioned at N-type doped epitaxial layer 2, in a P type doped semiconductor area 6, be provided with the 2nd P type heavily-doped semiconductor contact zone 8 and N-type heavily-doped semiconductor source region 7, above N-type post 5, be provided with gate oxide 9, above gate oxide 9, be provided with polysilicon gate 10, on polysilicon gate 10, be provided with the first type oxide layer 11, on the 2nd P type heavily-doped semiconductor contact zone 8 and N-type heavily-doped semiconductor source region 7, be connected with source metal 12, at N-type post surfaced active utmost point buried regions 13, source electrode buried regions 13 comprises the polysilicon 15 on thin oxide layer 14 and thin oxide layer, polysilicon gate 15 is connected with source metal 12.

The width of source electrode buried regions is changeable, depend on the size of drain-source electric capacity and gate leakage capacitance, the thickness of thin oxide layer can regulate, depend on the size of drain-source electric capacity, the thickness of the grid oxic horizon on polysilicon can regulate, depend on the size of grid source electric capacity, in the present embodiment, the width of source electrode buried regions is 10 nanometer～50 micron, the thickness of thin oxide layer 14 is 1 nanometer～5 micron, the thickness of the grid oxic horizon on polysilicon is 1 nanometer～5 micron, width 10 nanometer～50 micron of the grid oxic horizon on polysilicon.

With reference to the accompanying drawings, the specific embodiment of the present invention is made to more detailed explanation:

Fig. 1 is the structural representation of a kind of rapid superjunction that the present invention relates to, and wherein source electrode buried regions is arranged in the N-type epitaxial loayer of grid below.

Fig. 3 is the flow direction of a kind of rapid superjunction structure that the present invention relates to displacement current in the time turn-offing, can see that thereby one part of current has flowed to source electrode buried regions and reduced to flow to the electric current of parasitic triode, has stoped parasitic triode unlatching.

With reference to Fig. 4, the base of traditional ultra-junction longitudinal bilateral diffusion metal oxide semiconductor tube knot whole parasitic triodes of flowing through of displacement current in the time turn-offing, the risk that parasitic triode is opened is larger.

Claims

1. a rapid superjunction, comprise: the double N-type doped silicon substrate (1) of doing drain region, N-type doped epitaxial silicon layer (2), super-junction structure (3), described N-type doped epitaxial silicon layer (2) is located in N-type doped silicon substrate (1), super-junction structure (3) is located on N-type silicon doping semiconductor region (2), described super-junction structure (3) is made up of spaced P type post (4) and N-type post (5), on P type post, there is a P type doped semiconductor area (6), and a P type doped semiconductor area (6) is positioned at N-type doped epitaxial layer (2), in a P type doped semiconductor area (6), be provided with the 2nd P type heavily-doped semiconductor contact zone (8) and N-type heavily-doped semiconductor source region (7), be provided with gate oxide (9) in N-type post (5) top, be provided with polysilicon gate (10) in gate oxide (9) top, on polysilicon gate (10), be provided with the first type oxide layer (11), on the 2nd P type heavily-doped semiconductor contact zone (8) and N-type heavily-doped semiconductor source region (7), be connected with source metal (12), it is characterized in that, at N-type post surfaced active utmost point buried regions (13), source electrode buried regions (13) comprises the polysilicon (15) on thin oxide layer (14) and thin oxide layer, polysilicon (15) is connected with source metal (12), source electrode buried regions (13) is positioned at gate oxide (9) below, the thin oxide layer of source electrode buried regions makes polysilicon and the isolation of N-type post wherein, polysilicon in source electrode buried regions is connected with source metal.

2. rapid superjunction according to claim 1, is characterized in that, the width of source electrode buried regions (10) is 10 nanometer～50 micron.

3. rapid superjunction according to claim 1, is characterized in that, the thickness of thin oxide layer (14) is 1 nanometer～5 micron.

4. rapid superjunction according to claim 1, is characterized in that, the thickness of the grid oxic horizon on polysilicon (15) is 1 nanometer～5 micron.

5. rapid superjunction according to claim 1, is characterized in that, width 10 nanometer～50 micron of the grid oxic horizon on polysilicon (15).