CN202307902U

CN202307902U - Terminal structure of super junction VDMOS

Info

Publication number: CN202307902U
Application number: CN2011203915752U
Authority: CN
Inventors: 钱钦松; 祝靖; 林颜章; 马文力; 孙伟锋; 陆生礼; 时龙兴
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2011-10-15
Filing date: 2011-10-15
Publication date: 2012-07-04
Anticipated expiration: 2021-10-15

Abstract

The utility model provides a terminal structure of a super junction VDMOS. The terminal structure of the super junction VDMOS includes an N-type heavy doping silicon substrate that also functions as a drain region. A drain electrode metal is arranged on the lower surface of the N-type heavy doping silicon substrate. An N-type doping silicon epitaxial layer is arranged on the upper surface of the N-type heavy doping silicon substrate. A super junction structure is arranged on the N-type doping silicon epitaxial layer. The super junction structure includes a P-type doping silicon columnar area and an N-type doping silicon columnar area. The P-type doping silicon columnar area and the N-type doping silicon columnar area are arranged alternately in a staggered pattern. A silica layer is arranged on the super junction structure. It is characterized in that a row of N-type doping silicon areas is arranged on the top of the P-type doping silicon columnar area while a row of P-type doping silicon areas is arranged on the top of the N-type doping silicon columnar area.

Description

Ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure

Technical field

The utility model belongs to the semiconductor power device technology field; Relate to and receive the silicon system high voltage power device that mobile ion stains to be influenced; The silicon system of being specially adapted to ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor (Superjunction VDMOS, promptly hyperconjugation VDMOS all is abbreviated as hyperconjugation VDMOS once); In particular, relate to a kind of terminal structure that under the high temperature reverse bias condition, has the silicon system hyperconjugation VDMOS of high reliability.

Background technology

At present; Power device in the application in fields such as daily life, production more and more widely; Power metal oxide semiconductor field-effect transistor particularly; Because they have switching speed, less drive current, the safety operation area of broad faster, therefore received numerous researchers' favor.Nowadays, power device is just towards improving operating voltage, increase operating current, reducing conducting resistance and integrated direction develops.The utility model of ultra knot is the technical milestone of power metal oxide semiconductor field-effect transistor.

Power device not only gains great popularity in sophisticated technology fields such as national defence, space flight, aviations, and in industry, fields such as civilian household electrical appliances are paid attention to by people too.Growing along with power device, its reliability has also become the focus of people's common concern.Power device is that electronic equipment provides the power supply of desired form and motor device that driving is provided, and almost all electronic equipments and motor device all need be used power device, so the research of device reliability is had great important.

The definition of reliability is that product is accomplished the ability of predetermined function under defined terms and in the official hour.So-called defined terms mainly refers to use the conditions and environment condition.Service condition is meant that those will enter into product or material internal and acting stress condition, like electric stress, chemical stress and physical stress.The scope of reliability test is very extensive, its objective is in order to examine electronic products such as electronic devices and components in storage, transportation and the course of work, possibly run into various complicated mechanical, environmental condition.

Because the application scenario of power device; It is particularly important that reliability property under the high-temperature and high-pressure conditions seems; High temperature reverse bias (High Temperature Reverse bias, HTRB) test is just in order to assess a kind of reliability testing that useful life and the reliability of power chip under the high temperature reverse bias condition carried out; The mobile ion of under high-temperature and high-pressure conditions, being introduced by encapsulation (mainly be receive ion) has certain probability and passes the passivation layer of power device chip and the interface that dielectric layer enters into silicon and silicon dioxide, and the silicon surface electric field distribution that these mobile ions can change power device makes the withstand voltage degeneration of device.Therefore, reduce the withstand voltage susceptibility of power device under the high temperature reverse bias test extremely important meaning is arranged.

Through the terminal structure silicon face at hyperconjugation VDMOS the mobile ion blocking-up structure being set can suppress mobile ion and moved to the chip center zone by the terminal structure zone of hyperconjugation VDMOS.Electric field line is than comparatively dense near blocking-up structure, thereby electric field strength is bigger; With respect to other zone, have local peak value (below be called peak value electric field) near the electric field strength size blocking-up structure.In the time of near mobile ion moves to blocking-up structure, receive the effect of peak value electric field, mobile ion will be fixed near the somewhere of blocking-up structure, no longer continue to move.Therefore, the blocking-up structure that is arranged on hyperconjugation VDMOS terminal structure surface can suppress moving of mobile ion, thereby reaches the ability that the anti-mobile ion of hyperconjugation VDMOS stains that improves.

Summary of the invention

The utility model provides ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure, and related structure can stop mobile ion to move to chip internal, has improved the ability that the anti-mobile ion of transistor stains.

The utility model adopts following technical scheme:

Ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure; Comprise: the double N type heavily doped silicon substrate of doing the drain region; Lower surface at N type heavily doped silicon substrate is provided with drain metal, is provided with N type doped epitaxial silicon layer at the upper surface of N type heavily doped silicon substrate, on N type doped epitaxial silicon layer, is provided with super-junction structure; Described super-junction structure comprises P type doped silicon cylindrical region and N type doped silicon cylindrical region; P type doped silicon cylindrical region and N type doped silicon cylindrical region are alternately arranged, and on described super-junction structure, are provided with silicon dioxide layer, it is characterized in that; Be provided with a row N type doped silicon regions at P type doped silicon cylindrical region top, be provided with a row P type doped silicon region at N type doped silicon cylindrical region top.

Compared with prior art, the utlity model has following advantage:

1, the utility model structure is provided with a row N type doped silicon regions at the P of traditional super-junction structure type doped silicon cylindrical region top; And be provided with a row P type doped silicon region at the N of traditional super-junction structure type doped silicon cylindrical region top; Each the N type doped silicon regions that is arranged on P type doped silicon cylindrical region top with the intersection of P type doped silicon cylindrical region near can form peak value electric field; Each the P type doped silicon regions that is arranged on N type doped silicon cylindrical region top simultaneously with the intersection of N type doped silicon cylindrical region near can form peak value electric field; Peak value electric field in P type doped silicon cylindrical region top and the formation of N type doped silicon cylindrical region top can be fixed near the mobile ion moving to; Make mobile ion can't arrive chip internal, thereby improved chip reliability.

Description of drawings

Fig. 1 is the position view that the related ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the utility model content is arranged in chip.

Fig. 2 is the schematic top plan view of the ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the utility model, wherein the concordant arrangement of P type doped silicon regions at the N type doped silicon regions at P type doped silicon cylindrical region top and N type doped silicon cylindrical region top.

Fig. 3 is the profile of the ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the utility model among Fig. 2 along AA ' direction.

Fig. 4 is the profile of the ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the utility model among Fig. 2 along BB ' direction, wherein contains the sketch map of this body structure surface peak value electric field.

Fig. 5 is the profile of the ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the utility model among Fig. 2 along CC ' direction.

Fig. 6 be the utility model ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure schematic top plan view, wherein the P type doped silicon regions at the N type doped silicon regions at P type doped silicon cylindrical region top and N type doped silicon cylindrical region top dislocation is arranged.

Embodiment

Ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure; Comprise: the double N type heavily doped silicon substrate 4 of doing the drain region; Lower surface at N type heavily doped silicon substrate 4 is provided with drain metal 11, is provided with N type doped epitaxial silicon layer 5 at the upper surface of N type heavily doped silicon substrate 4, on N type doped epitaxial silicon layer 5, is provided with super-junction structure; Described super-junction structure comprises P type doped silicon cylindrical region 6 and N type doped silicon cylindrical region 7; P type doped silicon cylindrical region 6 is alternately arranged with N type doped silicon cylindrical region 7, on described super-junction structure, is provided with silicon dioxide layer 8, it is characterized in that; Be provided with a row N type doped silicon regions 9 at P type doped silicon cylindrical region 6 tops, be provided with a row P type doped silicon regions 10 at N type doped silicon cylindrical region 7 tops.N type doped silicon regions 9 is one of following dual mode with the positional alignment of P type doped silicon regions 10:

(1) the P type doped silicon regions 10 concordant arrangements at the N type doped silicon regions 9 at P type doped silicon cylindrical region 6 tops and N type doped silicon cylindrical region 7 tops.

(2) the N type doped silicon regions 9 at P type doped silicon cylindrical region 6 tops is arranged with P type doped silicon regions 10 dislocation at N type doped silicon cylindrical region 7 tops.

With reference to the accompanying drawings, the embodiment of the utility model is made more detailed explanation:

With reference to figure 1, the ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure 1 that the utility model relates to is positioned at around the transition region 2, and said transition region 2 is surrounded primitive unit cell district 3.

Fig. 2 is the schematic top plan view of the ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the utility model, wherein the P type doped silicon regions 10 concordant arrangements at the N type doped silicon regions 9 at P type doped silicon cylindrical region 6 tops and N type doped silicon cylindrical region 7 tops.Generalized section along AA ', BB ', CC ' among Fig. 2 is respectively Fig. 3, Fig. 4, Fig. 5.Ordinate E is the surface field intensity size of a kind of ultra-junction longitudinal bilateral diffusion metallic oxide field effect pipe terminal structure shown in Figure 2 among Fig. 4; Abscissa X is along this position from left to right, terminal structure surface; Can find out along the variation of X from electric field strength size E, form a plurality of electric field strength peak values on the surface of terminal structure shown in Figure 2.

Fig. 6 is the schematic top plan view of the ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the utility model, and wherein the N type doped silicon regions 9 at P type doped silicon cylindrical region 6 tops is arranged with P type doped silicon regions 10 dislocation at N type doped silicon cylindrical region 7 tops.

Claims

1. ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure; Comprise: the double N type heavily doped silicon substrate (4) of doing the drain region; Lower surface at N type heavily doped silicon substrate (4) is provided with drain metal (11), is provided with N type doped epitaxial silicon layer (5) at the upper surface of N type heavily doped silicon substrate (4), on N type doped epitaxial silicon layer (5), is provided with super-junction structure; Described super-junction structure comprises P type doped silicon cylindrical region (6) and N type doped silicon cylindrical region (7); P type doped silicon cylindrical region (6) and N type doped silicon cylindrical region (7) are alternately arranged, and on described super-junction structure, are provided with silicon dioxide layer (8), it is characterized in that; Be provided with row's N type doped silicon regions (9) at P type doped silicon cylindrical region (6) top, be provided with row's P type doped silicon regions (10) at N type doped silicon cylindrical region (7) top.

2. ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure according to claim 1; It is characterized in that the concordant arrangement of P type doped silicon regions (10) at the N type doped silicon regions (9) at P type doped silicon cylindrical region (6) top and N type doped silicon cylindrical region (7) top.

3. ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure according to claim 1; It is characterized in that the N type doped silicon regions (9) at P type doped silicon cylindrical region (6) top is arranged with P type doped silicon regions (10) dislocation at N type doped silicon cylindrical region (7) top.