CN102315274B - Hyperconjugation terminal structure of longitudinal double-diffused metal-oxide field effect transistor - Google Patents
Hyperconjugation terminal structure of longitudinal double-diffused metal-oxide field effect transistor Download PDFInfo
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- CN102315274B CN102315274B CN 201110311815 CN201110311815A CN102315274B CN 102315274 B CN102315274 B CN 102315274B CN 201110311815 CN201110311815 CN 201110311815 CN 201110311815 A CN201110311815 A CN 201110311815A CN 102315274 B CN102315274 B CN 102315274B
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Abstract
The invention discloses a hyperconjugation terminal structure of a longitudinal double-diffused metal-oxide field effect transistor, which comprises an N-type heavily-doped silicon substrate which is simultaneously used as a drain region, wherein a drain electrode metal is arranged on the lower surface of the N-type heavily-doped silicon substrate; an N-type doping silicon epitaxial layer is arranged on the upper surface of the N-type heavily-doped silicon substrate; a hyperconjugation structure is arranged on the N-type doping silicon epitaxial layer and comprises P-type doped silicon columnar regions and N-type doped silicon columnar regions which are arrayed alternatively; and a silicon dioxide layer is arranged on the hyperconjugation structure. The hyperconjugation terminal structure is characterized in that a row of N-type doped silicon regions are arranged at the top of the P-type doped silicon columnar regions; and a row of P-type doped silicon region are arranged at the top of the N-type doped silicon columnar regions.
Description
Technical field
The invention belongs to the semiconductor power device technology field, relate to and be subjected to the silicon high voltage power device processed that mobile ion stains to be affected, be specially adapted to silicon ultra-junction longitudinal bilateral diffusion metal oxide processed field-effect transistor (Superjunction VDMOS, it is hyperconjugation VDMOS, all be abbreviated as hyperconjugation VDMOS once), in particular, relate to a kind of terminal structure that under the high temperature reverse bias condition, has the silicon hyperconjugation VDMOS processed of high reliability.
Background technology
At present, power device is more and more extensive in the application in the fields such as daily life, production, power metal oxide semiconductor field-effect transistor particularly, because they have faster switching speed, less drive current, wider safety operation area, therefore be subject to numerous researchers' favor.Nowadays, power device is just towards improving operating voltage, increase operating current, reducing conducting resistance and integrated future development.The invention of super knot is the technical milestone of power metal oxide semiconductor field-effect transistor.
Power device not only gains great popularity in sophisticated technology fields such as national defence, space flight, aviations, and in industry, the fields such as civilian household electrical appliances are paid attention to by people too.Growing along with power device, its reliability has also become the focus of people's common concern.Power device provides driving for electronic equipment provides the power supply of desired form and motor device, and almost all electronic equipments and motor device all need be used power device, so the research of device reliability is had vital meaning.
The definition of reliability is, product is under defined terms and the in setting time the ability of completing setting function.So-called defined terms mainly refers to use the conditions and environment condition.Service condition refers to that those will enter into product or material internal and the stress condition that works, such as electric stress, chemical stress and physical stress.The scope of reliability test is very extensive, its objective is in order to examine the electronic products such as electronic devices and components may run into machinery, the environmental condition of various complexity in storage, transportation and the course of work.
Because the application scenario of power device, it is particularly important that reliability under the high-temperature and high-pressure conditions seems, high temperature reverse bias (High Temperature Reverse bias, HTRB) test is just in order to assess useful life and the reliability a kind of reliability testing carried out of power chip under the high temperature reverse bias condition; The mobile ion of being introduced by encapsulation under high-temperature and high-pressure conditions (mainly be receive ion) has certain probability and passes the passivation layer of power device chip and the interface that dielectric layer enters into silicon and silicon dioxide, and the silicon surface electric field distribution that these mobile ions can change power device makes the withstand voltage degeneration of device.Therefore, reduce the withstand voltage susceptibility of power device under the high temperature reverse bias test extremely important meaning is arranged.
By the terminal structure silicon face at hyperconjugation VDMOS the mobile ion blocking-up structure being set, can to suppress mobile ion mobile to the chip center zone by the terminal structure zone of hyperconjugation VDMOS.Electric field line is than comparatively dense near blocking-up structure, thereby electric field strength is larger; With respect to other zone, the electric field strength size has local peak value (hereinafter referred to as peak value electric field) near blocking-up structure.In the time of near mobile ion moves to blocking-up structure, be subject to the effect of peak value electric field, mobile ion will be fixed near the somewhere of blocking-up structure, no longer continue mobile.Therefore, the blocking-up structure that is arranged on hyperconjugation VDMOS terminal structure surface can suppress the movement of mobile ion, thereby reaches the ability that the anti-mobile ion of hyperconjugation VDMOS stains that improves.
Summary of the invention
The invention provides ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure, related structure can stop mobile ion to move to chip internal, has improved the ability that the anti-mobile ion of transistor stains.
The present invention adopts following technical scheme:
Ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure, comprise: the double N-type heavily doped silicon substrate of doing the drain region, lower surface at N-type heavily doped silicon substrate is provided with drain metal, upper surface at N-type heavily doped silicon substrate is provided with the N-type doped epitaxial silicon layer, be provided with super-junction structure at the N-type doped epitaxial silicon layer, described super-junction structure comprises P type doped silicon cylindrical region and N-type doped silicon cylindrical region, P type doped silicon cylindrical region and N-type doped silicon cylindrical region alternative arrangement, be provided with silicon dioxide layer at described super-junction structure, it is characterized in that, be provided with row's N-type doped silicon regions at P type doped silicon cylindrical region top, be provided with a row P type doped silicon region at N-type doped silicon cylindrical region top.
Compared with prior art, the present invention has following advantage:
1, structure of the present invention is provided with row's N-type doped silicon regions at the P of traditional super-junction structure type doped silicon cylindrical region top, and be provided with a row P type doped silicon region at the N-type doped silicon cylindrical region top of traditional super-junction structure, each the N-type doped silicon regions that is arranged on P type doped silicon cylindrical region top with the intersection of P type doped silicon cylindrical region near can form peak value electric field, each the P type doped silicon regions that is arranged on simultaneously N-type doped silicon cylindrical region top with the intersection of N-type doped silicon cylindrical region near can form peak value electric field, peak value electric field in P type doped silicon cylindrical region top and the formation of N-type doped silicon cylindrical region top can be fixed near the mobile ion moving to, make mobile ion can't arrive chip internal, thereby improved the reliability of chip.
Description of drawings
Fig. 1 is the position view that the related ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of content of the present invention is arranged in chip.
Fig. 2 is the schematic top plan view of ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the present invention, wherein the concordant arrangement of P type doped silicon regions at the N-type doped silicon regions at P type doped silicon cylindrical region top and N-type doped silicon cylindrical region top.
Fig. 3 be among Fig. 2 ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the present invention along the profile of AA ' direction.
Fig. 4 is that ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the present invention wherein contains the schematic diagram of this body structure surface peak value electric field along the profile of BB ' direction among Fig. 2.
Fig. 5 be among Fig. 2 ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the present invention along the profile of CC ' direction.
Fig. 6 be ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the present invention schematic top plan view, the P type doped silicon regions Heterogeneous Permutation at the N-type doped silicon regions at P type doped silicon cylindrical region top and N-type doped silicon cylindrical region top wherein.
Embodiment
Ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure, comprise: the double N-type heavily doped silicon substrate 4 of doing the drain region, lower surface at N-type heavily doped silicon substrate 4 is provided with drain metal 11, upper surface at N-type heavily doped silicon substrate 4 is provided with N-type doped epitaxial silicon layer 5, be provided with super-junction structure at N-type doped epitaxial silicon layer 5, described super-junction structure comprises P type doped silicon cylindrical region 6 and N-type doped silicon cylindrical region 7, P type doped silicon cylindrical region 6 and N-type doped silicon cylindrical region 7 alternative arrangements, be provided with silicon dioxide layer 8 at described super-junction structure, it is characterized in that, be provided with row's N-type doped silicon regions 9 at P type doped silicon cylindrical region 6 tops, be provided with a row P type doped silicon regions 10 at N-type doped silicon cylindrical region 7 tops.N-type doped silicon regions 9 is one of following dual mode with the positional alignment of P type doped silicon regions 10:
(1) the P type doped silicon regions 10 concordant arrangements at the N-type doped silicon regions 9 at P type doped silicon cylindrical region 6 tops and N-type doped silicon cylindrical region 7 tops.
(2) the N-type doped silicon regions 9 at P type doped silicon cylindrical region 6 tops and P type doped silicon regions 10 Heterogeneous Permutations at N-type doped silicon cylindrical region 7 tops.
With reference to the accompanying drawings, the specific embodiment of the present invention is made more detailed explanation:
With reference to figure 1, the ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure 1 that the present invention relates to is positioned at around the transition region 2, and described transition region 2 is surrounded primitive unit cell district 3.
Fig. 2 is the schematic top plan view of ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the present invention, wherein the P type doped silicon regions 10 concordant arrangements at the N-type doped silicon regions 9 at P type doped silicon cylindrical region 6 tops and N-type doped silicon cylindrical region 7 tops.Generalized section along AA ', BB ', CC ' among Fig. 2 is respectively Fig. 3, Fig. 4, Fig. 5.Ordinate E is the surface field intensity size of a kind of ultra-junction longitudinal bilateral diffusion metallic oxide field effect pipe terminal structure shown in Figure 2 among Fig. 4, abscissa X is along this position from left to right, terminal structure surface, can find out along the variation of X from electric field strength size E, form a plurality of electric field strength peak values on the surface of terminal structure shown in Figure 2.
Fig. 6 is the schematic top plan view of ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure of the present invention, wherein the N-type doped silicon regions 9 at P type doped silicon cylindrical region 6 tops and P type doped silicon regions 10 Heterogeneous Permutations at N-type doped silicon cylindrical region 7 tops.
Claims (3)
1. ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure, comprise: the double N-type heavily doped silicon substrate (4) of doing the drain region, lower surface at N-type heavily doped silicon substrate (4) is provided with drain metal (11), upper surface at N-type heavily doped silicon substrate (4) is provided with N-type doped epitaxial silicon layer (5), be provided with super-junction structure at N-type doped epitaxial silicon layer (5), described super-junction structure comprises P type doped silicon cylindrical region (6) and N-type doped silicon cylindrical region (7), P type doped silicon cylindrical region (6) and N-type doped silicon cylindrical region (7) alternative arrangement, be provided with silicon dioxide layer (8) at described super-junction structure, it is characterized in that, be provided with row's N-type doped silicon regions (9) at P type doped silicon cylindrical region (6) top, be provided with row's P type doped silicon regions (10) at N-type doped silicon cylindrical region (7) top.
2. ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure according to claim 1, it is characterized in that the concordant arrangement of P type doped silicon regions (10) at the N-type doped silicon regions (9) at P type doped silicon cylindrical region (6) top and N-type doped silicon cylindrical region (7) top.
3. ultra-junction longitudinal bilateral diffusion metal oxide field-effect transistor terminal structure according to claim 1, it is characterized in that P type doped silicon regions (10) Heterogeneous Permutation at the N-type doped silicon regions (9) at P type doped silicon cylindrical region (6) top and N-type doped silicon cylindrical region (7) top.
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| CN 201110311815 CN102315274B (en) | 2011-10-15 | 2011-10-15 | Hyperconjugation terminal structure of longitudinal double-diffused metal-oxide field effect transistor |
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| CN 201110311815 CN102315274B (en) | 2011-10-15 | 2011-10-15 | Hyperconjugation terminal structure of longitudinal double-diffused metal-oxide field effect transistor |
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| CN102315274B true CN102315274B (en) | 2013-01-30 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6870201B1 (en) * | 1997-11-03 | 2005-03-22 | Infineon Technologies Ag | High voltage resistant edge structure for semiconductor components |
| CN102082168A (en) * | 2009-10-30 | 2011-06-01 | 万国半导体股份有限公司 | Staggered column superjunction |
| CN102117830A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Super-MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure of semi-insulating column |
| CN202307902U (en) * | 2011-10-15 | 2012-07-04 | 东南大学 | Terminal structure of super junction VDMOS |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4843843B2 (en) * | 2000-10-20 | 2011-12-21 | 富士電機株式会社 | Super junction semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6870201B1 (en) * | 1997-11-03 | 2005-03-22 | Infineon Technologies Ag | High voltage resistant edge structure for semiconductor components |
| CN102082168A (en) * | 2009-10-30 | 2011-06-01 | 万国半导体股份有限公司 | Staggered column superjunction |
| CN102117830A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Super-MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure of semi-insulating column |
| CN202307902U (en) * | 2011-10-15 | 2012-07-04 | 东南大学 | Terminal structure of super junction VDMOS |
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