CN105097728B - Encapsulating structure - Google Patents
Encapsulating structure Download PDFInfo
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- CN105097728B CN105097728B CN201510373971.5A CN201510373971A CN105097728B CN 105097728 B CN105097728 B CN 105097728B CN 201510373971 A CN201510373971 A CN 201510373971A CN 105097728 B CN105097728 B CN 105097728B
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- connecting key
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- plastic packaging
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- packaging layer
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- 238000004806 packaging method and process Methods 0.000 claims abstract description 178
- 229920003023 plastic Polymers 0.000 claims abstract description 149
- 239000004033 plastic Substances 0.000 claims abstract description 149
- 239000004020 conductor Substances 0.000 claims abstract description 127
- 239000010410 layer Substances 0.000 claims description 238
- 239000000463 material Substances 0.000 claims description 69
- 239000011241 protective layer Substances 0.000 claims description 69
- 230000004888 barrier function Effects 0.000 claims description 49
- 239000011810 insulating material Substances 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 238000009413 insulation Methods 0.000 claims description 20
- 229920000915 polyvinyl chloride Polymers 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 239000004411 aluminium Substances 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 239000004800 polyvinyl chloride Substances 0.000 claims description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 230000006870 function Effects 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 65
- 238000005516 engineering process Methods 0.000 description 30
- 239000011347 resin Substances 0.000 description 30
- 239000000758 substrate Substances 0.000 description 28
- 229920005989 resin Polymers 0.000 description 24
- 230000008569 process Effects 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 238000005530 etching Methods 0.000 description 15
- 238000005520 cutting process Methods 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 8
- 229920000647 polyepoxide Polymers 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 239000009719 polyimide resin Substances 0.000 description 8
- 239000011135 tin Substances 0.000 description 8
- 229910052718 tin Inorganic materials 0.000 description 8
- 238000000576 coating method Methods 0.000 description 7
- 238000010276 construction Methods 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 7
- 239000003292 glue Substances 0.000 description 7
- 229920002577 polybenzoxazole Polymers 0.000 description 7
- -1 polybutylene terephthalate Polymers 0.000 description 6
- 238000010992 reflux Methods 0.000 description 6
- 239000002356 single layer Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000003854 Surface Print Methods 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000012774 insulation material Substances 0.000 description 4
- 229920000098 polyolefin Polymers 0.000 description 4
- 229920002635 polyurethane Polymers 0.000 description 4
- 239000004814 polyurethane Substances 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 239000004425 Makrolon Substances 0.000 description 2
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 2
- 239000004695 Polyether sulfone Substances 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 2
- 239000004372 Polyvinyl alcohol Substances 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 239000002365 multiple layer Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- 229920001707 polybutylene terephthalate Polymers 0.000 description 2
- 229920000515 polycarbonate Polymers 0.000 description 2
- 229920006393 polyether sulfone Polymers 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- 229920002451 polyvinyl alcohol Polymers 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 241000196324 Embryophyta Species 0.000 description 1
- 150000003851 azoles Chemical class 0.000 description 1
- JSLMNNPQKHONFW-UHFFFAOYSA-N benzene naphthalene-1-carboxylic acid Chemical compound C1(=CC=CC2=CC=CC=C12)C(=O)O.C1=CC=CC=C1 JSLMNNPQKHONFW-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229920001038 ethylene copolymer Polymers 0.000 description 1
- 239000005038 ethylene vinyl acetate Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001200 poly(ethylene-vinyl acetate) Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920006389 polyphenyl polymer Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of encapsulating structure, including:Plastic packaging layer, plastic packaging layer have relative the 5th surface and the 6th surface;Chip in plastic packaging layer, chip have relative first surface and second surface, and the second surface of chip includes functional areas, and the first surface of chip flushes with the 5th surface of plastic packaging layer;Through the connecting key of plastic packaging layer, connecting key is located at chip circumference, connecting key includes conductor wire, connecting key includes first end and the second end, the first end of connecting key and the second end expose conductor wire, the first end of connecting key flushes with the 5th surface of plastic packaging layer, and the second end of connecting key is higher than or be flush to the 6th surface of plastic packaging layer;Wiring layer again positioned at the surface of plastic packaging layer the 6th, then wiring layer electrically connect with the second end of connecting key and the functional areas of chip;Positioned at the first soldered ball for connecting up layer surface again.The encapsulating structure is simple, manufacturing cost reduces, accurate size and diminution.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of encapsulating structure.
Background technology
In the prior art, chip is that the side of (Wire Bonding) is bonded by metal lead wire with the connection of external circuit
Formula realization, i.e. Wire Bonding Technology.As the feature size downsizing of chip and the integrated level of integrated circuit improve, wire bonding skill
The art no longer growth requirement of applicable technology.
In order to improve the integrated level of chip package, Stacked Die Packaging (stacked die package) technology gradually into
For the main flow of technology development.Stacked Die Packaging technology, also known as three-dimensional packaging technology, specifically stacked in same packaging body
The encapsulation technology of at least two chips.Stacked Die Packaging technology can realize the Large Copacity of semiconductor devices, multi-functional, small chi
The technical need such as very little, inexpensive, therefore laminated chips technology is flourished in recent years.
By taking the memory using stacked package technology as an example, compared to the memory for not using Stack Technology, using heap
The memory of folded encapsulation technology can possess more than twice of memory capacity.In addition, more can be effective using stacked package technology
Ground utilizes the area, USB flash disk, SD card more applied to big memory space etc. of chip.
Stacked chips encapsulation technology can be realized by multiple technologies means, such as routing technique, silicon hole
(through silicon via, abbreviation TSV) technology or plastic packaging through hole (through molding via, abbreviation TMV) skill
Art.
However, above-mentioned technological means still faces various technique limitations and cost limitation, further subtract moreover, being faced with
The problem of thin encapsulating structure thickness.
The content of the invention
Of the invention to solve the problems, such as to be to provide a kind of encapsulating structure, the encapsulating structure is simple, manufacturing cost reduces, size
Accurate and diminution.
To solve the above problems, the present invention also provides a kind of encapsulating structure, including:Plastic packaging layer, the plastic packaging layer have phase
To the 5th surface and the 6th surface;Chip in the plastic packaging layer, the chip have relative first surface and
Two surfaces, the second surface of the chip include functional areas, the 5th surface of the first surface of the chip and the plastic packaging layer
Flush;Through the connecting key of the plastic packaging layer, the connecting key is located at the chip circumference, and the connecting key includes conductor wire,
The connecting key includes first end and the second end, and the first end of the connecting key and the second end expose the conductor wire, described
The first end of connecting key flushes with the 5th surface of plastic packaging layer, and the second end of the connecting key is higher than or be flush to the plastic packaging layer
The 6th surface;Wiring layer again positioned at the surface of plastic packaging layer the 6th, the second end of the wiring layer again and the connecting key
And the functional areas electrical connection of chip;Positioned at first soldered ball for connecting up layer surface again.
Optionally, the connecting key also includes the protective layer positioned at the conductor wire sidewall surfaces, the protective layer exposure
Go out the conductor wire at the connecting key first end and the second end.
Optionally, the material of the protective layer is insulating materials.
Optionally, the insulating materials is organic insulation or inorganic insulating material;The organic insulation includes
Polyvinyl chloride;The inorganic insulating material includes the one or more in silica, silicon nitride and silicon oxynitride.
Optionally, the first end size of the connecting key is more than the second end size of the connecting key.
Optionally, the first end size of the connecting key is identical with the second end size.
Optionally, the connecting key first end to the second end distance be 40 microns~400 microns.
Optionally, the conductive linear dimension of the connecting key first end and the conductive linear dimension at the second end are identical.
Optionally, the material of the conductor wire is copper, tungsten, aluminium, gold or silver.
Optionally, in addition to:Carrier, the first surface of the chip, the 5th surface of the plastic packaging layer and the company
The first end for connecing key is fixed on the carrier surface.
Optionally, the first surface of the chip is fixed on the carrier surface by tack coat;The of the connecting key
The carrier surface is fixed in one end by tack coat.
Optionally, the functional areas surface of the chip exposes pad;The bond pad surface has projection, the projection
Top surface protrudes from the second surface of the chip;The plastic packaging layer exposes the top surface of the projection, the projection
Top surface be the chip functional areas surface.
Optionally, in addition to:The first insulating barrier positioned at the surface of plastic packaging layer the 6th, have in first insulating barrier
The conductor wire at the end of connecting key second and some first through hole on chip functions area surface are exposed respectively;The cloth again
Line layer is located in the first through hole and the surface of insulating layer of part first.
Optionally, in addition to:Have in second insulating barrier for connecting up layer surface again, second insulating barrier sudden and violent
Second through hole of exposed portion wiring layer again;First soldered ball is located in second through hole.
Optionally, in addition to:The second soldered ball positioned at the conductor wire surface of the connecting key first end.
Optionally, in addition to:Packaging body, the packaging body have the 3rd surface, the 3rd surface exposure of the packaging body
Go out conductive structure;The first surface and plastic packaging layer surface of the chip and the 3rd surface of the packaging body are oppositely arranged, described
Conductive structure is connected with each other by second soldered ball and the connecting key.
Compared with prior art, technical scheme has advantages below:
In the encapsulating structure of the present invention, key is directly fixedly connected with the carrier surface of chip circumference, the connecting key includes
Conductor wire, and the first end of the connecting key and the second end expose conductor wire, and the connecting key runs through the plastic packaging layer,
I.e. described conductor wire can be through to the 6th surface from the 5th surface of the plastic packaging layer, realize chip first surface to this
The electrical connection on two surfaces.Moreover, the connecting key and chip are directly fixed in the plastic packaging layer, make the connecting key relative to
The position of the chip is more accurate and is easy to regulate and control, and not only contributes to ensure the accurate size of encapsulating structure, and is advantageous to
Avoid in wiring layer relative to generation position skew between the connecting key or chip.Therefore, the structure letter of the encapsulating structure
Single, manufacturing cost reduces, and the size of the encapsulating structure is more accurate, is advantageous to reduce the size of encapsulating structure.
Further, the connecting key also includes the protective layer positioned at the conductor wire sidewall surfaces.The protective layer is not only
The conductor wire can be protected, additionally it is possible to so that the cross sectional dimensions increase of connecting key so that the connecting key is easier to be aligned,
Advantageously ensure that the connecting key is accurate relative to the position of chip.
Further, the first end size of the connecting key is more than the second end size of the connecting key.Due to the connection
Carrier surface is fixed at second end of key, and the first end size of the connecting key is larger, is advantageous to carrying the connecting key
The fixation in body surface face is more stable, can ensure that the relative position between connecting key and chip is accurate.
Brief description of the drawings
Fig. 1 is that through-silicon via structure is introduced in encapsulating structure to realize the cross-sectional view of chip chamber conducting;
Fig. 2 is that plastic packaging through-hole structure is introduced in encapsulating structure to realize the cross-sectional view of chip chamber conducting;
Fig. 3 to Figure 16 is the cross-sectional view of the forming process of the encapsulating structure of one embodiment of the invention;
Figure 17 to Figure 20 is the cross-sectional view of the forming process of the encapsulating structure of another embodiment of the present invention.
Embodiment
As stated in the Background Art, existing stacked chips encapsulation technology faces technique limitation and cost limitation, for technology
Popularization and application cause limitation, moreover, stacked chips encapsulation technology is also faced with that encapsulating structure thickness is further being thinned
The problem of, to further improve the integrated level of chip, reduce size.
Stacked chips encapsulation technology can pass through silicon hole (through silicon via, abbreviation TSV) technology or plastic packaging
Through hole (through molding via, abbreviation TMV) technology is realized.However, either silicon hole technology or plastic packaging through hole
Technology, it is respectively provided with certain defect.
Fig. 1 is refer to, Fig. 1 is that through-silicon via structure is introduced in encapsulating structure to realize that the cross-section structure of chip chamber conducting shows
It is intended to, including:Carrier 100;The chip 101 on the surface of carrier 100 is fixed on, the chip 101 includes relative non-functional face 102
And functional surfaces 103, the non-functional face 102 of the chip 101 are in contact with the surface of carrier 100, the functional surfaces of the chip 101
103 surfaces have pad 104;Through the conductive plunger 105 of the chip 101, one end and the weldering of the conductive plunger 105
Disk 104 electrically connects;Plastic packaging layer 106 positioned at the surface of carrier 100, the plastic packaging layer 106 surround the chip 101, and institute
State plastic packaging layer 106 and expose the pad 104;Positioned at wiring layer 107 again on the surface of plastic packaging layer 106, the wiring layer again
107 electrically connect with the pad 104;Soldered ball 108 positioned at the surface of wiring layer again 107.
Wherein, the conductive plunger 105 is generally formed before cutting forms independent chip 101;The conductive plunger
105 forming step includes:Substrate is provided, the substrate has functional surfaces, and the substrate includes some chip regions;Using quarter
Etching technique forms through hole in the chip region of the substrate from the functional surfaces;Formed in the side wall and lower surface of the through hole
Insulating barrier (does not indicate);Surface of insulating layer in the through hole forms conductive plunger 105;It is relative with functional surfaces from the substrate
Surface is polished, until exposing an end position of the conductive plunger 105;After the glossing, described in cutting
Substrate, some chip regions are made to form independent chip 101.
However, it is necessary to form through hole in substrate during the conductive plunger 105 is formed, and the through hole
Depth is the thickness of chip 101 that is formed, therefore the depth of the through hole is deeper, and the depth-to-width ratio of the through hole is higher, therefore, right
Form that the etching technics requirement of the through hole is higher, and the difficulty of the etching technics is larger.Moreover, subsequently need in the through hole
Interior filling conductive material is to form conductive plunger 105, and the depth-to-width ratio of the through hole is higher, the filling difficulty of the conductive material
It is larger, it is higher for the technological requirement of formation conductive plunger 105.In addition, realize the etching technics and profundity of above-mentioned high-aspect-ratio
The wide process costs than through hole filling are higher.To sum up, because the technology difficulty of through-silicon via structure is higher, technique is complex, and
Process costs are higher, and being applied to stacked chips encapsulation for silicon hole technology causes limitation.
In order to reduce technology difficulty, a kind of plastic packaging through hole technology is had also been proposed.Fig. 2 is refer to, Fig. 2 is in encapsulating structure
Plastic packaging through-hole structure is introduced to realize the cross-sectional view of chip chamber conducting, including:Carrier 110;It is fixed on the table of carrier 110
The chip 111 in face, the chip 111 include relative non-functional face 112 and functional surfaces 113, the chip 111 it is non-functional
Face 112 is in contact with the surface of carrier 110, and the surface of functional surfaces 113 of the chip 111 has pad 114;Positioned at the carrier
The plastic packaging layer 115 on 110 surfaces, the plastic packaging layer 115 surrounds the chip 111, and the plastic packaging layer 115 exposes the pad
114;Through the conductive plunger 116 of the plastic packaging layer 115;Positioned at wiring layer 117 again on the surface of plastic packaging layer 115, it is described again
Wiring layer 117 electrically connects with the pad 114 and conductive plunger 116;Soldered ball 118 positioned at the surface of wiring layer again 117.
Wherein, the forming step of the conductive plunger 116 includes:Formed using etching technics in the plastic packaging layer 115
It is through to the through hole on the surface of carrier 110;Conductive plunger 116 is formed in the through hole.
However, because the thickness of the plastic packaging layer 115 is the thickness of the chip 111, and the through hole runs through the modeling
Sealing 115, therefore the depth of the through hole is deeper, the depth-to-width ratio of the through hole is higher;Etching technics to forming the through hole
With higher required precision, the difficulty of the etching technics is larger.Secondly as follow-up need to fill in the through hole to lead
Electric material is to form conductive plunger 116, and the depth-to-width ratio of the through hole is higher, cause to fill the difficulty of the conductive material compared with
Greatly.It is additionally, since the conductive plunger 116 to be formed at around the chip 111, therefore, it is necessary to is accurately set to described conductive slotting
116 positions relative to chip are filled in, it is therefore, higher for positioning accuracy request when forming the through hole.To sum up, though using
Plastic packaging through hole technology realizes that stacked chips encapsulate, and is still faced with that complex process, technology difficulty are higher and cost is higher
Problem.
In order to solve the above problems, the present invention provides a kind of encapsulating structure, including:Plastic packaging layer, the plastic packaging layer have phase
To the 5th surface and the 6th surface;Chip in the plastic packaging layer, the chip have relative first surface and
Two surfaces, the second surface of the chip include functional areas, the 5th surface of the first surface of the chip and the plastic packaging layer
Flush;Through the connecting key of the plastic packaging layer, the connecting key is located at the chip circumference, and the connecting key includes conductor wire,
The connecting key includes first end and the second end, and the first end of the connecting key and the second end expose the conductor wire, described
The first end of connecting key flushes with the 5th surface of plastic packaging layer, and the second end of the connecting key is higher than or be flush to the plastic packaging layer
The 6th surface;Wiring layer again positioned at the surface of plastic packaging layer the 6th, the second end of the wiring layer again and the connecting key
And the functional areas electrical connection of chip;Positioned at first soldered ball for connecting up layer surface again.
Wherein, key is directly fixedly connected with the carrier surface of chip circumference, the connecting key includes conductor wire, and the company
The first end and the second end for connecing key expose conductor wire, and the connecting key runs through the plastic packaging layer, i.e., described conductor wire energy
It is enough to be through to the 6th surface from the 5th surface of the plastic packaging layer, chip first surface being electrically connected to second surface is realized with this
Connect.Moreover, the connecting key and chip are directly fixed in the plastic packaging layer, make position of the connecting key relative to the chip
Put more accurate and be easy to regulate and control, not only contribute to ensure the accurate size of encapsulating structure, and be advantageous to avoid in wiring layer
Offset relative to position occurs between the connecting key or chip.Therefore, the structure of the encapsulating structure is simple, manufacturing cost drop
It is low, and the size of the encapsulating structure is more accurate, is advantageous to reduce the size of encapsulating structure.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 3 to Figure 16 is the cross-sectional view of the forming process of the encapsulating structure of one embodiment of the invention.
It refer to Fig. 3, there is provided carrier 200.
The carrier 200 provides workbench for subsequent technique, for the plastic packaging layer for carrying chip He being subsequently formed.
In the present embodiment, the carrier 200 is rigid substrate, and the rigid substrate is PCB substrate, glass substrate, gold
Belong to substrate, semiconductor substrate or polymeric substrates.The rigid substrate has higher hardness, deformation is not susceptible to, follow-up
It is enough supporting-core piece and plastic packaging layer in technique.
In other embodiments, the carrier can also be flexible base plate.
Fig. 4 is refer to, in the surface fixed chip 201 of carrier 200, the chip 201 has relative first surface
210 and second surface 220, the second surface 220 of the chip 201 includes functional areas (not shown), and the first of the chip 201
Surface 210 interfixes with the surface of carrier 200.
The first surface 210 of the chip 201 is fixed on the surface of carrier 200 by tack coat (not shown).It is described
The material of tack coat is UV glue, and UV glue viscosity after ultraviolet irradiates reduces, so as to subsequently by carrier 200 from encapsulating structure
Middle stripping.
In one embodiment, tack coat is adhered in the first surface 210 of the chip 201, then the tack coat is adhered to
In the surface of carrier 200, to realize the bonding between chip 201 and carrier 200.And the first surface 210 of the chip 201 does not have
Functional area, i.e., the first surface 210 of described chip 201 do not have electric connection structure, and the first surface 210 of chip 201 is fixed
After the surface of carrier 200, the functional areas of the second surface 220 of chip 201 can be exposed.
In another embodiment, additionally it is possible to need the correspondence position of fixed chip 201 to be formed on the surface of the carrier 200
Tack coat, or tack coat is formed in the surface global of carrier 200, then the first surface 210 of the chip 201 is adhered to described
Tie layer surface, chip 201 is set to be fixed on the surface of carrier 200.
In the present embodiment, the surface global of carrier 200 covers the tack coat.
The chip 201 can be sensor chip, logic circuit chip, storage chip etc..The table of chip 201 second
Can have transistor, passive device (such as resistance, electric capacity and inductance etc.), memory device, sensing in the functional areas in face 220
One or more of device, electric interconnection structure.
The forming step of the chip 201 includes:Substrate is provided, the substrate has some chip regions, the substrate bag
Relative first surface and second surface are included, there are functional areas in the chip region of the substrate second surface;The substrate is entered
Row cutting, is separated from each other some chip regions, forms independent chip 201.
In the present embodiment, the functional areas surface of the chip 201 exposes pad;The bond pad surface has projection
221, the top surface of the projection 221 protrudes from the second surface 220 of the chip 201, the top surface of the projection 221
The functional areas surface of i.e. described chip 201.The material of the projection 213 includes copper, gold or tin, and the projection 213 has default
Thickness.The projection 221 can be realized with the circuit in functional areas or device and electrically connected.The projection 221 is used for subsequently setting
The connecting key electrical connection put, so as to realize the electrical connection between the functional areas of chip 201 and other chips or external circuit.At this
In embodiment, the functional areas surface of the chip 201 is the top surface of the projection 221.In other embodiments, the work(
Energy area can also be sensor region, have sensor in the sensor region, and the sensor is used to obtain external environment condition
In information.
Fig. 5 is refer to, the surface of carrier 200 around the chip 201 is fixedly connected with key 203, and the connecting key 203 wraps
Conductor wire 230 is included, the connecting key 230 includes the end 232 of first end 231 and second, the He of first end 231 of the connecting key 203
Second end 232 exposes the conductor wire 230, and the first end 231 of the connecting key 203 and the surface of carrier 200 are mutually solid
Fixed, the second end 232 of the connecting key 203 is higher than or is flush to the functional areas surface of the chip 201.
The first end 231 of the connecting key 203 is fixed on the surface of carrier 200 by tack coat.The tack coat
Material is UV glue, and UV glue viscosity after ultraviolet irradiates reduces, subsequently to peel off carrier 200 from encapsulating structure.
In one embodiment, in the surface adhesion tack coat of first end 231 of the connecting key 203, then by the tack coat
The surface of carrier 200 is adhered to, to realize the bonding between connecting key 203 and carrier 200.
In another embodiment, additionally it is possible to need to be fixedly connected with the correspondence position shape of key 203 on the surface of the carrier 200
Tack coat is covered into tack coat, or in the surface global of carrier 200, then the first surface 210 of the connecting key 203 is adhered to
The tie layer surface, connecting key 203 is set to be fixed on the surface of carrier 200.
In the present embodiment, the functional areas surface of the chip 201 is the top surface of the projection 221, and in carrier
200 surfaces are fixedly connected after the first end 231 of key 203, and the surface of the second end 232 of connecting key 203 is higher than or is flush to described
The functional areas surface of chip 201, i.e., the surface of the second end 232 of described connecting key 203 are higher than or are flush to the top of the projection 221
Portion surface.
The surface of carrier 200 around a chip 201, fixes one or several connecting keys 203.When a chip
When the quantity of connecting key 203 around 201 is more than 1, the quantity of the connecting key 203 can count with the projection 221 on the surface of chip 201
Amount is consistent, and the position of the connecting key 203 is corresponding with the position of projection 221 on the surface of chip 201.
The end 232 of first end 231 and second of the connecting key 203 exposes conductor wire 230, by the connecting key 203
First end 231 and the surface of carrier 200 interfix after, i.e., conduction that the described first end 231 of connecting key 203 exposes
Line 230 interfixes with the surface of carrier 200, and the surface of conductor wire 230 that second end 232 exposes is higher than or flushed
In the top surface of the projection 221.Subsequently after plastic packaging layer surface forms wiring layer again, the wiring layer again can be realized
Electrical connection between conductor wire 230 and projection 221 that second end 232 exposes, so that projection 221 arrives the table of carrier 200
Face can realize electrical connection.
Because the connecting key 203 is directly fixed on the surface of carrier 200, avoid be subsequently formed plastic packaging layer and then
The step of carrying out routing technique or forming plastic packaging through-hole structure, can simplify processing step, and reduce technology difficulty, so as to
Cost can be reduced.Moreover, the connecting key 203 is directly fixed on the surface of carrier 200 so that the connecting key 203 relative to
The position of chip 201 is more accurate, avoids during plastic packaging through-hole structure is formed, caused error during etching through hole
Problem.In addition, the second end 232 of the connecting key 203 is higher than or is flush to the top surface of the projection 221, then follow-up shape
Into the surface of plastic packaging layer can be flush to the bond pad surface;Compared in routing technique, plastic packaging layer surface needs to be higher than core
The problem of piece surface, the modeling seal coat thickness that the present embodiment is subsequently formed is relatively thin, is advantageous to the thickness of thinned formed encapsulating structure
Spend size.
In the present embodiment, the distance at 231 to the second end of first end 232 of connecting key 203 is 40 microns~400 micro-
Rice;The distance at 231 to the second end of first end 232 of connecting key 203 is more than or equal to the thickness of the chip 201, the core
The thickness of piece 201 is distance of the top surface of projection 221 to the first surface 210 of chip 201.Thus, it is possible to ensure rear
Continuous to be formed after plastic packaging layer, the plastic packaging layer surface can flush with the top surface of projection 221, while the plastic packaging layer can be sudden and violent
Expose the second end 232 of connecting key 203.
The material of the conductor wire 230 is conductive material, and the conductor wire 230 is used to realize chip 201 from first surface
210 to second surface 220 conducting;It is copper, tungsten, aluminium, gold or silver that the conductive material, which includes,.
In the present embodiment, the connecting key 203 also includes the protective layer 233 positioned at the sidewall surfaces of conductor wire 230,
The protective layer 233 exposes the conductor wire 230 at the first end 231 of connecting key 203 and the second end 232.
In another embodiment, the connecting key can not also include the protective layer, and only have the conductor wire.
The material of the protective layer 233 is insulating materials.The insulating materials is organic insulation or inorganic insulation material
Material;The organic insulation includes polyvinyl chloride or resin;The resin includes epoxy resin, polyimide resin, benzo
Cyclobutane resin or polybenzoxazoles resin;The inorganic insulating material includes one in silica, silicon nitride and silicon oxynitride
Kind is a variety of.
The protective layer 233 can not only be when being fixed on 200 surface of carrier, for protecting described lead by connecting key 203
The surface of electric wire 230 can increase the sectional dimension of the connecting key 203 from damage, so as to consolidate by connecting key 203
Determine with being more easy to be aligned during 200 surface of carrier, so that being fixed on the connecting key 203 on the surface of carrier 200 relative to the position of chip 201
Put more accurate.
In the present embodiment, the size of first end 231 of the connecting key 203 is identical with the size of the second end 232.The connection
The size of conductor wire 230 of the first end 231 of key 203 is identical with the size of conductor wire 230 at the second end 232.Wherein, the conductor wire
230 a diameter of 30 microns~150 microns, the thickness of the protective layer 233 is 10 nanometers~10 microns;When the conductor wire 230
Material when being copper, the minimum diameter of the conductor wire 230 is 30 microns;It is described when the material of the conductor wire 230 is aluminium
The minimum diameter of conductor wire 230 is 100 microns.
In the present embodiment, the conductor wire 230 is cylinder, i.e., the section of described conductor wire 230 is circular, the company
The end 232 of first end 231 and second for connecing key 203 exposes the cylindrical both ends of conductor wire 230 respectively;The connecting key
203 first ends 231 and the size of conductor wire 230 at the second end 232 are the diameter of the cylindrical conductive line 230.
In the present embodiment, the cylindrical conductor wire 230 is from the diameter of 203 first end of connecting key, 231 to the second end 232
It is identical.
In the present embodiment, the sidewall surfaces of conductor wire 230 are also covered with protective layer 233, and the protective layer 233
Thickness is homogeneous, so as to after the Surface coating protective layer 233 of conductor wire 230, the connecting key 203 from first end 231 to
The size at the second end 232 is still identical.
In other embodiments, the size at the second end of the connecting key can also be less than the size of the first end.
The forming step of the connecting key is illustrated below with reference to accompanying drawing.
It refer to Fig. 6, there is provided initial conduction line 300, the initial conduction line 300 have the 3rd end 301 and the 4th end
302。
The initial conduction line 300 forms conductor wire 230 (as shown in Figure 5) for cutting.The initial conduction line 300
Material is conductive material;It is copper, tungsten, aluminium, gold or silver that the conductive material, which includes,.
In the present embodiment, the initial conduction line 300 is cylinder, i.e., the section of described initial conduction line 300 is circle
Shape;And size of the initial conduction line 300 from the end 302 of the 3rd end 301 to the 4th is identical, i.e., described cylindrical conductor wire
300 diameter from the end 302 of the 3rd end 301 to the 4th is identical.
Fig. 7 is refer to, initial protective layers 303 is formed in the sidewall surfaces of the initial conduction line 300, forms initial connection
Key 310, the initial protective layers 303 expose the 3rd end 301 and the 4th end 302 of the initial conduction line 300.
The formation process of the initial protective layers 303 includes chemical vapor deposition method, physical gas-phase deposition, atom
Layer depositing operation, spraying coating process or Shooting Technique.
The material of the initial protective layers 303 is insulating materials;The insulating materials is organic insulation or inorganic exhausted
Edge material.
In one embodiment, when the material of the initial protective layers 303 is organic insulation, the organic insulation
Including polyvinyl chloride or resin;The resin includes epoxy resin, polyimide resin, benzocyclobutane olefine resin or polyphenyl and disliked
Azoles resin;The formation process of the initial protective layers 303 can be spraying coating process or Shooting Technique.
In another embodiment, the material of the initial protective layers 303 is inorganic insulating material, the inorganic insulating material
Including the one or more in silica, silicon nitride and silicon oxynitride;The formation process of the initial protective layers 303 being capable of chemistry
Gas-phase deposition, physical gas-phase deposition, atom layer deposition process;And the technique for forming the initial protective layers 303 needs
There is good covering power and uniformity, formed initial protective layers 303 is evenly covered on described first
The surface of beginning conductor wire 300.
Fig. 8 is refer to, it is described initial along being cut perpendicular to the direction of initial conduction line 300 (as shown in Figure 7) side wall
Protective layer 303 (as shown in Figure 7) and initial conduction line 300 (as shown in Figure 7), form some sections of conductor wires 230 and positioned at leading
The protective layer 233 of the sidewall surfaces of electric wire 230.
In the present embodiment, the sidewall surfaces of the initial conduction line 300 are around the axis A (as shown in Figure 7)
Surface, the axis A are the central shaft by the 3rd end 301 and the 4th end 302 in the initial conduction line 300;Along perpendicular to
The direction cutting of the side wall of initial conduction line 300 is along perpendicular to the axis A direction cutting initial protective layers 303 and just
Beginning conductor wire 300.
The cutting technique can be laser cutting parameter.After cutting technique, the initial protective layers 303 and just
Beginning conductor wire 300 forms some discrete connecting keys 203.
Fig. 9 is refer to, forms plastic packaging layer 204 on the surface of carrier 200, the plastic packaging layer 204 surrounds the chip 201
With connecting key 203, the surface of the plastic packaging layer 204 exposes the second end 232 and the function of chip 201 of the connecting key 203
Area surface.
In the present embodiment, the surface of the plastic packaging layer 204 and the top of projection 221 of the second surface 220 of chip 201
Surface flushes, i.e., described plastic packaging layer 204 exposes the top surface of the projection 221.Due to the second end of the connecting key 203
232 are higher than or are flush to the top surface of the projection 221, so as to make the plastic packaging layer 204 expose the connecting key
203 the second end 232.Electrical connection between connecting key 203 and projection 221 subsequently can be realized by forming again wiring layer.
The surface for being additionally, since the plastic packaging layer 204 flushes with the top surface of projection 221, the thickness of the plastic packaging layer 204
, the thinner thickness of the plastic packaging layer 204 identical with the thickness of chip 201 is spent, the thickness gauge of formed encapsulating structure can be made
It is very little smaller.
In the present embodiment, the forming step of the plastic packaging layer 204 includes:Covering institute is formed on the surface of carrier 200
State the initial plastic packaging layer of the projection 221 on chip 201 and chip 201;The initial plastic packaging layer is polished, until exposure
Untill the top surface for going out the projection 221, the plastic packaging layer 204 is formed.
The plastic packaging layer 204 can be photosensitive dry film, non-photo-sensing dry film or capsulation material film.
In one embodiment, the plastic packaging layer 204 is photosensitive dry film, and the formation process of the initial plastic packaging layer is pasted for vacuum
Membrane process.
In another implementation, the material of the plastic packaging layer 204 is capsulation material, the capsulation material include epoxy resin,
It is polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, makrolon, poly- to benzene
Naphthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, second
Alkene-acetate ethylene copolymer, polyvinyl alcohol or other suitable polymeric materials.
The formation process of the initial plastic packaging layer includes Shooting Technique (injection molding), turns modeling technique
(transfer molding) or silk-screen printing technique.The Shooting Technique includes:Mould is provided;Filling modeling in the mold
Closure material, the capsulation material is set to coat the chip 201 and connecting key 203;Elevated cure, shape are carried out to the capsulation material
Into plastic packaging layer 204.
In other embodiments, the material of the plastic packaging layer 204 can also be other insulating materials.
Subsequently formed on the surface of plastic packaging layer 204 and electrically connected with the end 232 of connecting key 203 second and projection 221
Wiring layer again.In one embodiment, the wiring layer again can be formed directly into the surface of plastic packaging layer 204.In this implementation
In example, the first insulating barrier can be formed on the surface of plastic packaging layer 204 and then is connected up again in the formation of the first surface of insulating layer
Layer;Illustrated below with reference to accompanying drawing.
Figure 10 is refer to, the first insulating barrier 205 is formed on the surface of plastic packaging layer 204, is had in first insulating barrier 205
Have some the first of the conductor wire 230 for exposing the end 232 of connecting key 203 second respectively and the functional areas surface of chip 201
Through hole 206.
First insulating barrier 205 is used to protect the surface of plastic packaging layer 204;First in first insulating barrier 205
The wiring layer again that through hole 206 is used to enable to be subsequently formed electrically connects with conductor wire 230 and projection 221.
The forming step of first insulating barrier 205 includes:In the plastic packaging layer 204, connecting key 203 and the table of projection 221
Face forms the first dielectric film;First dielectric film is patterned, forms the first insulating barrier 205, and first insulation
There is first through hole 206 in layer 205.
In one embodiment, the material of first insulating barrier 205 is polymeric material or inorganic insulating material;It is described poly-
Compound material can be insulating resin;The inorganic insulating material can be silica, silicon nitride, one kind in silicon oxynitride or
Multiple combinations.
The technique being patterned to first dielectric film includes:Using coating process and exposure imaging technique first
Insulating film surface forms patterned photoresist layer;First dielectric film is etched with the photoresist layer.
The technique for etching first dielectric film is anisotropic dry etch process;The anisotropic dry method is carved
The etching gas of etching technique include CH4、CHF3、CH3One or more in F, bias power are more than 100 watts, and bias voltage is more than
10 volts.
In another embodiment, the material of the first insulating barrier 205 is photoresist, and the first through hole 206 uses photoetching work
Skill is formed.
Figure 11 is refer to, in the first through hole 206 (as shown in Figure 10) and the surface shape of the first insulating barrier of part 205
Into wiring layer 207 again, the wiring layer again 207 electrically connects with the second end 232 of the connecting key 203 and projection 221.
The forming step of described wiring layer again 207 includes:In the first through hole 206 and the first insulating barrier 205
Surface forms conducting film, the full first through hole 206 of conducting film filling;Planarize the conducting film;In flatening process
Afterwards, patterned layer, the patterned layer covering part conducting film are formed on the conducting film surface;Using the patterned layer as
Mask, the conducting film is etched, untill the surface of the first insulating barrier 205 is exposed;After the conducting film is etched, remove
The patterned layer.
The material of the conducting film includes the one or more in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride, silver;Carve
The technique for losing the conducting film is anisotropic dry etch process or wet processing;The patterned layer can be figure
The photoresist layer of change, additionally it is possible to be patterned hard mask, the material of the hard mask is silica, silicon nitride, silicon oxynitride
In one kind or it is a variety of;The flatening process can be CMP process.
The wiring layer again 207 can be single layer structure or sandwich construction, the cloth again of the single layer structure or sandwich construction
Line layer 207 is used to realize specific circuit function.In the present embodiment, the wiring layer again 207 is single layer structure.In other realities
Apply in example, the wiring layer again can be sandwich construction, and be electrically isolated between adjacent two layers wiring layer with insulating barrier.
Figure 12 is refer to, in the second insulating barrier 208 of the surface of wiring layer again 207 formation, second insulating barrier 208
With the second through hole 280 for exposing partly again wiring layer 207.
Second insulating barrier 208 is solder mask, and second insulating barrier 208 is used for described in protective layer in wiring layer 207,
And the second through hole 280 in second insulating barrier 208 is used for the position for the first soldered ball that definition is subsequently formed.
The forming step of second insulating barrier 208 includes:Formed on the surface of 207 and first insulating barrier of wiring layer 205 again
Second dielectric film;Second dielectric film is patterned, forms the second insulating barrier 208, and in second insulating barrier 208
With second through hole 280.
In one embodiment, the material of second insulating barrier 208 is polymeric material or inorganic insulating material;It is described poly-
Compound material can be insulating resin;The inorganic insulating material can be silica, silicon nitride, one kind in silicon oxynitride or
Multiple combinations.
The technique being patterned to second dielectric film includes:Using coating process and exposure imaging technique second
Insulating film surface forms patterned photoresist layer;First dielectric film is etched with the photoresist layer.
The technique for etching second dielectric film is anisotropic dry etch process;The anisotropic dry method is carved
The etching gas of etching technique include CH4、CHF3、CH3One or more in F, bias power are more than 100 watts, and bias voltage is more than
10 volts.
In another embodiment, the material of the second insulating barrier 208 is photoresist, and second through hole 208 uses photoetching work
Skill is formed.
Figure 13 is refer to, first soldered ball 281 is formed in second through hole 280 (as shown in figure 12).
The material of first soldered ball 281 includes tin.The forming step of first soldered ball 281 includes:Described second
The surface printing tin cream of wiring layer again 207 of the bottom of through hole 280, then high temperature reflux is carried out, under surface tension effects, form first
Soldered ball 281.
In another embodiment, additionally it is possible to which first the surface printing of wiring layer 207 helps weldering to the electricity in the bottom of two through hole 280 again
Agent and soldered ball particle, then high temperature reflux form the first soldered ball 281.In other embodiments, additionally it is possible in wiring layer 207 again
Upper electrotinning post, then high temperature reflux form the first soldered ball 281.
In one embodiment, between the wiring layer again 207 and first soldered ball 281, additionally it is possible to which there is gold under ball
Belong to structure (Under Ball Metal, abbreviation UBM);Metal structure can include single metal layer or multiple-layer overlapped under the ball
Metal level;The material of the single metal layer or more metal layers includes the one or more in copper, aluminium, nickel, cobalt, titanium, tantalum
Combination.
Figure 14 is refer to, after first soldered ball 281 is formed, removes the carrier 200 (as shown in figure 13), exposure
Go out the first end 231 of the connecting key 203.
In the present embodiment, the surface global of the carrier 200 covering tack coat, and the material of the tack coat is UV glue,
The chip 201 and connecting key 203 are fixed by the tack coat and the carrier 200, and the plastic packaging layer 204 is formed at institute
State tie layer surface.By carrying out ultraviolet light to the tack coat, make the viscosity reduction of tack coat;Again by the carrier
200 from the first surface 210 of chip 201, the first end 231 of connecting key 203 and the sur-face peeling of plastic packaging layer 204, so as to expose
The first end 231 of the first surface 210 of chip 201 and connecting key 203.After the carrier 200 is peeled off, carry out cleaning with
Remove the tack coat of residual.
In other embodiments, additionally it is possible to which the carrier 200 is removed by etching technics or CMP process.
Figure 15 is refer to, after the carrier 200 (as shown in figure 13) is removed, in the first end 231 of connecting key 203
The surface of conductor wire 230 formed the second soldered ball 209.
Formed after second soldered ball 209, that is, realize the two-sided plant ball of formed encapsulating structure, the encapsulating structure
Both side surface can realize stacked package with other packaging bodies.
The material of second soldered ball 209 includes tin.The forming step of second soldered ball 209 includes:In the connection
The surface printing tin cream of conductor wire 230 of the first end 231 of key 203, then carry out high temperature reflux, under surface tension effects, form the
Two soldered balls 209.
In another embodiment, additionally it is possible to first helped in the surface printing of conductor wire 230 of the first end 231 of connecting key 203
Solder flux and soldered ball particle, then high temperature reflux form the second soldered ball 209.In other embodiments, additionally it is possible in the connecting key 203
The electroplating surface tin post of conductor wire 230 of first end 231, then high temperature reflux form the second soldered ball 209.
In another embodiment, Figure 16 is refer to, after the second soldered ball 209 is formed, in addition to:Packaging body 400 is provided,
The packaging body 400 has the 3rd surface 401, and the 3rd surface 401 of the packaging body 400 exposes conductive structure 402;Make institute
The first surface 210 and the surface of plastic packaging layer 204 and the 3rd surface 401 of the packaging body 400 for stating chip 201 are oppositely arranged, and
Second soldered ball 209 is set to be connected with each other with the conductive structure 402 by welding procedure.
There is chip or semiconductor devices, and the chip or semiconductor devices and the conduction in the packaging body 400
Structure 402 electrically connects.Because the conductive structure 402 is electrically connected by the second soldered ball 209 and connecting key 203 with chip 201, from
And can realize that the chip in packaging body 400 or semiconductor devices electrically connect with the chip 201, stacked chips envelope is formed with this
Assembling structure, and that formed is packaging body stacked structure (Package On Package, abbreviation POP).
To sum up, it is directly solid in the carrier surface of chip circumference before plastic packaging layer is formed in the forming method of the present embodiment
Determine connecting key.Wherein, the connecting key includes conductor wire, and the first end of the connecting key and the second end expose conduction
Line;After the first end fixation by the connecting key and carrier surface, the second end of the connecting key can be higher than or flush
In the functional surfaces of the chip, therefore, after the carrier surface forms and exposes the plastic packaging floor in chip functions area, the company
The plastic packaging layer surface can be also higher than or be flush to by connecing the second end of key, so as to which the conductor wire can be from the plastic packaging layer
Surface is through to carrier surface, so as to the electrical connection of follow-up chip first surface to second surface.Because the connecting key is direct
Carrier surface is fixed on, avoids the step of being handled in plastic packaging layer, can simplify the forming method of encapsulating structure.And
And the connecting key is directly fixed on carrier surface, the connecting key can be made more accurate relative to the position of the chip
And be easy to regulate and control, not only contribute to ensure the accurate size of formed encapsulating structure, and be advantageous to the cloth again being subsequently formed
Line layer is realized with the second end of the connecting key and electrically connected.Therefore, the forming method processing step simplification of the encapsulating structure, work
Skill cost reduces, technology difficulty reduces, and the size of the encapsulating structure formed is more accurate, is advantageous to reduce encapsulating structure
Size.
Accordingly, the present embodiment also provides a kind of encapsulating structure formed using the above method, please continue to refer to Figure 15,
Including:
Plastic packaging layer 204, the plastic packaging layer 204 have relative the 5th surface and the 6th surface;
Chip 201 in the plastic packaging layer 204, the chip 201 have the relative table of first surface 210 and second
Face 220, the second surface 220 of the chip 201 include functional areas, the first surface 210 of the chip 201 and the plastic packaging layer
204 the 5th surface flushes;
Through the connecting key 203 of the plastic packaging layer 204, the connecting key 203 is located at around the chip 201, the company
Connecing key 204 includes conductor wire 230, and the connecting key 230 includes the end 232 of first end 231 and second, and the of the connecting key 203
The end 232 of one end 231 and second exposes the conductor wire 230, and the of the first end 231 of the connecting key 203 and plastic packaging layer 204
Five surfaces flush, and the second end 232 of the connecting key 203 is higher than or be flush to the 6th surface of the plastic packaging layer 204;
Wiring layer again 207 positioned at the surface of plastic packaging layer 204 the 6th, the wiring layer again 207 and the connecting key 203
The second end 232 and chip 201 functional areas electrical connection;
The first soldered ball 281 positioned at the surface of wiring layer again 207.
Illustrated below with reference to accompanying drawing.
The chip 201 can be sensor chip, logic circuit chip, storage chip etc..The table of chip 201 second
Can have transistor, passive device (such as resistance, electric capacity and inductance etc.), memory device, sensing in the functional areas in face 220
One or more of device, electric interconnection structure.
In the present embodiment, the functional areas surface of the chip 201 exposes pad;The bond pad surface has projection
The top surface of 221 projections 221 protrudes from the second surface 220 of the chip 201.The projection 221 can be with function
Circuit or device in area realize electrical connection.The projection 221 is used to electrically connect with connecting key 203, so as to realize chip 201
Electrical connection between functional areas and other chips or external circuit.In the present embodiment, the functional areas surface of the chip 201 is
The top surface of the projection 221, the plastic packaging layer 204 expose the top surface of the projection 221.In other embodiments
In, the functional areas can also be sensor region, have sensor in the sensor region, and the sensor is used to obtain
Information in external environment condition.
One or several connecting keys 203 are fixed around a chip 201;Connecting key around a chip 201
When 203 quantity are more than 1, the quantity of the connecting key 203 can be consistent with the quantity of projection 221 on the surface of chip 201, and the company
The position for connecing key 203 is corresponding with the position of projection 221 on the surface of chip 201.
In the present embodiment, the distance at 231 to the second end of first end 232 of connecting key 203 is 40 microns~400 micro-
Rice;The distance at 231 to the second end of first end 232 of connecting key 203 is more than or equal to the thickness of the chip 201, the core
The thickness of piece 201 is distance of the top surface of projection 221 to the first surface 210 of chip 201.
The material of the conductor wire 230 is conductive material, and the conductor wire 230 is used to realize chip 201 from first surface
210 to second surface 220 conducting;It is copper, tungsten, aluminium, gold or silver that the conductive material, which includes,.
In the present embodiment, the connecting key 203 also includes the protective layer 233 positioned at the sidewall surfaces of conductor wire 230,
The protective layer 233 exposes the conductor wire 230 at the first end 231 of connecting key 203 and the second end 232.In another embodiment
In, the connecting key can not also include the protective layer, and only have the conductor wire.
The material of the protective layer 233 is insulating materials.The insulating materials is organic insulation or inorganic insulation material
Material;The organic insulation includes polyvinyl chloride or resin;The resin includes epoxy resin, polyimide resin, benzo
Cyclobutane resin or polybenzoxazoles resin;The inorganic insulating material includes one in silica, silicon nitride and silicon oxynitride
Kind is a variety of.
The protective layer 233 can not only be when being fixed on 200 surface of carrier, for protecting described lead by connecting key 203
The surface of electric wire 230 can increase the sectional dimension of the connecting key 203 from damage, so that the connecting key 203
It is more accurate relative to the position of chip 201.
In the present embodiment, the size of first end 231 of the connecting key 203 is identical with the size of the second end 232.The connection
The size of conductor wire 230 of the first end 231 of key 203 is identical with the size of conductor wire 230 at the second end 232.Wherein, the conductor wire
230 a diameter of 30 microns~150 microns, the thickness of the protective layer 233 is 10 nanometers~10 microns;When the conductor wire 230
Material when being copper, the minimum diameter of the conductor wire 230 is 30 microns;It is described when the material of the conductor wire 230 is aluminium
The minimum diameter of conductor wire 230 is 100 microns.
In the present embodiment, the conductor wire 230 is cylinder, i.e., the section of described conductor wire 230 is circular, the company
The end 232 of first end 231 and second for connecing key 203 exposes the cylindrical both ends of conductor wire 230 respectively;The connecting key
203 first ends 231 and the size of conductor wire 230 at the second end 232 are the diameter of the cylindrical conductive line 230.In the present embodiment
In, the cylindrical conductor wire 230 is identical from 203 first end of connecting key, 231 to the second end, 232 diameters.
In the present embodiment, the sidewall surfaces of conductor wire 230 are also covered with protective layer 233, and the protective layer 233
Thickness is homogeneous, so as to after the Surface coating protective layer 233 of conductor wire 230, the connecting key 203 from first end 231 to
The size at the second end 232 is still identical.In other embodiments, the size at the second end of the connecting key can also be less than described
The size of first end.
In the present embodiment, the surface of the plastic packaging layer 204 and the top of projection 221 of the second surface 220 of chip 201
Surface flushes, because the second end 232 of the connecting key 203 is higher than or is flush to the top surface of the projection 221, so as to
The plastic packaging layer 204 is enough set to expose the second end 232 of the connecting key 203.It is additionally, since the surface of the plastic packaging layer 204
Flushed with the top surface of projection 221, the thickness of the plastic packaging layer 204 is identical with the thickness of chip 201, the plastic packaging layer 204
Thinner thickness, the thickness of encapsulating structure can be made smaller.
The plastic packaging layer 204 can be photosensitive dry film, non-photo-sensing dry film or capsulation material film.It is described in one implements
The material of plastic packaging layer 204 is capsulation material, and the capsulation material includes epoxy resin, polyimide resin, benzocyclobutene tree
It is fat, polybenzoxazoles resin, polybutylene terephthalate, makrolon, polyethylene terephthalate, polyethylene, poly-
Propylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol
Or other suitable polymeric materials.
The encapsulating structure of the present embodiment also includes:The first insulating barrier 205 positioned at the surface of plastic packaging layer 204 the 6th, institute
Stating in the first insulating barrier 205 has the conductor wire 230 and chip 201 for exposing the end 232 of connecting key 203 second respectively
Some first through hole on functional areas surface;The wiring layer again 207 is located in the first through hole and the insulating barrier of part first
205 surfaces.
First insulating barrier 205 is used to protect the surface of plastic packaging layer 204;First in first insulating barrier 205
Through hole is used to enable again wiring layer 207 electrically connect with conductor wire 230 and projection 221.In one embodiment, described first is exhausted
The material of edge layer 205 is polymeric material or inorganic insulating material;The polymeric material can be insulating resin;It is described inorganic
Insulating materials can be one or more combinations in silica, silicon nitride, silicon oxynitride.In another embodiment, first is exhausted
The material of edge layer 205 is photoresist.
The material of the wiring layer again 207 includes one kind or more in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride, silver
Kind.The wiring layer again 207 can be single layer structure or sandwich construction, the wiring layer again of the single layer structure or sandwich construction
207 are used to realize specific circuit function.In the present embodiment, the wiring layer again 207 is single layer structure.In other embodiments
In, the wiring layer again can be sandwich construction, and be electrically isolated between adjacent two layers wiring layer with insulating barrier.
The encapsulating structure of the present embodiment also includes:The second insulating barrier 208 positioned at the surface of wiring layer again 207, it is described
There is the second through hole for exposing partly again wiring layer 207 in second insulating barrier 208;First soldered ball 281 is positioned at described the
In two through holes.
Second insulating barrier 208 is solder mask, and second insulating barrier 208 is used for described in protective layer in wiring layer 207,
And position of the second through hole 280 in second insulating barrier 208 for defining first soldered ball 281.In one embodiment,
The material of second insulating barrier 208 is polymeric material or inorganic insulating material;The polymeric material can be insulation tree
Fat;The inorganic insulating material can be one or more combinations in silica, silicon nitride, silicon oxynitride.In another implementation
In example, the material of the second insulating barrier 208 is photoresist.
The encapsulating structure of the present embodiment also includes:Positioned at the surface of conductor wire 230 of the first end 231 of connecting key 203
Second soldered ball 209.The material of first soldered ball 281 includes tin;The material of second soldered ball 209 includes tin.
In one embodiment, between the wiring layer again 207 and first soldered ball 281, additionally it is possible to which there is gold under ball
Belong to structure (Under Ball Metal, abbreviation UBM);Metal structure can include single metal layer or multiple-layer overlapped under the ball
Metal level;The material of the single metal layer or more metal layers includes the one or more in copper, aluminium, nickel, cobalt, titanium, tantalum
Combination.
In the present embodiment, the encapsulating structure can also include carrier 200 (as shown in figure 13), the chip 201
The first end 231 of first surface 210, the 5th surface of the plastic packaging layer 204 and the connecting key 203 is fixed on the load
The surface of body 200.
In the present embodiment, the carrier 200 is rigid substrate, and the rigid substrate is PCB substrate, glass substrate, gold
Belong to substrate, semiconductor substrate or polymeric substrates.The rigid substrate has higher hardness, is not susceptible to deformation, it is sufficient to prop up
Support core piece and plastic packaging layer.In other embodiments, the carrier can also be flexible base plate.
The first surface 210 of the chip 201 is fixed on the surface of carrier 200 by tack coat;The connecting key 203
First end logical 231 cross tack coats and be fixed on the surface of carrier 200.The material of the tack coat is UV glue, the UV glue warp
Viscosity reduces after ultraviolet irradiation, is easy to peel off carrier 200 from encapsulating structure.
In another embodiment, Figure 16 is refer to, the encapsulating structure also includes:Packaging body 400, the packaging body 400
With the 3rd surface 401, the 3rd surface 401 of the packaging body 400 exposes conductive structure 402;The first of the chip 201
Surface 210 and the surface of plastic packaging layer 204 and the 3rd surface 401 of the packaging body 400 are oppositely arranged, and the conductive structure 402 is logical
Second soldered ball 209 is crossed to be connected with each other with the connecting key 203.
There is chip or semiconductor devices, and the chip or semiconductor devices and the conduction in the packaging body 400
Structure 402 electrically connects.Because the conductive structure 402 is electrically connected by the second soldered ball 209 and connecting key 203 with chip 201, from
And can realize that the chip in packaging body 400 or semiconductor devices electrically connect with the chip 201, the encapsulating structure is stacking
The encapsulating structure of chip, i.e. packaging body stacked structure (Package On Package, abbreviation POP).
To sum up, in the structure of the present embodiment, key, the connecting key are directly fixedly connected with the carrier surface of chip circumference
Including conductor wire, and the first end of the connecting key and the second end expose conductor wire, and the connecting key runs through the modeling
Sealing, i.e., described conductor wire can be through to the 6th surface from the 5th surface of the plastic packaging layer, the table of chip first realized with this
Face to second surface electrical connection.Moreover, the connecting key and chip are directly fixed in the plastic packaging layer, make the connecting key
It is more accurate relative to the position of the chip and be easy to regulate and control, not only contribute to ensure the accurate size of encapsulating structure, and
Be advantageous to avoid in wiring layer relative to generation position skew between the connecting key or chip.Therefore, the encapsulating structure
Simple in construction, manufacturing cost reduces, and the size of the encapsulating structure is more accurate, is advantageous to reduce the chi of encapsulating structure
It is very little.
Figure 17 to Figure 20 is the cross-sectional view of the forming process of the encapsulating structure of another embodiment of the present invention.
It refer to Figure 17, there is provided carrier 500;In the surface fixed chip 501 of carrier 500, the chip 501 has phase
To first surface 510 and second surface 520, the second surface 520 of the chip 501 includes functional areas (not shown), described
The first surface 510 of chip 501 interfixes with the surface of carrier 500;The surface of carrier 500 around the chip 501 is fixed
Connecting key 503, the connecting key 503 include conductor wire 530, and the connecting key 530 includes the end 532 of first end 531 and second, institute
The end 532 of first end 531 and second for stating connecting key 503 exposes the conductor wire 530, the first end 531 of the connecting key 503
Interfixed with the surface of carrier 500, the second end 532 of the connecting key 503 is higher than or be flush to the work(of the chip 501
Can area surface.
The carrier 500, the chip 501, in the technique of the surface fixed chip 501 of carrier 500 and in carrier 500
The technique that surface is fixedly connected with key 503 is identical with the related content of previous embodiment, will not be described here.
In the present embodiment, the connecting key 503 also includes the protective layer 533 positioned at the sidewall surfaces of conductor wire 530,
The protective layer 533 exposes the conductor wire 530 at the first end 531 of connecting key 503 and the second end 532.
The material of the protective layer 533 is insulating materials.The insulating materials is organic insulation or inorganic insulation material
Material;The organic insulation includes polyvinyl chloride or resin;The resin includes epoxy resin, polyimide resin, benzo
Cyclobutane resin or polybenzoxazoles resin;The inorganic insulating material includes one in silica, silicon nitride and silicon oxynitride
Kind is a variety of.
In the present embodiment, the size of first end 531 of the connecting key 503 is more than the second end 532 of the connecting key 503
Size.Moreover, the side wall of the connecting key 503 tilts relative to the surface of the first end 531 of connecting key 503, the connecting key
Acute angle between 503 sidewall surfaces and the surface of the first end 531 is 75 °~89 °.
In the present embodiment, the conductor wire 530 is cylinder, i.e., the section of described conductor wire 530 is circular, the company
The end 532 of first end 531 and second for connecing key 503 exposes the cylindrical both ends of conductor wire 530 respectively;The connecting key
503 first ends 531 and the size of conductor wire 530 at the second end 532 are the diameter of the cylindrical conductive line 530.
In the present embodiment, the cylindrical conductor wire 530 is from the diameter phase of 503 first end of connecting key, 531 to the second end 532
Together.
In the present embodiment, the sidewall surfaces of conductor wire 530 are also covered with protective layer 533, and positioned at connecting key 503 the
The thickness of protective layer 533 of one end 531 is more than the thickness of protective layer 533 positioned at the second end 532, so that the connecting key 503
The size of first end 531 is more than the size of the second end 532 of the connecting key 503.
Because the first end 531 of the connecting key 503 is fixed on the surface of carrier 500 by tack coat, when the connecting key
When 531 size of first end 531 is more than the second 532 size of end, fixation of the connecting key 503 on the surface of carrier 500 is more steady
Fixed, during plastic packaging layer is subsequently formed, the connecting key 503 is not susceptible to displacement, advantageously ensures that the connecting key 503
Position relative to chip 500 is accurate.
And the conductor wire 530 in the connecting key 503 is identical from 503 first end of connecting key, 531 to the second end, 532 diameters,
It is smaller from the end 532 of 503 first end of connecting key 531 to the second, the resistivity contrasts of the conductor wire 530 so that the conductor wire
530 electric performance stablity.
The forming step of the connecting key is illustrated below with reference to accompanying drawing.
It refer to Figure 18, there is provided initial conduction line 600, the initial conduction line 600 have the 3rd end 601 and the 4th end
602;Initial protective layers 603 are formed in the sidewall surfaces of the initial conduction line 600, form initial connecting key 610, it is described initial
Protective layer 601 exposes the 3rd end 601 and the 4th end 602 of the initial conduction line 600.
In the present embodiment, it is described first from the direction at the end 602 of the 3rd end 601 to the 4th of the initial conduction line 600
Beginning connecting key 600 has some cut length 620, and each cut length 620 is respectively provided with close to the 5th end 621 at the 3rd end 601 and leaned on
6th end 622 at nearly 4th end 602;The thickness of initial protective layers 603 at the end 621 of the cut length 620 the 5th is more than cut length the
The thickness of initial protective layers 603 at six ends 622.
The formation process of the initial protective layers 603 is Shooting Technique.The forming step bag of the initial protective layers 603
Include:Diaphragm is formed on the surface of initial conduction line 600 using coating process;The diaphragm is moulded using mould
Shape, form the initial protective layers 603.
Wherein, the inner wall surface pattern of the mould is identical with the surface topography of the initial protective layers 603 of required formation, from
And by the moulding of the mould, the thickness of protective layer 603 can be made to produce difference, the surface of protective layer 603 is serrated.
The material of the protective layer 233 is organic insulation;The organic insulation includes polyvinyl chloride or resin;
The resin includes epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
Figure 19 is refer to, it is described first along being cut perpendicular to the direction of initial conduction line 600 (as shown in figure 18) side wall
Beginning protective layer 603 (as shown in figure 18) and initial conduction line 601 (as shown in figure 18), form some sections of conductor wires 530, Yi Jiwei
In the protective layer 533 of the sidewall surfaces of conductor wire 530.
After the initial connecting key 610 (as shown in figure 18) is cut, some cut length 620 (as shown in figure 18) are mutual
Independent, each cut length 620 forms the connecting key 503, and the 5th end 621 (as shown in figure 18) of the cut length 620 turns into
The first end 531 of connecting key 503,622 the second end 532 (as shown in figure 18) as connecting key of the 6th end of the cut length.
In the present embodiment, the sidewall surfaces of the initial conduction line 600 are around the axis B (as shown in figure 18)
Surface, the axis B are the central shaft by the 3rd end 601 and the 4th end 602 in the initial conduction line 600;Along perpendicular to
The direction cutting of the side wall of initial conduction line 600 is along perpendicular to the axis B direction cutting initial protective layers 603 and just
Beginning conductor wire 600.
The cutting technique can be laser cutting parameter.After cutting technique, the initial protective layers 603 and just
Beginning conductor wire 600 forms some discrete connecting keys 503.Moreover, edge of the cutting technique along the cut length 620 enters
OK, so that some cut length 620 can be mutually discrete.
Figure 20 is refer to, forms plastic packaging layer 504 on the surface of carrier 500, the plastic packaging layer 504 surrounds the chip
501 and connecting key 503, the surface of the plastic packaging layer 504 expose the second end 532 and the work(of chip 501 of the connecting key 503
Can area surface;Wiring layer 507 again, the wiring layer again 507 and the connecting key 503 are formed on the surface of plastic packaging layer 504
Second end 532 and the electrical connection of the functional areas of chip 501;The first soldered ball 581 is formed on the surface of wiring layer again 507;In shape
Into after first soldered ball 581, the carrier 500 (as shown in figure 19) is removed, exposes the first end of the connecting key 503
531。
The plastic packaging layer 504, the technique for forming plastic packaging layer 504, the wiring layer again 507, the work for forming again wiring layer 507
Skill, first soldered ball 581, the technique for forming the first soldered ball 581 and the technique and previous embodiment phase that remove carrier 500
Together, will not be described here.
In the present embodiment, it is additionally included in the surface of plastic packaging layer 504 and forms the first insulating barrier 505, first insulation
There is conductor wire 530 and the functional areas surface of chip 501 for exposing the end 532 of connecting key 503 second respectively in layer 505
Some first through hole;The functional areas surface of chip 501 is the top surface of the projection 521 on chip 501.Described
In the first through hole and surface of the first insulating barrier of part 505 forms wiring layer 507 again, the wiring layer again 507 with it is described
Second end 532 of connecting key 503 and projection 521 electrically connect.
In the present embodiment, it is additionally included in the surface of wiring layer 507 again and forms the second insulating barrier 508, described second is exhausted
There is the second through hole for exposing partly again wiring layer 507 in edge layer 508;First soldered ball is formed in second through hole
581。
In addition, after the carrier 500 is removed, additionally it is possible in the conductor wire 530 of the first end 531 of connecting key 503
Surface forms the second soldered ball.
Moreover, after the second soldered ball is formed, in addition to:Packaging body is provided, the packaging body has the 3rd surface, described
3rd surface of packaging body exposes conductive structure;Make first surface 510 and the surface of plastic packaging layer 504 and the institute of the chip 501
The 3rd surface for stating packaging body is oppositely arranged, and second soldered ball is mutually interconnected with the conductive structure by welding procedure
Connect.
Accordingly, the present embodiment also provides a kind of encapsulating structure formed using the above method, please continue to refer to Figure 20,
Including:
Plastic packaging layer 504, the plastic packaging layer 504 have relative the 5th surface and the 6th surface;
Chip 501 in the plastic packaging layer 504, the chip 501 have the relative table of first surface 510 and second
Face 520, the second surface 520 of the chip 501 include functional areas, the first surface 510 of the chip 501 and the plastic packaging layer
504 the 5th surface flushes;
Through the connecting key 503 of the plastic packaging layer 504, the connecting key 503 is located at around the chip 501, the company
Connecing key 504 includes conductor wire 530, and the connecting key 530 includes the end 532 of first end 531 and second, and the of the connecting key 503
The end 532 of one end 531 and second exposes the conductor wire 530, and the of the first end 531 of the connecting key 503 and plastic packaging layer 504
Five surfaces flush, and the second end 532 of the connecting key 503 is higher than or be flush to the 6th surface of the plastic packaging layer 504;
Wiring layer again 507 positioned at the surface of plastic packaging layer 504 the 6th, the wiring layer again 507 and the connecting key 503
The second end 532 and chip 501 functional areas electrical connection;
The first soldered ball 581 positioned at the surface of wiring layer again 507.
The difference of the encapsulating structure of the present embodiment and the encapsulating structure (as shown in figure 15) of previous embodiment is:The company
The size of first end 531 for connecing key 503 is more than the size of the second end 532 of the connecting key 503.
In the present embodiment, the connecting key 503 also includes the protective layer 533 positioned at the sidewall surfaces of conductor wire 530,
The protective layer 533 exposes the conductor wire 530 at the first end 531 of connecting key 503 and the second end 532.
The material of the protective layer 533 is insulating materials.The insulating materials is organic insulation or inorganic insulation material
Material;The organic insulation includes polyvinyl chloride or resin;The resin includes epoxy resin, polyimide resin, benzo
Cyclobutane resin or polybenzoxazoles resin;The inorganic insulating material includes one in silica, silicon nitride and silicon oxynitride
Kind is a variety of.
In the present embodiment, the size of first end 531 of the connecting key 503 is more than the second end 532 of the connecting key 503
Size.Moreover, the side wall of the connecting key 503 tilts relative to the surface of the first end 531 of connecting key 503, the connecting key
Acute angle between 503 sidewall surfaces and the surface of the first end 531 is 75 °~89 °.
In the present embodiment, the conductor wire 530 is cylinder, i.e., the section of described conductor wire 530 is circular, the company
The end 532 of first end 531 and second for connecing key 503 exposes the cylindrical both ends of conductor wire 530 respectively;The connecting key
503 first ends 531 and the size of conductor wire 530 at the second end 532 are the diameter of the cylindrical conductive line 530.
In the present embodiment, the cylindrical conductor wire 530 is from the diameter phase of 503 first end of connecting key, 531 to the second end 532
Together.
In the present embodiment, the sidewall surfaces of conductor wire 530 are also covered with protective layer 533, and positioned at connecting key 503 the
The thickness of protective layer 533 of one end 531 is more than the thickness of protective layer 533 positioned at the second end 532, so that the connecting key 503
The size of first end 531 is more than the size of the second end 532 of the connecting key 503.
To sum up, in the present embodiment, the first end size of the connecting key is more than the second end size of the connecting key.Due to
Carrier surface is fixed at second end of the connecting key, and the first end size of the connecting key is larger, is advantageous to make the company
The fixation that key is connect in carrier surface is more stable, the connecting key can be avoided to be subjected to displacement, so as to ensure that connecting key and core
Relative position between piece is accurate.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (14)
- A kind of 1. encapsulating structure, it is characterised in that including:Plastic packaging layer, the plastic packaging layer have relative the 5th surface and the 6th surface;Chip in the plastic packaging layer, the chip have relative a first surface and second surface, and the of the chip Two surfaces include functional areas, and the first surface of the chip flushes with the 5th surface of the plastic packaging layer;Through the connecting key of the plastic packaging layer, the connecting key is located at the chip circumference, the connecting key include conductor wire with And the protective layer positioned at the conductor wire sidewall surfaces, the protective layer expose leading for the connecting key first end and the second end Electric wire, the material of the protective layer are insulating materials, and the connecting key includes first end and the second end, the first of the connecting key End and the second end expose the conductor wire, and the first end of the connecting key flushes with the 5th surface of plastic packaging layer, the connection Second end of key is higher than or is flush to the 6th surface of the plastic packaging layer;Wiring layer again positioned at the surface of plastic packaging layer the 6th, second end and chip of the wiring layer again with the connecting key Functional areas electrical connection;Positioned at first soldered ball for connecting up layer surface again.
- 2. encapsulating structure as claimed in claim 1, it is characterised in that the insulating materials is organic insulation or inorganic exhausted Edge material;The organic insulation includes polyvinyl chloride;The inorganic insulating material includes silica, silicon nitride and nitrogen oxidation One or more in silicon.
- 3. encapsulating structure as claimed in claim 1, it is characterised in that the first end size of the connecting key is more than the connection Second end size of key.
- 4. encapsulating structure as claimed in claim 1, it is characterised in that the first end size of the connecting key and the second end size It is identical.
- 5. encapsulating structure as claimed in claim 1, it is characterised in that the distance of the connecting key first end to the second end is 40 Micron~400 microns.
- 6. encapsulating structure as claimed in claim 1, it is characterised in that the conductive linear dimension and second of the connecting key first end The conductive linear dimension at end is identical.
- 7. encapsulating structure as claimed in claim 1, it is characterised in that the material of the conductor wire is copper, tungsten, aluminium, gold or silver.
- 8. encapsulating structure as claimed in claim 1, it is characterised in that also include:Carrier, the first surface of the chip, institute State the 5th surface of plastic packaging layer and the first end of the connecting key is fixed on the carrier surface.
- 9. encapsulating structure as claimed in claim 8, it is characterised in that the first surface of the chip is fixed on by tack coat The carrier surface;The first end of the connecting key is fixed on the carrier surface by tack coat.
- 10. encapsulating structure as claimed in claim 1, it is characterised in that the functional areas surface of the chip exposes pad;Institute Stating bond pad surface has projection, and the top surface of the projection protrudes from the second surface of the chip;The plastic packaging layer exposure Go out the top surface of the projection, the top surface of the projection is the functional areas surface of the chip.
- 11. encapsulating structure as claimed in claim 1, it is characterised in that also include:Positioned at the surface of plastic packaging layer the 6th One insulating barrier, first insulating barrier is interior to have the conductor wire and chip functions for exposing the end of connecting key second respectively Some first through hole on area surface;The wiring layer again is located in the first through hole and the surface of insulating layer of part first.
- 12. encapsulating structure as claimed in claim 1, it is characterised in that also include:The second of layer surface is connected up again positioned at described Insulating barrier, second insulating barrier is interior to have the second through hole for exposing partly again wiring layer;First soldered ball is positioned at described In second through hole.
- 13. encapsulating structure as claimed in claim 1, it is characterised in that also include:Positioned at the conduction of the connecting key first end Second soldered ball on line surface.
- 14. encapsulating structure as claimed in claim 13, it is characterised in that also include:Packaging body, the packaging body have the 3rd Surface, the 3rd surface of the packaging body expose conductive structure;The first surface of the chip and plastic packaging layer surface with it is described 3rd surface of packaging body is oppositely arranged, and the conductive structure is connected with each other by second soldered ball and the connecting key.
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US20170098589A1 (en) * | 2015-10-05 | 2017-04-06 | Mediatek Inc. | Fan-out wafer level package structure |
CN108428665B (en) * | 2018-04-09 | 2020-10-30 | 山东汉芯科技有限公司 | Integrated packaging process for laminated chip |
CN112750792A (en) * | 2019-10-30 | 2021-05-04 | 浙江荷清柔性电子技术有限公司 | Packaging structure and flexible integrated packaging method of ultrathin chip |
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CN104332456A (en) * | 2014-09-04 | 2015-02-04 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level fan-out stacked packaging structure and manufacturing process thereof |
CN104538375A (en) * | 2014-12-30 | 2015-04-22 | 华天科技(西安)有限公司 | Fan-out PoP packaging structure and manufacturing method thereof |
CN104600039A (en) * | 2014-12-26 | 2015-05-06 | 南通富士通微电子股份有限公司 | Double-side interconnecting fan-out process |
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US8981559B2 (en) * | 2012-06-25 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
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CN104332456A (en) * | 2014-09-04 | 2015-02-04 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level fan-out stacked packaging structure and manufacturing process thereof |
CN104600039A (en) * | 2014-12-26 | 2015-05-06 | 南通富士通微电子股份有限公司 | Double-side interconnecting fan-out process |
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