CN108428665B - Integrated packaging process for laminated chip - Google Patents
Integrated packaging process for laminated chip Download PDFInfo
- Publication number
- CN108428665B CN108428665B CN201810309452.6A CN201810309452A CN108428665B CN 108428665 B CN108428665 B CN 108428665B CN 201810309452 A CN201810309452 A CN 201810309452A CN 108428665 B CN108428665 B CN 108428665B
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- Prior art keywords
- layer
- chip
- forming
- substrate
- hard metal
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- 238000012858 packaging process Methods 0.000 title claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 239000010410 layer Substances 0.000 claims description 113
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 229910052802 copper Inorganic materials 0.000 claims description 27
- 239000010949 copper Substances 0.000 claims description 27
- 238000005553 drilling Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 239000002356 single layer Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000000608 laser ablation Methods 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 238000000429 assembly Methods 0.000 claims description 2
- 230000000712 assembly Effects 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a laminated chip integrated packaging process, which utilizes a hard metal layer with larger thickness and hardness to carry through holes above the hard metal layer so as to prevent collapse; the upper second through hole and the upper third through hole do not correspond to the lower plug position, so that the collapse is further prevented; in addition, the hard metal layer can be used as an interconnection structure, the side surface of the hard metal layer can independently bear the function of electric connection, and the fact that even when more chips need to be electrically interconnected is achieved, larger surface area of the metal block is not needed.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to a laminated chip integrated packaging process.
Background
After chips are formed on a substrate or a wafer, subsequent steps such as drilling, inter-chip interconnection, and the like are required. For example, in fig. 1, after a chip on a substrate 1 is electrically connected to a pad 4 through a redistribution layer, it is necessary to form a through hole 5 in an insulating layer 2 on the pad 4 to realize a conductive lead-out terminal above the substrate 1, and also to form a via hole 3 below the pad 4, which may cause the pad 4 to be recessed downward due to the presence of the via hole 3, and may cause poor electrical connection of the through hole 5 above or a defective position such as the recessed portion 5, which is not favorable for subsequent packaging. Therefore, there is a need for an interconnect scheme that prevents dishing from occurring while addressing the flexible design of electrical interconnects for multiple chips at the wafer level.
Disclosure of Invention
Based on solving the above problems, the present invention provides a stacked chip integrated package process, which comprises the following steps:
(1) providing a chip substrate, wherein the substrate at least comprises a first chip and a second chip on an active surface of the substrate, and a plurality of electrode pads coplanar with the active surface are arranged on the first chip and the second chip;
(2) depositing a first dielectric layer on the active surface, and drilling and filling in the first dielectric layer to form a plurality of first through holes corresponding to the plurality of electrode pads;
(3) forming a first photoresist layer on the first dielectric layer, forming a first opening in the first photoresist layer, and depositing a thin copper layer on the first opening, wherein the thin copper layer is only connected with one electrode pad of the first chip and one electrode pad of the second chip;
(4) forming a second photoresist layer on a part of the thin copper layer, forming a second opening between the second photoresist layer and the first photoresist layer, and electroplating the second opening to form a thick copper layer;
(5) removing the first photoresist layer and the second photoresist layer;
(6) forming a third photoresist layer on the active surface and the thick copper layer, wherein the photoresist layer is provided with a third opening, the third opening corresponds to the part covered by the second photoresist, and a hard metal layer is electroplated in the third opening, and the thickness of the hard metal layer is greater than that of the thick copper layer;
(7) removing the third photoresist layer;
(8) depositing a second dielectric layer on the active surface, wherein the dielectric layer covers the hard metal layer and the thick copper layer;
(9) forming a plurality of second through holes in the second dielectric layer, wherein the second through holes are positioned in the annular edge area of the hard metal layer, and forming a bonding pad on the upper surface of the second dielectric layer, and the bonding pad is electrically connected with the second through holes;
(10) drilling the back surface of the substrate to form a blind hole, wherein the blind hole corresponds to the circular central area of the hard metal layer and penetrates through the substrate, the first dielectric layer and the thin copper layer to extend into the hard metal layer;
(11) filling the blind holes with a conductive substance to form conductive holes, and forming a single-layer semiconductor assembly;
(12) a plurality of the single-layer semiconductor assemblies are stacked and welded on the substrate.
According to an embodiment of the invention, the first chip and the second chip are chips formed directly on the chip substrate.
According to an embodiment of the invention, said drilling is performed by mechanical drilling or laser ablation drilling.
According to an embodiment of the present invention, the hard metal layer is an alloy of at least one of W, Co, Mo and at least one of WC, TiC.
According to the embodiment of the invention, the conductive substance filled in the second through hole is copper or aluminum or the like.
According to the embodiment of the invention, the first dielectric layer and the second dielectric layer are made of silicon dioxide or silicon nitride.
According to the embodiment of the invention, the method further comprises the steps of forming a bump on the bonding pad and forming a solder ball at the end part of the through hole.
According to an embodiment of the invention, the active surface faces away from the substrate, only the uppermost semiconductor component facing towards the substrate.
The invention has the following advantages:
(1) the hard metal layer with larger thickness and hardness is used for bearing the through hole above the through hole, so that collapse is prevented;
(2) the upper second through hole and the upper third through hole do not correspond to the lower plug position, so that the collapse is further prevented;
(3) in addition, the hard metal layer can be used as an interconnection structure, the side surface of the hard metal layer can independently bear the function of electric connection, and the fact that even when more chips need to be electrically interconnected is achieved, larger surface area of the metal block is not needed.
Drawings
FIG. 1 is a cross-sectional view of a prior art stacked chip integrated package process;
FIGS. 2 a-2 l are cross-sectional views of the stacked chip integrated package process of the present invention;
fig. 3 is a cross-sectional view of the single layer semiconductor device stack formed in fig. 2.
Detailed Description
Referring to fig. 2 and 3, the stacked chip integrated package process of the present invention includes the following steps:
(1) providing a chip substrate 11, wherein the substrate 11 at least comprises a first chip and a second chip 12 on the active surface thereof, and a plurality of electrode pads 13 coplanar with the active surface are arranged on the first chip and the second chip 12;
(2) depositing a first dielectric layer 14 on the active surface, and drilling and filling a plurality of first through holes 15 corresponding to the plurality of electrode pads 13 in the first dielectric layer 14;
(3) forming a first photoresist layer 16 on the first dielectric layer 14, forming a first opening 17 in the first photoresist layer 16, and depositing a thin copper layer 18 on the first opening 17, wherein the thin copper layer 18 is only used for connecting one electrode pad of the first chip with one electrode pad of the second chip;
(4) forming a second photoresist layer 19 on a portion of the thin copper layer 18, forming a second opening 20 between the second photoresist layer 19 and the first photoresist layer 16, and electroplating a thick copper layer 21 in the second opening 20;
(5) removing the first photoresist layer 16 and the second photoresist layer 19;
(6) forming a third photoresist layer 22 on the active surface and the thick copper layer 21, wherein the third photoresist layer 22 has a third opening corresponding to the portion covered by the second photoresist 19, a hard metal layer 23 is electroplated in the third opening, and the thickness of the hard metal layer 23 is greater than that of the thick copper layer 21;
(7) removing the third photoresist layer 22;
(8) depositing a second dielectric layer 24 on the active surface, wherein the second dielectric layer 24 covers the hard metal layer 23 and the thick copper layer 21;
(9) forming a plurality of second through holes 25 in the second dielectric layer 24, wherein the plurality of second through holes 25 are located in an annular edge area of the hard metal layer 23, and forming a pad 26 on an upper surface of the second dielectric layer 24, and the pad 26 is electrically connected with the plurality of second through holes 25;
(10) drilling the back surface of the substrate 11 to form a blind hole 27, wherein the blind hole 27 corresponds to the circular central area of the hard metal layer 23 and extends into the hard metal layer 23 through the substrate 11, the first dielectric layer 14 and the thin copper layer 18;
(11) filling the blind via 27 with a conductive material to form a conductive via 28, forming a single-layer semiconductor assembly; further comprising the steps of forming bumps 29 on the pads 26 and forming solder balls 30 at the ends of the vias 28.
(12) A plurality of the above single-layer semiconductor devices are stacked and bonded on the substrate 34. A stack 40 is formed, as shown in fig. 3, each including a dielectric layer 35, a substrate layer 36, wherein the two layers are electrically connected by bumps 32, and the lowest semiconductor component is electrically connected to a substrate 34 by solder balls 33. The solder balls 33 are the solder balls 30, and the bumps 32 are the bumps 29.
Wherein the first chip and the second chip are chips directly formed on the chip substrate 11. The drilling is achieved by mechanical drilling or laser ablation drilling. The hard metal layer 23 is an alloy of at least one of W, Co, and Mo and at least one of WC and TiC. The conductive material filled in the second through hole 25 is copper or aluminum. The first and second dielectric layers 16, 26 are made of silicon dioxide or silicon nitride.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (8)
1. A laminated chip integrated packaging process comprises the following steps:
(1) providing a chip substrate, wherein the substrate at least comprises a first chip and a second chip on an active surface of the substrate, and a plurality of electrode pads coplanar with the active surface are arranged on the first chip and the second chip;
(2) depositing a first dielectric layer on the active surface, and drilling and filling in the first dielectric layer to form a plurality of first through holes corresponding to the plurality of electrode pads;
(3) forming a first photoresist layer on the first dielectric layer, forming a first opening in the first photoresist layer, and depositing a thin copper layer on the first opening, wherein the thin copper layer is only connected with one electrode pad of the first chip and one electrode pad of the second chip;
(4) forming a second photoresist layer on a part of the thin copper layer, forming a second opening between the second photoresist layer and the first photoresist layer, and electroplating the second opening to form a thick copper layer;
(5) removing the first photoresist layer and the second photoresist layer;
(6) forming a third photoresist layer on the active surface and the thick copper layer, wherein the third photoresist layer is provided with a third opening, the third opening corresponds to the part covered by the second photoresist, and a hard metal layer is electroplated in the third opening, and the thickness of the hard metal layer is greater than that of the thick copper layer;
(7) removing the third photoresist layer;
(8) depositing a second dielectric layer on the active surface, wherein the second dielectric layer covers the hard metal layer and the thick copper layer;
(9) forming a plurality of second through holes in the second dielectric layer, wherein the second through holes are positioned in the annular edge area of the hard metal layer, and forming a bonding pad on the upper surface of the second dielectric layer, and the bonding pad is electrically connected with the second through holes;
(10) drilling the back surface of the substrate to form a blind hole, wherein the blind hole corresponds to the circular central area of the hard metal layer and penetrates through the substrate, the first dielectric layer and the thin copper layer to extend into the hard metal layer;
(11) filling the blind holes with a conductive substance to form conductive holes, and forming a single-layer semiconductor assembly;
(12) a plurality of the single-layer semiconductor assemblies are stacked and welded on the substrate.
2. The stacked chip integrated package process of claim 1, wherein: the first chip and the second chip are chips directly formed on the chip substrate.
3. The stacked chip integrated package process of claim 1, wherein: the drilling is achieved by mechanical drilling or laser ablation drilling.
4. The stacked chip integrated package process of claim 1, wherein: the hard metal layer is an alloy of at least one of W, Co and Mo and at least one of WC and TiC.
5. The stacked chip integrated package process of claim 1, wherein: and the conductive substance filled in the second through hole is copper or aluminum.
6. The stacked chip integrated package process of claim 1, wherein: the first dielectric layer and the second dielectric layer are made of silicon dioxide or silicon nitride.
7. The stacked chip integrated package process of claim 1, wherein: the method also comprises the steps of forming a bump on the bonding pad and forming a solder ball at the end part of the through hole.
8. The stacked chip integrated package process of claim 1, wherein: the active surface is away from the substrate, and only the semiconductor assembly on the uppermost layer faces the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810309452.6A CN108428665B (en) | 2018-04-09 | 2018-04-09 | Integrated packaging process for laminated chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810309452.6A CN108428665B (en) | 2018-04-09 | 2018-04-09 | Integrated packaging process for laminated chip |
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| Publication Number | Publication Date |
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| CN108428665A CN108428665A (en) | 2018-08-21 |
| CN108428665B true CN108428665B (en) | 2020-10-30 |
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| CN201810309452.6A Active CN108428665B (en) | 2018-04-09 | 2018-04-09 | Integrated packaging process for laminated chip |
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| CN112802939A (en) * | 2021-01-19 | 2021-05-14 | 佛山市国星半导体技术有限公司 | Flip LED chip easy to weld |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7569422B2 (en) * | 2006-08-11 | 2009-08-04 | Megica Corporation | Chip package and method for fabricating the same |
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2018
- 2018-04-09 CN CN201810309452.6A patent/CN108428665B/en active Active
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|---|---|---|---|---|
| CN101345231A (en) * | 2007-07-12 | 2009-01-14 | 东部高科股份有限公司 | Semiconductor chip, method of fabricating the same and stack package having the same |
| CN102569173A (en) * | 2010-12-03 | 2012-07-11 | 三星电子株式会社 | Methods of manufacturing a semiconductor device |
| CN104752320A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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| TW201733041A (en) * | 2016-03-04 | 2017-09-16 | 力成科技股份有限公司 | Wafer level chip scale package having continuous TSV configuration and its fabrication method |
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| CN108428665A (en) | 2018-08-21 |
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Denomination of invention: A laminated chip integrated packaging process Effective date of registration: 20220214 Granted publication date: 20201030 Pledgee: Zaozhuang rural commercial bank Limited by Share Ltd. Yicheng sub branch Pledgor: Shandong Hanxin Technology Co.,Ltd. Registration number: Y2022980001543 |
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Denomination of invention: An integrated packaging process for stacked chips Effective date of registration: 20230213 Granted publication date: 20201030 Pledgee: Zaozhuang rural commercial bank Limited by Share Ltd. Yicheng sub branch Pledgor: Shandong Hanxin Technology Co.,Ltd. Registration number: Y2023980032481 |
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Granted publication date: 20201030 Pledgee: Zaozhuang rural commercial bank Limited by Share Ltd. Yicheng sub branch Pledgor: Shandong Hanxin Technology Co.,Ltd. Registration number: Y2023980032481 |