CN105097728A - Packaging structure - Google Patents

Packaging structure Download PDF

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Publication number
CN105097728A
CN105097728A CN201510373971.5A CN201510373971A CN105097728A CN 105097728 A CN105097728 A CN 105097728A CN 201510373971 A CN201510373971 A CN 201510373971A CN 105097728 A CN105097728 A CN 105097728A
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China
Prior art keywords
connecting key
chip
plastic packaging
layer
conductor wire
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Granted
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CN201510373971.5A
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CN105097728B (en
Inventor
石磊
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Nantong Fujitsu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

A packaging structure comprises a plastic packaging layer with opposite fifth and sixth surfaces, a chip positioned in the plastic packaging layer, a connecting key penetrating through the plastic packaging layer, a re-wiring layer positioned on the sixth surface of the plastic packaging layer, and a first welding ball positioned on the surface of the re-wiring layer, wherein the chip is provided with opposite first and second surfaces, the second surface of the chip comprises a functional region, and the first surface of the chip is flush with the fifth surface of the plastic packaging layer; the connecting key is positioned around the chip and comprises a conductive wire, a first end and a second end, the conductive wire is exposed at the first end and the second end of the connecting key, the first end of the connecting key is flush with the fifth surface of the plastic packaging layer, and the second end of the connecting key is higher than or flush with the sixth surface of the plastic packaging layer; and the re-wiring layer is electrically connected with the second end of the connecting key and the functional region of the chip. The packaging structure is simple, reduced in manufacturing cost, and accurate and reduced in size.

Description

Encapsulating structure
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of encapsulating structure.
Background technology
In the prior art, the connection of chip and external circuit is realized by the mode of metal lead wire bonding (WireBonding), i.e. Wire Bonding Technology.Along with the integrated level of the feature size downsizing of chip and integrated circuit improves, the growth requirement of Wire Bonding Technology no longer applicable technology.
In order to improve the integrated level of chip package, Stacked Die Packaging (stackeddiepackage) technology becomes the main flow of technical development gradually.Stacked Die Packaging technology, also known as three-dimensional packaging technology, the specifically encapsulation technology of stacking at least two chips in same packaging body.Stacked Die Packaging technology can realize the Large Copacity of semiconductor device, multi-functional, the technical need such as small size, low cost, and therefore laminated chips technology obtains flourish in recent years.
To use the memory of stacked package technology, compared to the memory not using Stack Technology, adopt the memory of stacked package technology can have the memory capacity of more than twice.In addition, use stacked package technology more can effectively utilize the area of chip, be applied to the aspect such as the USB flash disk of large memory space, SD card more.
Stacked chips encapsulation technology can be realized by multiple technologies means, such as routing technique, silicon through hole (throughsiliconvia is called for short TSV) technology or plastic packaging through hole (throughmoldingvia is called for short TMV) technology.
But above-mentioned technological means still faces various process technology limit and cost restriction, and, be faced with the problem of further thinning encapsulating structure gauge.
Summary of the invention
The problem that the present invention solves is to provide a kind of encapsulating structure, described encapsulating structure is simple, manufacturing cost reduces, size accurately and reduce.
For solving the problem, the present invention also provides a kind of encapsulating structure, comprising: plastic packaging layer, and described plastic packaging layer has the 5th relative surface and the 6th surface; Be positioned at the chip of described plastic packaging layer, described chip has relative first surface and second surface, and the second surface of described chip comprises functional areas, and the first surface of described chip flushes with the 5th surface of described plastic packaging layer; Run through the connecting key of described plastic packaging layer, described connecting key is positioned at described chip circumference, described connecting key comprises conductor wire, described connecting key comprises first end and the second end, first end and second end of described connecting key expose described conductor wire, the first end of described connecting key flushes with the 5th surface of plastic packaging layer, the second end of described connecting key higher than or the 6th surface that flushes in described plastic packaging layer; Be positioned at the wiring layer again on described plastic packaging layer the 6th surface, described wiring layer is again electrically connected with the second end of described connecting key and the functional areas of chip; First soldered ball on wiring layer surface again described in being positioned at.
Optionally, described connecting key also comprises the protective layer being positioned at described conductor wire sidewall surfaces, and described protective layer exposes the conductor wire of described connecting key first end and the second end.
Optionally, the material of described protective layer is insulating material.
Optionally, described insulating material is organic insulating material or inorganic insulating material; Described organic insulating material comprises polyvinyl chloride; Described inorganic insulating material comprise in silica, silicon nitride and silicon oxynitride one or more.
Optionally, the first end size of described connecting key is greater than the second end size of described connecting key.
Optionally, the first end size of described connecting key and the second end measure-alike.
Optionally, described connecting key first end is 40 microns ~ 400 microns to the distance of the second end.
Optionally, the conductor wire size of described connecting key first end and the conductor wire of the second end measure-alike.
Optionally, the material of described conductor wire is copper, tungsten, aluminium, gold or silver-colored.
Optionally, also comprise: carrier, the 5th surface of the first surface of described chip, described plastic packaging layer and the first end of described connecting key are fixed on described carrier surface.
Optionally, the first surface of described chip is fixed on described carrier surface by tack coat; The first end of described connecting key is fixed on described carrier surface by tack coat.
Optionally, the surface, functional areas of described chip exposes pad; Described bond pad surface has projection, and the top surface of described projection protrudes from the second surface of described chip; Described plastic packaging layer exposes the top surface of described projection, the top surface of described projection and the surface, functional areas of described chip.
Optionally, also comprise: the first insulating barrier being positioned at described plastic packaging layer the 6th surface, have in described first insulating barrier and expose the conductor wire of described connecting key second end and some first through holes on surface, chip functions district respectively; Described wiring layer is again positioned at described first through hole and part first surface of insulating layer.
Optionally, also comprise: second insulating barrier on wiring layer surface again described in being positioned at, there is in described second insulating barrier the second through hole exposing part wiring layer again; Described first soldered ball is positioned at described second through hole.
Optionally, also comprise: the second soldered ball being positioned at the conductor wire surface of described connecting key first end.
Optionally, also comprise: packaging body, described packaging body has the 3rd surface, and the 3rd surface of described packaging body exposes conductive structure; The first surface of described chip and plastic packaging layer surface are oppositely arranged with the 3rd surface of described packaging body, and described conductive structure is interconnected by described second soldered ball and described connecting key.
Compared with prior art, technical scheme of the present invention has the following advantages:
In encapsulating structure of the present invention, directly key is fixedly connected with at the carrier surface of chip circumference, described connecting key comprises conductor wire, and the first end of described connecting key and the second end all expose conductor wire, and described connecting key runs through described plastic packaging layer, namely described conductor wire can be through to the 6th surface from the 5th surface of described plastic packaging layer, realizes the electrical connection of chip first surface to second surface with this.And, described connecting key and chip are directly fixed in described plastic packaging layer, make described connecting key more accurate relative to the position of described chip and be easy to regulation and control, not only be conducive to ensureing that the size of encapsulating structure is accurate, and be conducive to avoiding at wiring layer relative to occurrence positions skew between described connecting key or chip.Therefore, the structure of described encapsulating structure is simple, manufacturing cost reduces, and the size of described encapsulating structure is more accurate, is conducive to the size reducing encapsulating structure.
Further, described connecting key also comprises the protective layer being positioned at described conductor wire sidewall surfaces.Described protective layer can not only protect described conductor wire, and the cross sectional dimensions of connecting key can also be made to increase, and makes described connecting key be easier to aim at, is conducive to ensureing that described connecting key is accurate relative to the position of chip.
Further, the first end size of described connecting key is greater than the second end size of described connecting key.Because the second end of described connecting key is fixed on carrier surface, and the first end size of described connecting key is comparatively large, is conducive to making described connecting key more stable fixing of carrier surface, can ensure that the relative position between connecting key and chip is accurate.
Accompanying drawing explanation
Fig. 1 introduces through-silicon via structure to realize the cross-sectional view of chip chamber conducting in encapsulating structure;
Fig. 2 introduces plastic packaging through-hole structure to realize the cross-sectional view of chip chamber conducting in encapsulating structure;
Fig. 3 to Figure 16 is the cross-sectional view of the forming process of the encapsulating structure of one embodiment of the invention;
Figure 17 to Figure 20 is the cross-sectional view of the forming process of the encapsulating structure of another embodiment of the present invention.
Embodiment
As stated in the Background Art, existing stacked chips encapsulation technology faces process technology limit and cost restriction, restriction is caused for applying of technology, and, stacked chips encapsulation technology also faces the problem at further thinning encapsulating structure gauge, to improving integrated level, the reduction size of chip further.
Stacked chips encapsulation technology can pass through silicon through hole (throughsiliconvia is called for short TSV) technology or plastic packaging through hole (throughmoldingvia is called for short TMV) technology realizes.But, no matter be silicon through hole technology or plastic packaging through hole technology, all there is certain defect.
Please refer to Fig. 1, Fig. 1 introduces through-silicon via structure to realize the cross-sectional view of chip chamber conducting in encapsulating structure, comprising: carrier 100; Be fixed on the chip 101 on carrier 100 surface, described chip 101 comprises relative non-functional face 102 and functional surfaces 103, and the non-functional face 102 of described chip 101 contacts with carrier 100 surface, and functional surfaces 103 surface of described chip 101 has pad 104; Run through the conductive plunger 105 of described chip 101, one end of described conductive plunger 105 is electrically connected with described pad 104; Be positioned at the plastic packaging layer 106 on described carrier 100 surface, described plastic packaging layer 106 surrounds described chip 101, and described plastic packaging layer 106 exposes described pad 104; Be positioned at the wiring layer again 107 on described plastic packaging layer 106 surface, described wiring layer again 107 is electrically connected with described pad 104; The soldered ball 108 on wiring layer 107 surface again described in being positioned at.
Wherein, described conductive plunger 105 is usually formed in cutting and is independently formed before chip 101; The forming step of described conductive plunger 105 comprises: provide substrate, and described substrate has functional surfaces, and described substrate comprises some chip region; Etching technics is adopted to form through hole from described functional surfaces in the chip region of described substrate; In sidewall and lower surface formation insulating barrier (sign) of described through hole; Surface of insulating layer in described through hole forms conductive plunger 105; Polishing is carried out, until expose an end position of described conductive plunger 105 from described substrate and functional surfaces apparent surface; After described glossing, cut described substrate, make some chip region form independently chip 101.
But, in the process forming described conductive plunger 105, need to form through hole in substrate, and the degree of depth of described through hole is formed chip 101 thickness, therefore the degree of depth of described through hole is comparatively dark, and the depth-to-width ratio of described through hole is higher, therefore, require higher to the etching technics forming described through hole, the difficulty of described etching technics is larger.And filled conductive material is to form conductive plunger 105 in described through hole for follow-up needs, and the depth-to-width ratio of described through hole is higher, the filling difficulty of described electric conducting material is comparatively large, higher for the technological requirement forming conductive plunger 105.In addition, the process costs that the etching technics of above-mentioned high-aspect-ratio and high aspect ratio vias fill is realized higher.To sum up, because the technology difficulty of through-silicon via structure is higher, technique is comparatively complicated, and process costs is higher, is applied to stacked chips encapsulation causes restriction for silicon through hole technology.
In order to reduce technology difficulty, also been proposed a kind of plastic packaging through hole technology.Please refer to Fig. 2, Fig. 2 introduces plastic packaging through-hole structure to realize the cross-sectional view of chip chamber conducting in encapsulating structure, comprising: carrier 110; Be fixed on the chip 111 on carrier 110 surface, described chip 111 comprises relative non-functional face 112 and functional surfaces 113, and the non-functional face 112 of described chip 111 contacts with carrier 110 surface, and functional surfaces 113 surface of described chip 111 has pad 114; Be positioned at the plastic packaging layer 115 on described carrier 110 surface, described plastic packaging layer 115 surrounds described chip 111, and described plastic packaging layer 115 exposes described pad 114; Run through the conductive plunger 116 of described plastic packaging layer 115; Be positioned at the wiring layer again 117 on described plastic packaging layer 115 surface, described wiring layer again 117 is electrically connected with described pad 114 and conductive plunger 116; The soldered ball 118 on wiring layer 117 surface again described in being positioned at.
Wherein, the forming step of described conductive plunger 116 comprises: adopt etching technics in described plastic packaging layer 115, form the through hole being through to carrier 110 surface; Conductive plunger 116 is formed in described through hole.
But due to the thickness of described plastic packaging layer 115 and the thickness of described chip 111, and described through hole runs through described plastic packaging layer 115, therefore the degree of depth of described through hole is comparatively dark, and the depth-to-width ratio of described through hole is higher; Have higher required precision to the etching technics forming described through hole, the difficulty of described etching technics is larger.Secondly, due to follow-up needs, in described through hole, filled conductive material is to form conductive plunger 116, and the depth-to-width ratio of described through hole is higher, causes the difficulty of filling described electric conducting material larger.And, because described conductive plunger 116 is formed at around described chip 111, therefore, need accurately to be decided to be the position of described conductive plunger 116 relative to chip, therefore, higher for positioning accuracy request when forming described through hole.To sum up, even if adopt plastic packaging through hole technology to realize stacked chips encapsulation, be still faced with complex process, technology difficulty is higher and cost is higher problem.
In order to solve the problem, the invention provides a kind of encapsulating structure, comprising: plastic packaging layer, described plastic packaging layer has the 5th relative surface and the 6th surface; Be positioned at the chip of described plastic packaging layer, described chip has relative first surface and second surface, and the second surface of described chip comprises functional areas, and the first surface of described chip flushes with the 5th surface of described plastic packaging layer; Run through the connecting key of described plastic packaging layer, described connecting key is positioned at described chip circumference, described connecting key comprises conductor wire, described connecting key comprises first end and the second end, first end and second end of described connecting key expose described conductor wire, the first end of described connecting key flushes with the 5th surface of plastic packaging layer, the second end of described connecting key higher than or the 6th surface that flushes in described plastic packaging layer; Be positioned at the wiring layer again on described plastic packaging layer the 6th surface, described wiring layer is again electrically connected with the second end of described connecting key and the functional areas of chip; First soldered ball on wiring layer surface again described in being positioned at.
Wherein, directly key is fixedly connected with at the carrier surface of chip circumference, described connecting key comprises conductor wire, and the first end of described connecting key and the second end all expose conductor wire, and described connecting key runs through described plastic packaging layer, namely described conductor wire can be through to the 6th surface from the 5th surface of described plastic packaging layer, realizes the electrical connection of chip first surface to second surface with this.And, described connecting key and chip are directly fixed in described plastic packaging layer, make described connecting key more accurate relative to the position of described chip and be easy to regulation and control, not only be conducive to ensureing that the size of encapsulating structure is accurate, and be conducive to avoiding at wiring layer relative to occurrence positions skew between described connecting key or chip.Therefore, the structure of described encapsulating structure is simple, manufacturing cost reduces, and the size of described encapsulating structure is more accurate, is conducive to the size reducing encapsulating structure.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 3 to Figure 16 is the cross-sectional view of the forming process of the encapsulating structure of one embodiment of the invention.
Please refer to Fig. 3, carrier 200 is provided.
Described carrier 200 provides workbench for subsequent technique, for the plastic packaging layer of carries chips and follow-up formation.
In the present embodiment, described carrier 200 is rigid substrate, and described rigid substrate is PCB substrate, glass substrate, metal substrate, semiconductor substrate or polymeric substrates.Described rigid substrate has higher hardness, not easily deformation occurs, and is enough to supporting chip and plastic packaging layer in subsequent technique.
In other embodiments, described carrier can also be flexible base plate.
Please refer to Fig. 4, at the surperficial fixed chip 201 of described carrier 200, described chip 201 has relative first surface 210 and second surface 220, the second surface 220 of described chip 201 comprises functional areas (not shown), and first surface 210 and carrier 200 surface of described chip 201 interfix.
The first surface 210 of described chip 201 is fixed on described carrier 200 surface by tack coat (not shown).The material of described tack coat is UV glue, and described UV glue viscosity after Ultraviolet radiation reduces, and is peeled off by carrier 200 so that follow-up from encapsulating structure.
In one embodiment, adhere to tack coat at the first surface 210 of described chip 201, more described tack coat is adhered to carrier 200 surface, to realize the bonding between chip 201 and carrier 200.And the first surface 210 of described chip 201 does not have functional areas, namely the first surface 210 of described chip 201 does not have electric connection structure, after chip 201 first surface 210 is fixed on carrier 200 surface, the functional areas of the second surface 220 of chip 201 can be exposed.
In another embodiment, the correspondence position of fixed chip 201 can also be needed tack coat is formed on the surface of described carrier 200, or form tack coat at carrier 200 surface global, again the first surface 210 of described chip 201 is adhered to described tie layer surface, make chip 201 be fixed on carrier 200 surface.
In the present embodiment, described carrier 200 surface global covers described tack coat.
Described chip 201 can be sensor chip, logic circuit chip, storage chip etc.Can have in transistor, passive device (such as resistance, electric capacity and inductance etc.), memory device, transducer, electric interconnection structure in the functional areas of described chip 201 second surface 220 one or more.
The forming step of described chip 201 comprises: provide substrate, and described substrate has some chip region, and described substrate comprises relative first surface and second surface, has functional areas in the chip region of described substrate second surface; Described substrate is cut, some chip region are separated from each other, form independently chip 201.
In the present embodiment, the surface, functional areas of described chip 201 exposes pad; Described bond pad surface has projection 221, and the top surface of described projection 221 protrudes from the second surface 220 of described chip 201, the top surface of described projection 221 and the surface, functional areas of described chip 201.The material of described projection 213 comprises copper, gold or tin, and described projection 213 has preset thickness.Described projection 221 can realize being electrically connected with the circuit in functional areas or device.Described projection 221 for being electrically connected with the connecting key of follow-up setting, thus realizes the electrical connection between the functional areas of chip 201 and other chip or external circuit.In the present embodiment, the surface, functional areas of described chip 201 and the top surface of described projection 221.In other embodiments, described functional areas can also be sensor region, have transducer in described sensor region, and described transducer is for obtaining the information in external environment condition.
Please refer to Fig. 5, carrier 200 surface around described chip 201 is fixedly connected with key 203, described connecting key 203 comprises conductor wire 230, described connecting key 230 comprises first end 231 and the second end 232, the first end 231 of described connecting key 203 and the second end 232 expose described conductor wire 230, first end 231 and described carrier 200 surface of described connecting key 203 interfix, the second end 232 of described connecting key 203 higher than or flush in surface, the functional areas of described chip 201.
The first end 231 of described connecting key 203 is fixed on described carrier 200 surface by tack coat.The material of described tack coat is UV glue, and described UV glue viscosity after Ultraviolet radiation reduces, and is peeled off by carrier 200 so that follow-up from encapsulating structure.
In one embodiment, at the first end 231 surface adhesion tack coat of described connecting key 203, more described tack coat is adhered to carrier 200 surface, to realize the bonding between connecting key 203 and carrier 200.
In another embodiment, the correspondence position being fixedly connected with key 203 can also be needed tack coat is formed on the surface of described carrier 200, or cover tack coat at carrier 200 surface global, again the first surface 210 of described connecting key 203 is adhered to described tie layer surface, make connecting key 203 be fixed on carrier 200 surface.
In the present embodiment, the surface, functional areas of described chip 201 and the top surface of described projection 221, and after carrier 200 surface is fixedly connected with the first end 231 of key 203, second end 232 surface of connecting key 203 higher than or flush in surface, the functional areas of described chip 201, namely described connecting key 203 the second end 232 surface higher than or the top surface that flushes in described projection 221.
Carrier 200 surface around a chip 201, fixes one or several connecting keys 203.When connecting key 203 quantity around a chip 201 is greater than 1, the quantity of described connecting key 203 can be consistent with projection 221 quantity on chip 201 surface, and the position of described connecting key 203 is corresponding with projection 221 position on described chip 201 surface.
The first end 231 of described connecting key 203 and the second end 232 expose conductor wire 230, after the first end 231 of described connecting key 203 is interfixed with described carrier 200 surface, namely the conductor wire 230 that described connecting key 203 first end 231 exposes interfixes with described carrier 200 surface, and conductor wire 230 surface that described second end 232 exposes higher than or the top surface that flushes in described projection 221.Follow-up after plastic packaging layer surface forms wiring layer again, described wiring layer again can realize the electrical connection between conductor wire 230 that described second end 232 exposes and projection 221, thus enables projection 221 realize electrical connection to carrier 200 surface.
Because described connecting key 203 is directly fixed on carrier 200 surface, avoid after follow-up formation plastic packaging layer, then carry out routing technique or form the step of plastic packaging through-hole structure, can Simplified flowsheet step, and reduce technology difficulty, thus can reduce costs.And described connecting key 203 is directly fixed on carrier 200 surface, makes described connecting key 203 more accurate relative to the position of chip 201, avoid in the process forming plastic packaging through-hole structure, the error problem produced during etching through hole.In addition, the second end 232 of described connecting key 203 higher than or the top surface that flushes in described projection 221, then the surface of the plastic packaging layer of follow-up formation can flush in described bond pad surface; Compared in routing technique, plastic packaging layer surface needs the problem higher than chip surface, and the plastic packaging layer thickness of the follow-up formation of the present embodiment is thinner, is conducive to the gauge of thinning formed encapsulating structure.
In the present embodiment, the distance of described connecting key 203 first end 231 to the second end 232 is 40 microns ~ 400 microns; The distance of described connecting key 203 first end 231 to the second end 232 is more than or equal to the thickness of described chip 201, and the thickness of described chip 201 is the distance of described projection 221 top surface to the first surface 210 of chip 201.Can ensure that, after follow-up formation plastic packaging layer, described plastic packaging layer surface can flush with projection 221 top surface thus, described plastic packaging layer can expose the second end 232 of connecting key 203 simultaneously.
The material of described conductor wire 230 is electric conducting material, and described conductor wire 230 is for realizing the conducting of chip 201 from first surface 210 to second surface 220; Described electric conducting material comprises for copper, tungsten, aluminium, gold or silver-colored.
In the present embodiment, described connecting key 203 also comprises the protective layer 233 being positioned at described conductor wire 230 sidewall surfaces, and described protective layer 233 exposes the conductor wire 230 of described connecting key 203 first end 231 and the second end 232.
In another embodiment, described connecting key can not also comprise described protective layer, and only has described conductor wire.
The material of described protective layer 233 is insulating material.Described insulating material is organic insulating material or inorganic insulating material; Described organic insulating material comprises polyvinyl chloride or resin; Described resin comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; Described inorganic insulating material comprise in silica, silicon nitride and silicon oxynitride one or more.
Described protective layer 233 can not only when being fixed on carrier 200 surface by connecting key 203; for the protection of the surface of described conductor wire 230 from damage; and the sectional dimension of described connecting key 203 can be increased; thus more easily aim at when fixing surperficial with carrier 200 by connecting key 203, thus make the connecting key 203 being fixed on carrier 200 surface more accurate relative to the position of chip 201.
In the present embodiment, first end 231 size of described connecting key 203 and the second end 232 measure-alike.Conductor wire 230 size of described connecting key 203 first end 231 and the conductor wire 230 of the second end 232 measure-alike.Wherein, described conductor wire 230 diameter is 30 microns ~ 150 microns, and the thickness of described protective layer 233 is 10 nanometer ~ 10 micron; When the material of described conductor wire 230 is copper, the minimum diameter of described conductor wire 230 is 30 microns; When the material of described conductor wire 230 is aluminium, the minimum diameter of described conductor wire 230 is 100 microns.
In the present embodiment, described conductor wire 230 is cylindrical, and namely the cross section of described conductor wire 230 is circular, and the first end 231 of described connecting key 203 and the second end 232 expose described columniform conductor wire 230 two ends respectively; Described connecting key 203 first end 231 and conductor wire 230 size of the second end 232 and the diameter of described cylindrical conductive line 230.
In the present embodiment, described columniform conductor wire 230 is identical from connecting key 203 first end 231 to the second end 232 diameter.
In the present embodiment; described conductor wire 230 sidewall surfaces is also coated with protective layer 233; and the thickness of described protective layer 233 is homogeneous, thus after described conductor wire 230 Surface coating protective layer 233, described connecting key 203 is still identical from the size of first end 231 to the second end 232.
In other embodiments, the size of the second end of described connecting key can also be less than the size of described first end.
Be described below with reference to the forming step of accompanying drawing to described connecting key.
Please refer to Fig. 6, provide initial conduction line 300, described initial conduction line 300 has the 3rd end 301 and the 4th end 302.
Described initial conduction line 300 forms conductor wire 230 (as shown in Figure 5) for cutting.The material of described initial conduction line 300 is electric conducting material; Described electric conducting material comprises for copper, tungsten, aluminium, gold or silver-colored.
In the present embodiment, described initial conduction line 300 is cylindrical, and namely the cross section of described initial conduction line 300 is circular; And described initial conduction line 300 is from measure-alike to the 4th end 302 of the 3rd end 301, namely described columniform conductor wire 300 is identical to the diameter of the 4th end 302 from the 3rd end 301.
Please refer to Fig. 7, form initial protective layers 303 in the sidewall surfaces of described initial conduction line 300, form initial connecting key 310, described initial protective layers 303 exposes the 3rd end 301 and the 4th end 302 of described initial conduction line 300.
The formation process of described initial protective layers 303 comprises chemical vapor deposition method, physical gas-phase deposition, atom layer deposition process, spraying coating process or Shooting Technique.
The material of described initial protective layers 303 is insulating material; Described insulating material is organic insulating material or inorganic insulating material.
In one embodiment, when the material of described initial protective layers 303 is organic insulating material, described organic insulating material comprises polyvinyl chloride or resin; Described resin comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; The formation process of described initial protective layers 303 can be spraying coating process or Shooting Technique.
In another embodiment, the material of described initial protective layers 303 is inorganic insulating material, described inorganic insulating material comprise in silica, silicon nitride and silicon oxynitride one or more; The formation process of described initial protective layers 303 can chemical vapor deposition method, physical gas-phase deposition, atom layer deposition process; And the technique forming described initial protective layers 303 needs to have good covering power and uniformity, make formed initial protective layers 303 can be covered in the surface of described initial conduction line 300 equably.
Please refer to Fig. 8; cut described initial protective layers 303 (as shown in Figure 7) and initial conduction line 300 (as shown in Figure 7) along the direction perpendicular to described initial conduction line 300 (as shown in Figure 7) sidewall, form some sections of conductor wires 230 and be positioned at the protective layer 233 of conductor wire 230 sidewall surfaces.
In the present embodiment, the sidewall surfaces of described initial conduction line 300 is the surface around described axis A (as shown in Figure 7), and described axis A is the central shaft through the 3rd end 301 and the 4th end 302 in described initial conduction line 300; Namely described initial protective layers 303 and initial conduction line 300 is cut along the direction perpendicular to axis A along the direction cutting perpendicular to described initial conduction line 300 sidewall.
Described cutting technique can be laser cutting parameter.After cutting technique, described initial protective layers 303 and initial conduction line 300 form some discrete connecting keys 203.
Please refer to Fig. 9, form plastic packaging layer 204 on described carrier 200 surface, described plastic packaging layer 204 surrounds described chip 201 and connecting key 203, and the surface of described plastic packaging layer 204 exposes the second end 232 of described connecting key 203 and the surface, functional areas of chip 201.
In the present embodiment, the surface of described plastic packaging layer 204 flushes with projection 221 top surface of described chip 201 second surface 220, and namely described plastic packaging layer 204 exposes the top surface of described projection 221.Due to described connecting key 203 the second end 232 higher than or the top surface that flushes in described projection 221, thus described plastic packaging layer 204 can be made to expose the second end 232 of described connecting key 203.Follow-up can by forming the electrical connection that wiring layer again realizes between connecting key 203 and projection 221.
And because the surface of described plastic packaging layer 204 flushes with the top surface of projection 221, the thickness of described plastic packaging layer 204 is identical with the thickness of chip 201, the thinner thickness of described plastic packaging layer 204 can make the gauge of formed encapsulating structure less.
In the present embodiment, the forming step of described plastic packaging layer 204 comprises: the initial plastic packaging layer forming the projection 221 covered on described chip 201 and chip 201 on described carrier 200 surface; Polishing is carried out to described initial plastic packaging layer, till the top surface exposing described projection 221, forms described plastic packaging layer 204.
Described plastic packaging layer 204 can be photosensitive dry film, non-photo-sensing dry film or capsulation material film.
In one embodiment, described plastic packaging layer 204 is photosensitive dry film, and the formation process of described initial plastic packaging layer is vacuum film coating process.
In another is implemented, the material of described plastic packaging layer 204 is capsulation material, and described capsulation material comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol or other suitable polymeric materials.
The formation process of described initial plastic packaging layer comprises Shooting Technique (injectionmolding), turns and mould technique (transfermolding) or silk-screen printing technique.Described Shooting Technique comprises: provide mould; Fill capsulation material in the mold, make the coated described chip 201 of described capsulation material and connecting key 203; Elevated cure is carried out to described capsulation material, forms plastic packaging layer 204.
In other embodiments, the material of described plastic packaging layer 204 also can be other insulating material.
The follow-up wiring layer be again electrically connected with described connecting key 203 second end 232 and projection 221 in described plastic packaging layer 204 surface formation.In one embodiment, described wiring layer more directly can be formed at described plastic packaging layer 204 surface.In the present embodiment, after described plastic packaging layer 204 surface forms the first insulating barrier, then wiring layer again can be formed in the first surface of insulating layer; Be described below with reference to accompanying drawing.
Please refer to Figure 10, form the first insulating barrier 205 on described plastic packaging layer 204 surface, have in described first insulating barrier 205 and expose the conductor wire 230 of described connecting key 203 second end 232 and some first through holes 206 on surface, chip 201 functional areas respectively.
Described first insulating barrier 205 is for the protection of described plastic packaging layer 204 surface; The first through hole 206 in described first insulating barrier 205 is electrically connected with conductor wire 230 and projection 221 for enabling the wiring layer again of follow-up formation.
The forming step of described first insulating barrier 205 comprises: form the first dielectric film on described plastic packaging layer 204, connecting key 203 and projection 221 surface; Carry out graphically, forming the first insulating barrier 205 to described first dielectric film, and in described first insulating barrier 205, there is the first through hole 206.
In one embodiment, the material of described first insulating barrier 205 is polymeric material or inorganic insulating material; Described polymeric material can be insulating resin; Described inorganic insulating material can be one or more combinations in silica, silicon nitride, silicon oxynitride.
Carry out patterned technique to described first dielectric film to comprise: adopt coating process and exposure imaging technique to form patterned photoresist layer at the first insulating film surface; With described first dielectric film of described photoresist layer etching.
The technique etching described first dielectric film is anisotropic dry etch process; The etching gas of described anisotropic dry etch process comprises CH 4, CHF 3, CH 3one or more in F, bias power is greater than 100 watts, and bias voltage is greater than 10 volts.
In another embodiment, the material of the first insulating barrier 205 is photoresist, and described first through hole 206 adopts photoetching process to be formed.
Please refer to Figure 11, in described first through hole 206 (as shown in Figure 10) and part first insulating barrier 205 surface formed described in wiring layer 207 again, the second end 232 and the projection 221 of described wiring layer again 207 and described connecting key 203 are electrically connected.
The forming step of described wiring layer again 207 comprises: in described first through hole 206 and the first insulating barrier 205 surface form conducting film, described conducting film fills full described first through hole 206; Conducting film described in planarization; After flatening process, form patterned layer, described patterned layer cover part conducting film on described conducting film surface; With described patterned layer for mask, etch described conducting film, till exposing the first insulating barrier 205 surface; After the described conducting film of etching, remove described patterned layer.
The material of described conducting film comprise in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride, silver one or more; The technique etching described conducting film is anisotropic dry etch process or wet processing; Described patterned layer can be patterned photoresist layer, can also be patterned hard mask, the material of described hard mask be a kind of in silica, silicon nitride, silicon oxynitride or multiple; Described flatening process can be CMP (Chemical Mechanical Polishing) process.
Described wiring layer again 207 can be single layer structure or sandwich construction, and the wiring layer again 207 of described single layer structure or sandwich construction is for realizing specific circuit function.In the present embodiment, described wiring layer again 207 is single layer structure.In other embodiments, described wiring layer again can be sandwich construction, and with insulating barrier electric isolution between adjacent two layers wiring layer.
Please refer to Figure 12, form the second insulating barrier 208 on described wiring layer again 207 surface, there is in described second insulating barrier 208 the second through hole 280 exposing partly again wiring layer 207.
Described second insulating barrier 208 is solder mask, described second insulating barrier 208 for the protection of described in layer at wiring layer 207, and the second through hole 280 in described second insulating barrier 208 is for defining the position of the first soldered ball of follow-up formation.
The forming step of described second insulating barrier 208 comprises: form the second dielectric film at wiring layer 207 again and the first insulating barrier 205 surface; Carry out graphically, forming the second insulating barrier 208 to described second dielectric film, and in described second insulating barrier 208, there is described second through hole 280.
In one embodiment, the material of described second insulating barrier 208 is polymeric material or inorganic insulating material; Described polymeric material can be insulating resin; Described inorganic insulating material can be one or more combinations in silica, silicon nitride, silicon oxynitride.
Carry out patterned technique to described second dielectric film to comprise: adopt coating process and exposure imaging technique to form patterned photoresist layer at the second insulating film surface; With described first dielectric film of described photoresist layer etching.
The technique etching described second dielectric film is anisotropic dry etch process; The etching gas of described anisotropic dry etch process comprises CH 4, CHF 3, CH 3one or more in F, bias power is greater than 100 watts, and bias voltage is greater than 10 volts.
In another embodiment, the material of the second insulating barrier 208 is photoresist, and described second through hole 208 adopts photoetching process to be formed.
Please refer to Figure 13, in described second through hole 280 (as shown in figure 12), form described first soldered ball 281.
The material of described first soldered ball 281 comprises tin.The forming step of described first soldered ball 281 comprises: the wiring layer again 207 surface printing tin cream bottom described second through hole 280, then carries out high temperature reflux, under surface tension effects, forms the first soldered ball 281.
In another embodiment, can also electricity wiring layer 207 surface printing scaling powder and soldered ball particle more first bottom described two through holes 280, then high temperature reflux forms the first soldered ball 281.In other embodiments, can also on described wiring layer again 207 electrotinning post, then high temperature reflux forms the first soldered ball 281.
In one embodiment, between described wiring layer again 207 and described first soldered ball 281, metal structure under ball (UnderBallMetal is called for short UBM) can also be had; Under described ball, metal structure can comprise the metal level of single metal layer or multiple-layer overlapped; The material of described single metal layer or more metal layers comprises one or more combinations in copper, aluminium, nickel, cobalt, titanium, tantalum.
Please refer to Figure 14, after described first soldered ball 281 of formation, remove described carrier 200 (as shown in figure 13), expose the first end 231 of described connecting key 203.
In the present embodiment, described carrier 200 surface global covers tack coat, and the material of described tack coat is UV glue, and described chip 201 and connecting key 203 are fixed by described tack coat and described carrier 200, and described plastic packaging layer 204 is formed at described tie layer surface.By carrying out UV-irradiation to described tack coat, the viscosity of tack coat is reduced; Again by described carrier 200 from described chip 201 first surface 210, connecting key 203 first end 231 and plastic packaging layer 204 sur-face peeling, thus expose the first end 231 of chip 201 first surface 210 and connecting key 203.After the described carrier 200 of stripping, carry out cleaning to remove residual tack coat.
In other embodiments, described carrier 200 can also be removed by etching technics or CMP (Chemical Mechanical Polishing) process.
Please refer to Figure 15, after the described carrier 200 (as shown in figure 13) of removal, form the second soldered ball 209 on conductor wire 230 surface of described connecting key 203 first end 231.
After forming described second soldered ball 209, the two-sided of encapsulating structure namely realizing being formed plants ball, and the both side surface of described encapsulating structure all can realize stacked package with other packaging body.
The material of described second soldered ball 209 comprises tin.The forming step of described second soldered ball 209 comprises: at the conductor wire 230 surface printing tin cream of described connecting key 203 first end 231, then carry out high temperature reflux, under surface tension effects, form the second soldered ball 209.
In another embodiment, can also first at conductor wire 230 surface printing scaling powder and the soldered ball particle of described connecting key 203 first end 231, then high temperature reflux forms the second soldered ball 209.In other embodiments, can also at the zinc-plated post of conductor wire 230 surface electrical of described connecting key 203 first end 231, then high temperature reflux forms the second soldered ball 209.
In another embodiment, please refer to Figure 16, after formation second soldered ball 209, also comprise: provide packaging body 400, described packaging body 400 has the 3rd surface 401, and the 3rd surface 401 of described packaging body 400 exposes conductive structure 402; The first surface 210 of described chip 201 and plastic packaging layer 204 surface are oppositely arranged with the 3rd surface 401 of described packaging body 400, and by welding procedure, described second soldered ball 209 are interconnected with described conductive structure 402.
In described packaging body 400, there is chip or semiconductor device, and described chip or semiconductor device are electrically connected with described conductive structure 402.Because described conductive structure 402 is electrically connected with chip 201 by the second soldered ball 209 and connecting key 203, thus the chip that can realize in packaging body 400 or semiconductor device are electrically connected with described chip 201, stacked chip package structure is formed with this, and what formed is packaging body stacked structure (PackageOnPackage is called for short POP).
To sum up, in the formation method of the present embodiment, before formation plastic packaging layer, be directly fixedly connected with key at the carrier surface of chip circumference.Wherein, described connecting key comprises conductor wire, and the first end of described connecting key and the second end all expose conductor wire; After the first end of described connecting key is fixing and carrier surface, second end of described connecting key can higher than or the functional surfaces that flushes in described chip, therefore, after described carrier surface formation exposes the plastic packaging floor in chip functions district, second end of described connecting key also can higher than or flush in described plastic packaging layer surface, thus described conductor wire can be through to carrier surface, so that follow-up chip first surface is to the electrical connection of second surface from described plastic packaging layer surface.Because described connecting key is directly fixed on carrier surface, avoid the step carrying out processing in plastic packaging layer, the formation method of encapsulating structure can be made to simplify.And, described connecting key is directly fixed on carrier surface, described connecting key can be made more accurate relative to the position of described chip and be easy to regulation and control, not only be conducive to ensureing that the size of the encapsulating structure formed is accurate, and the second end of the wiring layer again and described connecting key that are conducive to follow-up formation realizes being electrically connected.Therefore, the formation method processing step of described encapsulating structure simplifies, process costs reduces, technology difficulty reduces, and the size of the encapsulating structure formed is more accurate, is conducive to the size reducing encapsulating structure.
Accordingly, the present embodiment also provides a kind of encapsulating structure adopting said method to be formed, and please continue to refer to Figure 15, comprising:
Plastic packaging layer 204, described plastic packaging layer 204 has the 5th relative surface and the 6th surface;
Be positioned at the chip 201 of described plastic packaging layer 204, described chip 201 has relative first surface 210 and second surface 220, the second surface 220 of described chip 201 comprises functional areas, and the first surface 210 of described chip 201 flushes with the 5th surface of described plastic packaging layer 204;
Run through the connecting key 203 of described plastic packaging layer 204, described connecting key 203 is positioned at around described chip 201, described connecting key 204 comprises conductor wire 230, described connecting key 230 comprises first end 231 and the second end 232, the first end 231 of described connecting key 203 and the second end 232 expose described conductor wire 230, the first end 231 of described connecting key 203 flushes with the 5th surface of plastic packaging layer 204, the second end 232 of described connecting key 203 higher than or the 6th surface that flushes in described plastic packaging layer 204;
Be positioned at the wiring layer again 207 on described plastic packaging layer 204 the 6th surface, described wiring layer again 207 is electrically connected with the second end 232 of described connecting key 203 and the functional areas of chip 201;
First soldered ball 281 on wiring layer 207 surface again described in being positioned at.
Be described below with reference to accompanying drawing.
Described chip 201 can be sensor chip, logic circuit chip, storage chip etc.Can have in transistor, passive device (such as resistance, electric capacity and inductance etc.), memory device, transducer, electric interconnection structure in the functional areas of described chip 201 second surface 220 one or more.
In the present embodiment, the surface, functional areas of described chip 201 exposes pad; The top surface that described bond pad surface has a projection 221 described in projection 221 protrudes from the second surface 220 of described chip 201.Described projection 221 can realize being electrically connected with the circuit in functional areas or device.Described projection 221 for being electrically connected with connecting key 203, thus realizes the electrical connection between the functional areas of chip 201 and other chip or external circuit.In the present embodiment, the surface, functional areas of described chip 201 and the top surface of described projection 221, described plastic packaging layer 204 exposes the top surface of described projection 221.In other embodiments, described functional areas can also be sensor region, have transducer in described sensor region, and described transducer is for obtaining the information in external environment condition.
One or several connecting keys 203 are fixed around a chip 201; When connecting key 203 quantity around a chip 201 is greater than 1, the quantity of described connecting key 203 can be consistent with projection 221 quantity on chip 201 surface, and the position of described connecting key 203 is corresponding with projection 221 position on described chip 201 surface.
In the present embodiment, the distance of described connecting key 203 first end 231 to the second end 232 is 40 microns ~ 400 microns; The distance of described connecting key 203 first end 231 to the second end 232 is more than or equal to the thickness of described chip 201, and the thickness of described chip 201 is the distance of described projection 221 top surface to the first surface 210 of chip 201.
The material of described conductor wire 230 is electric conducting material, and described conductor wire 230 is for realizing the conducting of chip 201 from first surface 210 to second surface 220; Described electric conducting material comprises for copper, tungsten, aluminium, gold or silver-colored.
In the present embodiment, described connecting key 203 also comprises the protective layer 233 being positioned at described conductor wire 230 sidewall surfaces, and described protective layer 233 exposes the conductor wire 230 of described connecting key 203 first end 231 and the second end 232.In another embodiment, described connecting key can not also comprise described protective layer, and only has described conductor wire.
The material of described protective layer 233 is insulating material.Described insulating material is organic insulating material or inorganic insulating material; Described organic insulating material comprises polyvinyl chloride or resin; Described resin comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; Described inorganic insulating material comprise in silica, silicon nitride and silicon oxynitride one or more.
Described protective layer 233 can not only when being fixed on carrier 200 surface by connecting key 203; for the protection of the surface of described conductor wire 230 from damage; and the sectional dimension of described connecting key 203 can be increased, thus make described connecting key 203 more accurate relative to the position of chip 201.
In the present embodiment, first end 231 size of described connecting key 203 and the second end 232 measure-alike.Conductor wire 230 size of described connecting key 203 first end 231 and the conductor wire 230 of the second end 232 measure-alike.Wherein, described conductor wire 230 diameter is 30 microns ~ 150 microns, and the thickness of described protective layer 233 is 10 nanometer ~ 10 micron; When the material of described conductor wire 230 is copper, the minimum diameter of described conductor wire 230 is 30 microns; When the material of described conductor wire 230 is aluminium, the minimum diameter of described conductor wire 230 is 100 microns.
In the present embodiment, described conductor wire 230 is cylindrical, and namely the cross section of described conductor wire 230 is circular, and the first end 231 of described connecting key 203 and the second end 232 expose described columniform conductor wire 230 two ends respectively; Described connecting key 203 first end 231 and conductor wire 230 size of the second end 232 and the diameter of described cylindrical conductive line 230.In the present embodiment, described columniform conductor wire 230 is identical from connecting key 203 first end 231 to the second end 232 diameter.
In the present embodiment; described conductor wire 230 sidewall surfaces is also coated with protective layer 233; and the thickness of described protective layer 233 is homogeneous, thus after described conductor wire 230 Surface coating protective layer 233, described connecting key 203 is still identical from the size of first end 231 to the second end 232.In other embodiments, the size of the second end of described connecting key can also be less than the size of described first end.
In the present embodiment, the surface of described plastic packaging layer 204 flushes with projection 221 top surface of described chip 201 second surface 220, due to described connecting key 203 the second end 232 higher than or the top surface that flushes in described projection 221, thus described plastic packaging layer 204 can be made to expose the second end 232 of described connecting key 203.And because the surface of described plastic packaging layer 204 flushes with the top surface of projection 221, the thickness of described plastic packaging layer 204 is identical with the thickness of chip 201, the thinner thickness of described plastic packaging layer 204 can make the gauge of encapsulating structure less.
Described plastic packaging layer 204 can be photosensitive dry film, non-photo-sensing dry film or capsulation material film.In implementing one, the material of described plastic packaging layer 204 is capsulation material, and described capsulation material comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol or other suitable polymeric materials.
The encapsulating structure of the present embodiment also comprises: the first insulating barrier 205 being positioned at described plastic packaging layer 204 the 6th surface, has and expose the described conductor wire 230 of connecting key 203 second end 232 and some first through holes on surface, chip 201 functional areas respectively in described first insulating barrier 205; Described wiring layer again 207 is positioned at described first through hole and part first insulating barrier 205 surface.
Described first insulating barrier 205 is for the protection of described plastic packaging layer 204 surface; The first through hole in described first insulating barrier 205 is used for making wiring layer 207 can be electrically connected with conductor wire 230 and projection 221 again.In one embodiment, the material of described first insulating barrier 205 is polymeric material or inorganic insulating material; Described polymeric material can be insulating resin; Described inorganic insulating material can be one or more combinations in silica, silicon nitride, silicon oxynitride.In another embodiment, the material of the first insulating barrier 205 is photoresist.
The material of described wiring layer again 207 comprise in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride, silver one or more.Described wiring layer again 207 can be single layer structure or sandwich construction, and the wiring layer again 207 of described single layer structure or sandwich construction is for realizing specific circuit function.In the present embodiment, described wiring layer again 207 is single layer structure.In other embodiments, described wiring layer again can be sandwich construction, and with insulating barrier electric isolution between adjacent two layers wiring layer.
The encapsulating structure of the present embodiment also comprises: second insulating barrier 208 on wiring layer 207 surface again described in being positioned at, and has the second through hole exposing part wiring layer 207 again in described second insulating barrier 208; Described first soldered ball 281 is positioned at described second through hole.
Described second insulating barrier 208 is solder mask, described second insulating barrier 208 for the protection of described in layer at wiring layer 207, and the second through hole 280 in described second insulating barrier 208 is for defining the position of described first soldered ball 281.In one embodiment, the material of described second insulating barrier 208 is polymeric material or inorganic insulating material; Described polymeric material can be insulating resin; Described inorganic insulating material can be one or more combinations in silica, silicon nitride, silicon oxynitride.In another embodiment, the material of the second insulating barrier 208 is photoresist.
The encapsulating structure of the present embodiment also comprises: the second soldered ball 209 being positioned at conductor wire 230 surface of described connecting key 203 first end 231.The material of described first soldered ball 281 comprises tin; The material of described second soldered ball 209 comprises tin.
In one embodiment, between described wiring layer again 207 and described first soldered ball 281, metal structure under ball (UnderBallMetal is called for short UBM) can also be had; Under described ball, metal structure can comprise the metal level of single metal layer or multiple-layer overlapped; The material of described single metal layer or more metal layers comprises one or more combinations in copper, aluminium, nickel, cobalt, titanium, tantalum.
In the present embodiment, described encapsulating structure can also comprise carrier 200 (as shown in figure 13), and the 5th surface of the first surface 210 of described chip 201, described plastic packaging layer 204 and the first end 231 of described connecting key 203 are fixed on described carrier 200 surface.
In the present embodiment, described carrier 200 is rigid substrate, and described rigid substrate is PCB substrate, glass substrate, metal substrate, semiconductor substrate or polymeric substrates.Described rigid substrate has higher hardness, not easily deformation occurs, and is enough to supporting chip and plastic packaging layer.In other embodiments, described carrier can also be flexible base plate.
The first surface 210 of described chip 201 is fixed on described carrier 200 surface by tack coat; The first end logical 231 of described connecting key 203 is crossed tack coat and is fixed on described carrier 200 surface.The material of described tack coat is UV glue, and described UV glue viscosity after Ultraviolet radiation reduces, and is convenient to carrier 200 to peel off from encapsulating structure.
In another embodiment, please refer to Figure 16, described encapsulating structure also comprises: packaging body 400, and described packaging body 400 has the 3rd surface 401, and the 3rd surface 401 of described packaging body 400 exposes conductive structure 402; The first surface 210 of described chip 201 and plastic packaging layer 204 surface are oppositely arranged with the 3rd surface 401 of described packaging body 400, and described conductive structure 402 is interconnected with described connecting key 203 by described second soldered ball 209.
In described packaging body 400, there is chip or semiconductor device, and described chip or semiconductor device are electrically connected with described conductive structure 402.Because described conductive structure 402 is electrically connected with chip 201 by the second soldered ball 209 and connecting key 203, thus the chip that can realize in packaging body 400 or semiconductor device are electrically connected with described chip 201, described encapsulating structure is the encapsulating structure of stacked chips, i.e. packaging body stacked structure (PackageOnPackage is called for short POP).
To sum up, in the structure of the present embodiment, directly key is fixedly connected with at the carrier surface of chip circumference, described connecting key comprises conductor wire, and the first end of described connecting key and the second end all expose conductor wire, and described connecting key runs through described plastic packaging layer, namely described conductor wire can be through to the 6th surface from the 5th surface of described plastic packaging layer, realizes the electrical connection of chip first surface to second surface with this.And, described connecting key and chip are directly fixed in described plastic packaging layer, make described connecting key more accurate relative to the position of described chip and be easy to regulation and control, not only be conducive to ensureing that the size of encapsulating structure is accurate, and be conducive to avoiding at wiring layer relative to occurrence positions skew between described connecting key or chip.Therefore, the structure of described encapsulating structure is simple, manufacturing cost reduces, and the size of described encapsulating structure is more accurate, is conducive to the size reducing encapsulating structure.
Figure 17 to Figure 20 is the cross-sectional view of the forming process of the encapsulating structure of another embodiment of the present invention.
Please refer to Figure 17, carrier 500 is provided; At the surperficial fixed chip 501 of described carrier 500, described chip 501 has relative first surface 510 and second surface 520, the second surface 520 of described chip 501 comprises functional areas (not shown), and first surface 510 and carrier 500 surface of described chip 501 interfix; Carrier 500 surface around described chip 501 is fixedly connected with key 503, described connecting key 503 comprises conductor wire 530, described connecting key 530 comprises first end 531 and the second end 532, the first end 531 of described connecting key 503 and the second end 532 expose described conductor wire 530, first end 531 and described carrier 500 surface of described connecting key 503 interfix, the second end 532 of described connecting key 503 higher than or flush in surface, the functional areas of described chip 501.
Described carrier 500, described chip 501, the surperficial fixed chip of carrier 500 501 technique and be fixedly connected with the technique of key 503 on carrier 500 surface identical with the related content of previous embodiment, do not repeat at this.
In the present embodiment, described connecting key 503 also comprises the protective layer 533 being positioned at described conductor wire 530 sidewall surfaces, and described protective layer 533 exposes the conductor wire 530 of described connecting key 503 first end 531 and the second end 532.
The material of described protective layer 533 is insulating material.Described insulating material is organic insulating material or inorganic insulating material; Described organic insulating material comprises polyvinyl chloride or resin; Described resin comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; Described inorganic insulating material comprise in silica, silicon nitride and silicon oxynitride one or more.
In the present embodiment, first end 531 size of described connecting key 503 is greater than the second end 532 size of described connecting key 503.And the sidewall of described connecting key 503 tilts relative to the surface of the first end 531 of connecting key 503, and the acute angle between the sidewall surfaces of described connecting key 503 and described first end 531 surface is 75 ° ~ 89 °.
In the present embodiment, described conductor wire 530 is cylindrical, and namely the cross section of described conductor wire 530 is circular, and the first end 531 of described connecting key 503 and the second end 532 expose described columniform conductor wire 530 two ends respectively; Described connecting key 503 first end 531 and conductor wire 530 size of the second end 532 and the diameter of described cylindrical conductive line 530.
In the present embodiment, described columniform conductor wire 530 is identical from connecting key 503 first end 531 to the second end 532 diameter.
In the present embodiment; described conductor wire 530 sidewall surfaces is also coated with protective layer 533; and protective layer 533 thickness being positioned at connecting key 503 first end 531 is greater than protective layer 533 thickness being positioned at the second end 532, thus first end 531 size of described connecting key 503 is made to be greater than the second end 532 size of described connecting key 503.
Because the first end 531 of described connecting key 503 is fixed on carrier 500 surface by tack coat, when first end 531 size of described connecting key 531 is greater than the second end 532 size, described connecting key 503 is more stable in fixing of carrier 500 surface, in the process of follow-up formation plastic packaging layer, described connecting key 503 is not easily subjected to displacement, and is conducive to ensureing that described connecting key 503 is accurate relative to the position of chip 500.
And conductor wire 530 in described connecting key 503 is identical from connecting key 503 first end 531 to the second end 532 diameter, from connecting key 503 first end 531 to the second end 532, the resistivity contrasts of described conductor wire 530 is less, makes the electric performance stablity of described conductor wire 530.
Be described below with reference to the forming step of accompanying drawing to described connecting key.
Please refer to Figure 18, provide initial conduction line 600, described initial conduction line 600 has the 3rd end 601 and the 4th end 602; Form initial protective layers 603 in the sidewall surfaces of described initial conduction line 600, form initial connecting key 610, described initial protective layers 601 exposes the 3rd end 601 and the 4th end 602 of described initial conduction line 600.
In the present embodiment, from the 3rd end 601 of described initial conduction line 600 to the direction of the 4th end 602, described initial connecting key 600 has some cut length 620, and each cut length 620 all has the five terminal 621 near the 3rd end 601 and the 6th end 622 near the 4th end 602; Initial protective layers 603 thickness of described cut length 620 five terminal 621 is greater than initial protective layers 603 thickness of cut length the 6th end 622.
The formation process of described initial protective layers 603 is Shooting Technique.The forming step of described initial protective layers 603 comprises: adopt coating process to form diaphragm on described initial conduction line 600 surface; Adopt mould to carry out moulding to described diaphragm, form described initial protective layers 603.
Wherein, the inner wall surface pattern of described mould is identical with the surface topography of the initial protective layers 603 of required formation, thus passes through the moulding of described mould, the thickness of protective layer 603 can be made to produce difference, make the surperficial indentation of protective layer 603.
The material of described protective layer 233 is organic insulating material; Described organic insulating material comprises polyvinyl chloride or resin; Described resin comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
Please refer to Figure 19; cut described initial protective layers 603 (as shown in figure 18) and initial conduction line 601 (as shown in figure 18) along the direction perpendicular to described initial conduction line 600 (as shown in figure 18) sidewall, form some sections of conductor wires 530 and be positioned at the protective layer 533 of conductor wire 530 sidewall surfaces.
After the described initial connecting key 610 (as shown in figure 18) of cutting, some cut length 620 (as shown in figure 18) are separate, each cut length 620 forms described connecting key 503, and the five terminal 621 (as shown in figure 18) of described cut length 620 becomes the first end 531 of connecting key 503, the 6th end 622 (as shown in figure 18) of described cut length becomes the second end 532 of connecting key.
In the present embodiment, the sidewall surfaces of described initial conduction line 600 is the surface around described axis B (as shown in figure 18), and described axis B is the central shaft through the 3rd end 601 and the 4th end 602 in described initial conduction line 600; Namely described initial protective layers 603 and initial conduction line 600 is cut along the direction perpendicular to axis B along the direction cutting perpendicular to described initial conduction line 600 sidewall.
Described cutting technique can be laser cutting parameter.After cutting technique, described initial protective layers 603 and initial conduction line 600 form some discrete connecting keys 503.And described cutting technique carries out along the edge of described cut length 620, so that some cut length 620 can be mutually discrete.
Please refer to Figure 20, form plastic packaging layer 504 on described carrier 500 surface, described plastic packaging layer 504 surrounds described chip 501 and connecting key 503, and the surface of described plastic packaging layer 504 exposes the second end 532 of described connecting key 503 and the surface, functional areas of chip 501; Form wiring layer 507 on described plastic packaging layer 504 surface, described wiring layer again 507 is electrically connected with the second end 532 of described connecting key 503 and the functional areas of chip 501 again; The first soldered ball 581 is formed on described wiring layer again 507 surface; After described first soldered ball 581 of formation, remove described carrier 500 (as shown in figure 19), expose the first end 531 of described connecting key 503.
The technique of described plastic packaging layer 504, the technique of formation plastic packaging layer 504, described wiring layer again 507, the technique forming again wiring layer 507, described first soldered ball 581, the technique forming the first soldered ball 581 and removal carrier 500 is identical with previous embodiment, does not repeat at this.
In the present embodiment, also be included in described plastic packaging layer 504 surface and form the first insulating barrier 505, have in described first insulating barrier 505 and expose the described conductor wire 530 of connecting key 503 second end 532 and some first through holes on surface, chip 501 functional areas respectively; Namely surface, described chip 501 functional areas is positioned at the top surface of the projection 521 on chip 501.In described first through hole and part first insulating barrier 505 surface formed described in wiring layer 507 again, the second end 532 and the projection 521 of described wiring layer again 507 and described connecting key 503 are electrically connected.
In the present embodiment, described in being also included in, wiring layer 507 surface forms the second insulating barrier 508 again, has the second through hole exposing partly again wiring layer 507 in described second insulating barrier 508; Described first soldered ball 581 is formed in described second through hole.
In addition, after the described carrier 500 of removal, the second soldered ball can also be formed on conductor wire 530 surface of described connecting key 503 first end 531.
And after formation second soldered ball, also comprise: provide packaging body, described packaging body has the 3rd surface, and the 3rd surface of described packaging body exposes conductive structure; The first surface 510 of described chip 501 and plastic packaging layer 504 surface are oppositely arranged with the 3rd surface of described packaging body, and by welding procedure, described second soldered ball and described conductive structure are interconnected.
Accordingly, the present embodiment also provides a kind of encapsulating structure adopting said method to be formed, and please continue to refer to Figure 20, comprising:
Plastic packaging layer 504, described plastic packaging layer 504 has the 5th relative surface and the 6th surface;
Be positioned at the chip 501 of described plastic packaging layer 504, described chip 501 has relative first surface 510 and second surface 520, the second surface 520 of described chip 501 comprises functional areas, and the first surface 510 of described chip 501 flushes with the 5th surface of described plastic packaging layer 504;
Run through the connecting key 503 of described plastic packaging layer 504, described connecting key 503 is positioned at around described chip 501, described connecting key 504 comprises conductor wire 530, described connecting key 530 comprises first end 531 and the second end 532, the first end 531 of described connecting key 503 and the second end 532 expose described conductor wire 530, the first end 531 of described connecting key 503 flushes with the 5th surface of plastic packaging layer 504, the second end 532 of described connecting key 503 higher than or the 6th surface that flushes in described plastic packaging layer 504;
Be positioned at the wiring layer again 507 on described plastic packaging layer 504 the 6th surface, described wiring layer again 507 is electrically connected with the second end 532 of described connecting key 503 and the functional areas of chip 501;
First soldered ball 581 on wiring layer 507 surface again described in being positioned at.
The difference of the encapsulating structure of the present embodiment and the encapsulating structure (as shown in figure 15) of previous embodiment is: first end 531 size of described connecting key 503 is greater than the second end 532 size of described connecting key 503.
In the present embodiment, described connecting key 503 also comprises the protective layer 533 being positioned at described conductor wire 530 sidewall surfaces, and described protective layer 533 exposes the conductor wire 530 of described connecting key 503 first end 531 and the second end 532.
The material of described protective layer 533 is insulating material.Described insulating material is organic insulating material or inorganic insulating material; Described organic insulating material comprises polyvinyl chloride or resin; Described resin comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; Described inorganic insulating material comprise in silica, silicon nitride and silicon oxynitride one or more.
In the present embodiment, first end 531 size of described connecting key 503 is greater than the second end 532 size of described connecting key 503.And the sidewall of described connecting key 503 tilts relative to the surface of the first end 531 of connecting key 503, and the acute angle between the sidewall surfaces of described connecting key 503 and described first end 531 surface is 75 ° ~ 89 °.
In the present embodiment, described conductor wire 530 is cylindrical, and namely the cross section of described conductor wire 530 is circular, and the first end 531 of described connecting key 503 and the second end 532 expose described columniform conductor wire 530 two ends respectively; Described connecting key 503 first end 531 and conductor wire 530 size of the second end 532 and the diameter of described cylindrical conductive line 530.
In the present embodiment, described columniform conductor wire 530 is identical from connecting key 503 first end 531 to the second end 532 diameter.
In the present embodiment; described conductor wire 530 sidewall surfaces is also coated with protective layer 533; and protective layer 533 thickness being positioned at connecting key 503 first end 531 is greater than protective layer 533 thickness being positioned at the second end 532, thus first end 531 size of described connecting key 503 is made to be greater than the second end 532 size of described connecting key 503.
To sum up, in the present embodiment, the first end size of described connecting key is greater than the second end size of described connecting key.Because the second end of described connecting key is fixed on carrier surface, and the first end size of described connecting key is larger, be conducive to making described connecting key more stable fixing of carrier surface, described connecting key can be avoided to be subjected to displacement, thus ensure that the relative position between connecting key and chip is accurate.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (16)

1. an encapsulating structure, is characterized in that, comprising:
Plastic packaging layer, described plastic packaging layer has the 5th relative surface and the 6th surface;
Be positioned at the chip of described plastic packaging layer, described chip has relative first surface and second surface, and the second surface of described chip comprises functional areas, and the first surface of described chip flushes with the 5th surface of described plastic packaging layer;
Run through the connecting key of described plastic packaging layer, described connecting key is positioned at described chip circumference, described connecting key comprises conductor wire, described connecting key comprises first end and the second end, first end and second end of described connecting key expose described conductor wire, the first end of described connecting key flushes with the 5th surface of plastic packaging layer, the second end of described connecting key higher than or the 6th surface that flushes in described plastic packaging layer;
Be positioned at the wiring layer again on described plastic packaging layer the 6th surface, described wiring layer is again electrically connected with the second end of described connecting key and the functional areas of chip;
First soldered ball on wiring layer surface again described in being positioned at.
2. encapsulating structure as claimed in claim 1, it is characterized in that, described connecting key also comprises the protective layer being positioned at described conductor wire sidewall surfaces, and described protective layer exposes the conductor wire of described connecting key first end and the second end.
3. encapsulating structure as claimed in claim 2, it is characterized in that, the material of described protective layer is insulating material.
4. encapsulating structure as claimed in claim 3, it is characterized in that, described insulating material is organic insulating material or inorganic insulating material; Described organic insulating material comprises polyvinyl chloride; Described inorganic insulating material comprise in silica, silicon nitride and silicon oxynitride one or more.
5. encapsulating structure as claimed in claim 1, it is characterized in that, the first end size of described connecting key is greater than the second end size of described connecting key.
6. encapsulating structure as claimed in claim 1, it is characterized in that, first end size and second end of described connecting key are measure-alike.
7. encapsulating structure as claimed in claim 1, it is characterized in that, described connecting key first end is 40 microns ~ 400 microns to the distance of the second end.
8. encapsulating structure as claimed in claim 1, is characterized in that, the conductor wire size of described connecting key first end and the conductor wire of the second end measure-alike.
9. encapsulating structure as claimed in claim 1, it is characterized in that, the material of described conductor wire is copper, tungsten, aluminium, gold or silver-colored.
10. encapsulating structure as claimed in claim 1, is characterized in that, also comprise: carrier, and the 5th surface of the first surface of described chip, described plastic packaging layer and the first end of described connecting key are fixed on described carrier surface.
11. encapsulating structures as claimed in claim 10, it is characterized in that, the first surface of described chip is fixed on described carrier surface by tack coat; The first end of described connecting key is fixed on described carrier surface by tack coat.
12. encapsulating structures as claimed in claim 1, it is characterized in that, the surface, functional areas of described chip exposes pad; Described bond pad surface has projection, and the top surface of described projection protrudes from the second surface of described chip; Described plastic packaging layer exposes the top surface of described projection, the top surface of described projection and the surface, functional areas of described chip.
13. encapsulating structures as claimed in claim 1, it is characterized in that, also comprise: the first insulating barrier being positioned at described plastic packaging layer the 6th surface, have in described first insulating barrier and expose the conductor wire of described connecting key second end and some first through holes on surface, chip functions district respectively; Described wiring layer is again positioned at described first through hole and part first surface of insulating layer.
14. encapsulating structures as claimed in claim 1, is characterized in that, also comprise: second insulating barrier on wiring layer surface again described in being positioned at, and have the second through hole exposing part wiring layer again in described second insulating barrier; Described first soldered ball is positioned at described second through hole.
15. encapsulating structures as claimed in claim 1, is characterized in that, also comprise: the second soldered ball being positioned at the conductor wire surface of described connecting key first end.
16. encapsulating structures as claimed in claim 15, is characterized in that, also comprise: packaging body, and described packaging body has the 3rd surface, and the 3rd surface of described packaging body exposes conductive structure; The first surface of described chip and plastic packaging layer surface are oppositely arranged with the 3rd surface of described packaging body, and described conductive structure is interconnected by described second soldered ball and described connecting key.
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