CN105845672A - Package structure - Google Patents

Package structure Download PDF

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Publication number
CN105845672A
CN105845672A CN 201610422460 CN201610422460A CN105845672A CN 105845672 A CN105845672 A CN 105845672A CN 201610422460 CN201610422460 CN 201610422460 CN 201610422460 A CN201610422460 A CN 201610422460A CN 105845672 A CN105845672 A CN 105845672A
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Prior art keywords
surface
linkage
chip
connected
end
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CN 201610422460
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Chinese (zh)
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高国华
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南通富士通微电子股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

A package structure comprises a first chip, a substrate core layer, a plastic package layer, a connection key structure, a second chip and a bonding metal line, wherein the first chip is provided with a functional surface, the substrate core layer is provided with a first surface and a second surface which are opposite to each other, the substrate core layer comprises a plastic package structure and the connection key structure, the connection key structure is arranged in the plastic package structure, the plastic package layer encircles the first chip, the functional surface of the first chip is arranged facing the first surface, the connection key structure comprises a first connection key and a second connection key which are electrically connected, the distance from the second connection key to the first surface is greater than the distance from the first connection key to the first surface, the distance from the second connection key to the first chip is greater than the distance from the first connection key to the first chip, the first connection key is electrically connected with the functional surface, the second chip is arranged on the second surface, the second chip and the first chip are arranged at the same side of the connection key structure, one end of the bonding metal line is electrically connected with the second connection key, and the other end of the bonding metal line is electrically connected with the second chip. The reliability of the package structure is improved.

Description

封装结构 The package structure

技术领域 FIELD

[0001]本发明涉及半导体制造领域,尤其涉及一种封装结构。 [0001] The present invention relates to semiconductor manufacturing, and more particularly relates to a package structure.

背景技术 Background technique

[0002]晶圆级封装(Wafer Level Packaging,简称WLP)技术是对整片晶圆进行封装测试后再切割得到单个成品芯片的技术。 [0002] The wafer-level package (Wafer Level Packaging, referred WLP) technique is to encapsulate the entire wafer and then cut to give a test individual final chip technology. 与陶瓷无引线芯片载具(Ceramic Leadless ChipCarrier)或有机无引线芯片载具(Organic Leadless Chip Carrier)等模式相比,晶圆级封装技术具有更轻、更小、更短、更薄以及更廉价等优点。 Ceramic leadless chip carrier (Ceramic Leadless ChipCarrier) or an organic leadless chip carrier (Organic Leadless Chip Carrier) mode and the like as compared to wafer level packaging technology has a lighter, smaller, shorter, thinner and less expensive Etc. 晶圆级封装技术是能够将IC设计、晶圆制造、封装测试、基板制造整合为一体的技术,因而成为当前封装领域的热点和未来发展的趋势。 WLP technique is capable of IC design, wafer fabrication, packaging and testing, integrated into one of the substrate fabrication technology, thus becoming hot and packaging field current trend of future development.

[0003]扇出晶圆封装是晶圆级封装的一种。 [0003] fan-out wafer packaging a wafer level package. 扇出晶圆封装方法包括以下工艺步骤:在载体表面形成剥离膜,并在剥离膜表面形成第一介质层,在第一介质层上形成第一图形层,所述第一图形层具有第一开口;在第一开口内形成用于与基板端连接的第一金属电极,在第一图形层表面形成再布线金属层;在第一金属电极表面、再布线金属层表面以及第一介质层表面形成第二介质层,并在第二介质层表面形成第二图形层,所述第二图形层具有第二开口;在第二开口内形成用于与芯片端连接的第二金属电极;将芯片倒装至第二金属电极后,在第二介质层和芯片表面形成塑封层,所述塑封层包围所述芯片,形成封装结构;将载体和剥离膜与封装结构分离;植球回流,形成焊球;单片切割,形成扇出芯片封装结构。 Fan-out wafer packaging method comprising the following process steps: forming the release surface of the carrier film, forming a first dielectric layer and the release film surface, forming a first pattern layer on the first dielectric layer, said first layer having a first pattern opening; opening formed in a first metal for the first electrode connected to the substrate side, a metal layer is formed and then a wiring pattern on a surface of a first layer; a first electrode metal surface, the metal surface of the wiring layer, and then a first dielectric layer surface forming a second dielectric layer, and forming a second pattern layer on the surface of the second dielectric layer, said second layer having a second opening pattern; forming a second metal electrode and a terminal connected to the chip in the second opening; chip after the flip to a second metal electrode formed on the second dielectric layer and the chip surface plastic layer, the plastic layer surrounds the chip, forming a package structure; separating the carrier film and the release package; bumping reflow soldering is formed ball; leadframe cutting, forming a fan-out chip package.

[0004]然而,现有的晶圆级封装技术形成的封装结构的可靠性较差。 [0004] However, the poor reliability of the package structure of a conventional wafer level packaging techniques.

发明内容 SUMMARY

[0005]本发明解决的问题是提供一种封装结构,以提高封装结构的可靠性。 [0005] The present invention solves the problem to provide a package structure, in order to improve reliability of the package structure.

[0006]为解决上述问题,本发明提供一种封装结构,包括:第一芯片,第一芯片具有功能面;基板核心层,所述基板核心层具有相对的第一表面和第二表面,基板核心层包括:塑封结构和位于塑封结构内的连接键结构;所述塑封层包围所述第一芯片,且所述第一芯片的功能面朝向所述第一表面设置;所述连接键结构包括电学连接的第一连接键和第二连接键,第二连接键到第一表面的距离大于第一连接键到第一表面的距离,所述第二连接键到第一芯片的距离大于第一连接键到第一芯片的距离,所述第一连接键与所述功能面电学连接;第二芯片,位于第二表面,所述第二芯片和第一芯片位于连接键结构的同一侧;键合金属线,所述键合金属线的一端与第二连接键电学连接,键合金属线的另一端与第二芯片电学连接。 [0006] In order to solve the above problems, the present invention provides a package structure, comprising: a first chip having a first chip surface function; core layer of the substrate, the substrate core layer having opposing first and second surfaces, the substrate the core layer comprising: a plastic structure and linkages plastic structure located within the structure; the first plastic layer surrounding the chip, the first chip and the functional surface disposed toward the first surface; the linkage structure includes the first linkages and the second linkages electrically connected to the second linkage surface is greater than the first distance from a first surface of a first linkage to said second linkage to the first distance is greater than a first chip linkages distance to the first chip, the first linkage is connected electrically to the functional surface; a second chip located on a second surface, said first chip and the second chip is connected at the same side of the key structure; bond bonding a metal wire, one end of the bond wire is connected to the second electrical linkage, bonding metal wire and the other end electrically connected to the second chip.

[0007]可选的,所述连接键结构还包括中间连接键,第一连接键和第二连接键通过中间连接键电学连接。 [0007] Alternatively, the key structure further includes an intermediate connecting linkages, the first linkage and the second linkage are connected by an intermediate electrical linkage.

[0008]可选的,第一连接键、第二连接键和中间连接键的材料为铜、钨、铝、金或银。 [0008] Alternatively, the first linkage, second linkage and the intermediate material linkages copper, tungsten, aluminum, gold, or silver.

[0009]可选的,所述中间连接键具有相对的第一连接端和第二连接端,第一连接端到第一芯片的距离小于第二连接端到第一芯片的距离,第一连接端与第一连接键连接,第二连接端与第二连接键连接。 [0009] Alternatively, the intermediate linkage having a first connection end and an opposite second end connected to a first end connected to a second distance less than the first chip from a first end connected to the chip, a first connection connecting a first end of the linkage, the second connecting terminal connected to the second linkage.

[0010]可选的,所述第二芯片的表面具有引线端;所述键合金属线的另一端与所述引线端连接。 [0010] Optionally, the surface of the second chip having a lead end; the other end of the bonding metal wire connected to said pin connector.

[0011 ]可选的,所述键合金属线的材料为铜、钨、铝、金或银。 [0011] Optionally, the bonding material of the metal wire is made of copper, tungsten, aluminum, gold, or silver.

[0012]可选的,所述基板核心层还包括:第一焊盘,所述第一焊盘具有相对的第一焊面和第二焊面,第一焊面与第二连接键连接,第二焊面与键合金属线连接。 [0012] Optionally, the substrate core layer further comprises: a first pad, the pad having a first surface opposite to a first weld and the second weld surface, the first weld surface and the second linkage is connected, connected to the second bonding surface bonding metal wires.

[0013]可选的,所述第一连接键包括相对的第一端和第二端,第一端朝向第一表面设置,第二端与第二连接键电学连接。 [0013] Optionally, the first linkage includes opposing first and second ends, a first surface disposed toward the first end, a second end connected to a second electrical linkage.

[0014]可选的,所述基板核心层还包括:第二焊盘和多个第三连接键,所述第二焊盘通过多个第三连接键分别与第一连接键的第一端表面以及功能面连接。 [0014] Optionally, the substrate core layer further comprises: a second plurality of pads and the third linkage, the second pad through a third plurality of linkages to the first end of a first linkage, respectively and a functional surface plane connection.

[0015]可选的,所述功能面包括功能区,所述功能区的表面连接有第三连接键,所述第二焊盘通过功能区表面的第三连接键与功能区连接。 [0015] Alternatively, the functional surface region comprises a functional surface, the functional region is connected to a third linkage, the second pad connected by a linkage with the third functional surface of the functional area regions.

[0016] 可选的,还包括:焊球,位于第二焊盘表面。 [0016] Optionally, further comprising: a solder ball pads located on a second surface.

[0017]可选的,还包括:保护层,所述保护层覆盖所述第二芯片、键合金属线和第二表面。 [0017] Optionally, further comprising: a protective layer, the second protective layer covers the chip, the bonding wire and the second surface.

[0018]可选的,还包括:主粘结层,位于第二芯片和第二表面之间。 [0018] Optionally, further comprising: a primary adhesive layer disposed between the second chip and a second surface.

[0019] 可选的,还包括:无源器件,嵌在塑封结构中,所述无源器件与第一连接键电学连接;所述第一连接键位于所述无源器件和第一芯片之间。 [0019] Optionally, further comprising: a passive device, embedded in the plastic structure, the passive component electrically connected to the first linkage; the linkage is in the first passive device chip and the first between.

[0020]与现有技术相比,本发明的技术方案具有以下优点: [0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021]本发明提供的封装结构,由于连接键结构包括第一连接键和第二连接键,第二连接键到第一芯片的距离大于第一连接键到第一芯片的距离,且第二芯片和第一芯片位于连接键结构的同一侧,因此使得第二连接键到第二芯片的距离大于第一连接键到第二芯片的距离。 [0021] The present invention provides a package structure, since the structure comprises a first linkage and a second linkage linkage, linkage to a second distance from the first chip to the first linkage is greater than the first chip and the second chip and the first chip on the same side of the linkage structure, so that the second key is connected to a second distance greater than the first chip is connected to the distance to the second chip key. 使得第二连接键到第二芯片的距离较大,为所述键合金属线提供了足够的空间,使得键合金属线容易形成,因此键合金属线的可靠性提高。 So that the second key to the second chip connection distance is large, the key to provide sufficient space together metal wires, so that the bonding metal wires easily formed, thus improving the reliability of the bonding of the metal wire. 从而提高了封装结构的可靠性。 Thereby improving the reliability of the packaging structure.

附图说明 BRIEF DESCRIPTION

[0022]图1是一种封装结构的示意图; [0022] FIG. 1 is a schematic diagram of a package structure;

[0023]图2为本发明一实施例提供的封装结构的结构示意图; [0023] Fig 2 a schematic view of the structure of a package structure according to an embodiment of the present invention;

[0024]图3至图13为本发明提供的封装结构的形成过程的结构示意图。 [0024] FIG. 3 to FIG 13 a schematic view of a forming process to provide a package structure of the present invention.

具体实施方式 detailed description

[0025]正如背景技术所述,现有技术形成的封装结构的可靠性有待提高。 [0025] As the background technology, the reliability of the package structure of the prior art is formed to be improved.

[0026]图1是一种封装结构的剖面结构示意图,封装结构包括:第一芯片100,所述第一芯片100具有功能面;塑封层130,所述塑封层130具有相对的第一表面和第二表面,所述塑封层130包围所述第一芯片100,所述第一芯片100的功能面朝向第一表面设置;导电插塞120,位于塑封层130内,所述导电插塞120具有相对的第一总端面和第二总端面,第一总端面朝向第一表面设置,第一总端面与功能面电学连接;第二芯片160,位于第二表面,所述第二芯片160和第一芯片100位于导电插塞120的同一侧;键合金属线170,所述键合金属线170的一端与第二总端面电学连接,所述键合金属线170的另一端与第二芯片160电学连接。 [0026] FIG. 1 is a schematic cross-sectional structure of a package structure, the package structure comprising: a first chip 100, the chip 100 having a first functional surface; 130 plastic layer, the plastic layer 130 having a first surface and a second surface, the plastic layer 130 surrounding the first chip 100, the first chip of the functional surface 100 disposed toward the first surface; conductive plug 120, 130 located within the plastic layer, with the conductive plug 120 opposed first and second end faces total overall end surface, a first total surface disposed toward the first end surface, a first end surface and the total functional surface electrically connected; a second chip 160, located on a second surface, the second chip 160 and the second a chip 100 side of the conductive plug 120 of the same; bonding metal wire 170, the bond end of the metal wire 170 is electrically connected to the second end surface of the total, the other end of the metal bonding wire 170 and the second chip 160 electrically connected.

[0027]所述键合金属线170采用打线工艺形成。 [0027] The bonding metal wires 170 are formed using wire bonding process.

[0028]然而,上述封装结构的可靠性较差,原因在于: [0028] However, the package structure is less reliable because:

[0029]随着特征尺寸的不断减小,导电插塞120到第二芯片160的距离不断减小,导致第二总端面到第二芯片160的距离减小。 [0029] With the feature size decreases, the conductive plug 160 from the chip 120 to the second decreasing, causing the second end face to the total distance to the second chip 160 is reduced. 另外,导电插塞120的第一总端面到第一芯片100的距离等于导电插塞120的第二总端面到第一芯片100的距离。 Further, the first conductive plug total distance from the first end surface 120 of the chip 100 to the conductive plug is equal to the second total distance from the first end surface 120 to the chip 100. 当第二芯片160在第二表面的投影面积大于第一芯片100在第二表面的投影面积时,第二总端面到第二芯片160的距离减小。 When the second chip 160 is greater than the projected area of ​​the second surface of the first chip 100 is in the projected area of ​​the second surface, the second end face to the total distance to the second chip 160 is reduced.

[0030]由于第二总端面到第二芯片160的距离减小,导致提供给键合金属线170的空间较小,导致形成键合金属线170采用打线工艺不能正常进行,影响键合金属线170的形成。 [0030] Since the second end surface of the total distance to the second chip 160 is reduced, resulting in bonding a metal wire to provide a small space 170, resulting in the formation of metal bonding wires 170 using wire process can not normally affect bonding metal line 170 is formed. 从而导致封装结构的可靠性降低。 Resulting in reduced reliability of the package structure.

[0031]在此基础上,本发明提供一种封装结构,包括:第一芯片,第一芯片具有功能面;基板核心层,所述基板核心层具有相对的第一表面和第二表面,基板核心层包括:塑封结构和位于塑封结构内的连接键结构;所述塑封层包围所述第一芯片,且所述第一芯片的功能面朝向所述第一表面设置;所述连接键结构包括电学连接的第一连接键和第二连接键,第二连接键到第一表面的距离大于第一连接键到第一表面的距离,所述第二连接键到第一芯片的距离大于第一连接键到第一芯片的距离,所述第一连接键与所述功能面电学连接;第二芯片,位于第二表面,所述第二芯片和第一芯片位于连接键结构的同一侧;键合金属线,所述键合金属线的一端与第二连接键电学连接,键合金属线的另一端与第二芯片电学连接。 [0031] On this basis, the present invention provides a package structure, comprising: a first chip having a first chip surface function; core layer of the substrate, the substrate core layer having opposing first and second surfaces, the substrate the core layer comprising: a plastic structure and linkages plastic structure located within the structure; the first plastic layer surrounding the chip, the first chip and the functional surface disposed toward the first surface; the linkage structure includes the first linkages and the second linkages electrically connected to the second linkage surface is greater than the first distance from a first surface of a first linkage to said second linkage to the first distance is greater than a first chip linkages distance to the first chip, the first linkage is connected electrically to the functional surface; a second chip located on a second surface, said first chip and the second chip is connected at the same side of the key structure; bond bonding a metal wire, one end of the bond wire is connected to the second electrical linkage, bonding metal wire and the other end electrically connected to the second chip.

[0032]由于连接键结构包括第一连接键和第二连接键,第二连接键到第一芯片的距离大于第一连接键到第一芯片的距离,且第二芯片和第一芯片位于连接键结构的同一侧,因此使得第二连接键到第二芯片的距离大于第一连接键到第二芯片的距离。 [0032] Since the structure comprises a first linkage and a second linkage linkage, linkage to a second distance greater than the first chip to the first linkage from the first chip and the second chip and the chip is located a first connection the same side of the key structure, so that the second key to the second chip connection distance greater than the first distance to the second linkage chip. 使得第二连接键到第二芯片的距离较大,为所述键合金属线提供了足够的空间,使得键合金属线容易形成,因此键合金属线的可靠性提高。 So that the second key to the second chip connection distance is large, the key to provide sufficient space together metal wires, so that the bonding metal wires easily formed, thus improving the reliability of the bonding of the metal wire. 从而提高了封装结构的可靠性。 Thereby improving the reliability of the packaging structure.

[0033]为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。 [0033] For the above-described objects, features and advantages of the present invention can be more fully understood by reading the following detailed description of the drawings Specific embodiments of the present invention binds.

[0034]图2为本发明一实施例提供的封装结构的示意图。 [0034] FIG. 2 is a schematic configuration of a package according to an embodiment of the present invention.

[0035]所述封装结构,参考图2,包括: [0035] The packaging structure, with reference to FIG. 2, comprising:

[0036]第一芯片210,第一芯片210具有功能面; [0036] The first chip 210, chip 210 has a function of a first surface;

[0037]基板核心层,所述基板核心层具有相对的第一表面和第二表面,基板核心层包括:塑封结构和位于塑封结构内的连接键结构; [0037] The core layer of the substrate, the substrate core layer having a first surface and a second surface opposite to the substrate core layer comprising: a plastic structure located within the structural linkages plastic structure;

[0038]所述塑封层包围所述第一芯片210,且所述第一芯片210的功能面朝向所述第一表面设置; [0038] The plastic layer surrounding the first chip 210, and the functional surface of the first chip 210 disposed toward the first surface;

[0039]所述连接键结构包括电学连接的第一连接键240和第二连接键280,第二连接键280到第一表面的距离大于第一连接键240到第一表面的距离,所述第二连接键280到第一芯片210的距离大于第一连接键240到第一芯片210的距离,所述第一连接键240与所述功能面电学连接; [0039] The key structure comprises a first connector electrically connected to linkages 240 and the second linkages 280, 240 to the distance 280 from the first surface to the second surface of the first linkages is greater than a first linkage, the the second linkage 280 to the first chip 210 is greater than the distance from the first linkage 240 to the first chip 210, the first linkage 240 is connected electrically to the functional surface;

[0040] 第二芯片350,位于第二表面,所述第二芯片350和第一芯片210位于连接键结构的同一侧; [0040] The second chip 350, located on a second surface, the second chip 350 and the chip 210 on the same side of the first linkage structure;

[0041] 键合金属线360,所述键合金属线360的一端与第二连接键280电学连接,键合金属线360的另一端与第二芯片350电学连接。 [0041] The bonding metal wire 360, the bond end of the metal wire 360 ​​connected to the second electrical connection key 280, the other end of the metal bonding wire 360 ​​is electrically connected to the second chip 350.

[0042]所述第一芯片210能够为传感器芯片、逻辑电路芯片、存储芯片等。 [0042] The first chip 210 can be a sensor chip, logic chip, memory chips.

[0043]在本实施例中,第一芯片210具有相对的功能面和非功能面,所述第一芯片210的功能面朝向第一表面设置,所述功能面包括功能区。 [0043] In the present embodiment, the first chip 210 having opposite functional surfaces and non-functional surface, the functional surface 210 of the first die toward the first surface, the functional surface comprises a ribbon.

[0044]所述功能区内能够具有晶体管、无源器件(例如电阻、电容和电感等)、存储器件、传感器、电互连结构中的一者或多者。 [0044] the functional region can be a transistor, a passive device (such as resistors, capacitors and inductors, etc.), a memory, a sensor, an electrical interconnect structure of one or more.

[0045]所述第一芯片210的功能区表面暴露出初始焊盘;所述初始焊盘表面具有凸块213,所述凸块213突出于所述第一芯片210的功能面,所述第一芯片210的功能区表面即所述凸块213的底部表面。 Ribbon surface [0045] of the initial first chip pad 210 is exposed; the initial surface having a bump pad 213, the protrusion 213 protruding to the functional surface of the first chip 210, the second a functional surface area of ​​the chip 210, i.e., the bottom surface 213 of the projection.

[0046]所述凸块213的材料包括铜、金或锡,所述凸块213具有预设厚度。 Materials [0046] The bump 213 comprises copper, gold or tin, the bumps 213 having a predetermined thickness. 所述凸块213能够与功能区内的电路或器件实现电连接。 The bump 213 can be electrically connected to the circuit or device function area. 所述凸块213用于与后续设置的连接键结构进行电连接,从而实现第一芯片210的功能区与后续形成的第二芯片和无源器件、以及外部电路之间的电连接。 The bumps 213 for electrical connection with the connection set subsequent key structure, thereby achieving an electrical connection between the first chip and the second functional region 210 and the passive chip devices subsequently formed, and an external circuit.

[0047]所述第一连接键240具有相对的第一端和第二端,第一端朝向第一表面设置,第二端与第二连接键电学连接。 [0047] The first linkage 240 having opposite first and second ends, a first surface disposed toward a first end, a second end connected to a second electrical linkage.

[0048]所述连接键结构还包括中间连接键260。 [0048] The key structure further includes an intermediate connecting linkage 260. 第二连接键280通过中间连接键260和第一连接键240电学连接。 The second linkages 260 and 280 bond first linkage 240 is connected through an intermediate electrical connector.

[0049]所述第一连接键240、中间连接键260和第二连接键280的材料为导电材料,所述导电材料为铜、妈、招、金或银。 [0049] 240 of the first linkage, the intermediate linkage and the second linkage 280 260 a material is a conductive material, the conductive material is copper, mother, strokes, gold or silver.

[0050]所述中间连接键260具有相对的第一连接端和第二连接端,第一连接端到第一芯片210的距离小于第二连接端到第一芯片210的距离,第一连接端与第一连接键240连接,第二连接端与第二连接键280连接。 [0050] The intermediate linkage 260 having opposite first connection end and a second connection end, connected to a first distance from the first end to the second chip 210 is less than the distance of the first end connected to the chip 210, a first connecting end a first linkage 240 is connected to the second connection terminal 280 is connected to the second linkage.

[0051 ]具体的,中间连接键260的第一连接端与第一连接键240的第二端连接。 [0051] Specifically, the intermediate bond 260 connected to a first end connected to the first linkage 240 is connected to a second end.

[0052]由于第一连接端到第一芯片210的距离小于第二连接端到第一芯片210的距离,第一连接键240与第一连接端连接,第二连接键280与第二连接端连接,因此使得在平行于第二表面的方向上,第二连接键280到第一芯片210的距离大于第一连接键240到第一芯片210的距离。 [0052] Since the first connecting end 210 is less than the distance of the first chip from a first end to the second connection chip 210, a first linkage 240 is connected to the first connecting end, a second linkage 280 is connected to the second end connection, so that in a direction parallel to the second surface, the second linkage 280 from the chip 210 to the first distance 240 to the first chip 210 is greater than a first linkage.

[0053]所述基板核心层还包括:第一焊盘300,第一焊盘300具有相对的第一焊面和第二焊面,第一焊面与第二连接键280连接,第二焊面与键合金属线360连接。 [0053] The core substrate layer further comprises: a first pad 300, pad 300 having a first opposing face and the second solder bonding a first surface, a first bonding surface and the second linkage 280 is connected to the second welding and the bonding surface 360 ​​bonding wires.

[0054]所述第一焊盘300的材料为金属,如铜、钨、铝、金或银。 Materials [0054] The first pad 300 is a metal, such as copper, tungsten, aluminum, gold, or silver.

[0055] 所述基板核心层还包括:第二焊盘340和多个第三连接键320,所述第二焊盘340通过多个第三连接键320分别与第一连接键240的第一端表面以及功能面连接。 [0055] The core substrate layer further comprises: a plurality of second pads 340 and third linkages 320, 340 through the second pad of the third plurality of first linkages 320 are connected to the first bond 240 end surface and a plane connection function.

[0056]具体的,功能区的功能面连接有第三连接键320,所述第二焊盘340通过功能区表面的第三连接键320与功能区连接。 [0056] Specifically, the functional surface of the ribbon is connected to the third linkage 320, the second pad 340 is connected by a third key function region 320 is connected to the surface of the ribbon.

[0057]所述功能面与第一连接键240电学连接。 The [0057] functional surface 240 connected to the first electrical linkage. 具体的,所述功能面通过第二焊盘340和第三连接键320实现与第一连接键240的电学连接。 Specifically, to realize the functional surface 320 electrically connected to a first linkage 240 by the second pad 340 and the third linkage.

[0058] 所述封装结构还包括无源器件220,所述无源器件220嵌在塑封结构中。 [0058] The package 220 further comprises a passive device, the passive device 220 is embedded in the plastic structure. 所述第一连接键240位于所述无源器件220和第一芯片210之间。 The first linkage 240 is located between the passive component 220 and the first chip 210.

[0059] 所述无源器件220可以为电阻、电容、电感、转换器、渐变器、谐振器、滤波网、混频器或开关。 [0059] The device 220 may be a passive resistors, capacitors, inductors, switches, fader, a resonator, a filter network, a switch or a mixer.

[0060]具体的,所述无源器件220具有相对的第三表面和第四表面,所述第三表面朝向所述第一表面设置。 [0060] Specifically, the passive component 220 has opposite third and fourth surfaces, the third surface toward the first surface.

[0061]所述无源器件220与第一连接键240电学连接。 [0061] The passive device 220 is connected electrically to the first linkage 240. 具体的,所述第三表面与第一连接键240电学连接。 Specifically, the third surface 240 and electrically connected to the first linkage.

[0062] 所述第三表面也连接有第三连接键320,所述第二焊盘340通过多个第三连接键320分别与第一连接键240的第一端表面、功能面、以及第三表面连接。 [0062] The third surface is also connected to the third linkage 320, the second pad 340 through a plurality of third keys 320 are respectively connected to a first end surface and the first linkage 240, the functional surface, and a second three connecting surfaces.

[0063]所述塑封结构、连接键结构、第一焊盘300,第三连接键320和第二焊盘340构成基板核心层。 [0063] The plastic structure, the structure of linkages, the first pad 300, the third linkage 320 and the second pad 340 of the substrate constituting the core layer.

[0064]所述第二芯片350能够为传感器芯片、逻辑电路芯片、存储芯片等。 [0064] The second chip 350 can be a sensor chip, logic chip, memory chips.

[0065]所述第二芯片350通过主粘结层固定在第二表面。 [0065] The second chip 350 through the primary adhesive layer fixed to the second surface. 所述主粘结层的材料为UV胶或者其它粘性材料。 The main material of the adhesive layer is a UV adhesive or other viscous materials.

[0066]所述第二芯片350的表面具有引线端;所述键合金属线360的另一端与所述引线端连接,从而实现键合金属线360与第二芯片350的电学连接。 [0066] surface of the second chip 350 having lead terminals; bonding metal wires 360 and the other end connected to said pin, in order to achieve bonding metal wire 360 ​​electrically connected to the second chip 350.

[0067]所述键合金属线360的材料为金属,如铜、钨、铝、金或银。 [0067] The bonding metal wire material 360 is a metal, such as copper, tungsten, aluminum, gold, or silver.

[0068] 本实施例中,所述键合金属线360的一端通过第一焊盘300与第二连接键280电学连接,所述键合金属线360的另一端与所述引线端连接。 [0068] In this embodiment, the bond end of the metal wire 360 ​​is connected by a first bond pad 300 and 280 electrically connected to the second, the bonding metal wires 360 connected to the other end of said pin.

[0069]由于第二连接键280到第一芯片210的距离大于第一连接键240到第一芯片210的距离,且第二芯片350和第一芯片210位于连接键结构的同一侧,因此使得第二连接键280到第二芯片350的距离大于第一连接键240到第二芯片350的距离。 [0069] Since the distance between the second linkage 280 to the first chip 210 is greater than the first distance 240 to the linkage 210 of the first chip and the second chip 350 and the chip 210 on the same side of the first linkage structure, so that the second linkage 280 from chip 350 to the second key is greater than the first distance 240 is connected to the second chip 350. 使得第二连接键350到第二芯片350的距离较大,为所述键合金属线360提供了足够的空间,使得键合金属线360容易形成,因此键合金属线360的可靠性提尚。 Such that the second linkage 350 from the chip 350 to the second large metal line 360 ​​provides sufficient space for the bonding wires so that the bonding metal 360 is easily formed, so the reliability of the bonding of the metal wire 360 ​​still provide . 从而提尚了封装结构的可靠性。 Thereby improving the reliability of the packaging structure yet.

[0070]所述封装结构还包括保护层370,所述保护层370覆盖所述第二芯片350、键合金属线360和第二表面。 [0070] The package structure 370 further comprises a protective layer, the protective layer 370 covers the second chip 350, bonding wires 360 and the second surface of the metal.

[0071]所述保护层370的材料为绝缘材料,所述绝缘材料为有机绝缘材料或无机绝缘材料。 Materials [0071] The protective layer 370 is an insulating material, the insulating material is an organic insulating material or inorganic insulating material.

[0072]在一实施例中,所述保护层370的材料为有机绝缘材料时,所述有机绝缘材料包括聚氯乙烯或树脂;所述树脂包括环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂或聚苯并恶唑树月旨。 The material [0072] In one embodiment, the protective insulating layer 370 is an organic material, the organic insulating material or a resin include polyvinyl chloride; the resin comprises an epoxy resin, a polyimide resin, a coumarone cyclobutene resin or polybenzoxazole purpose tree months. 在另一实施例中,所述保护层370的材料为无机绝缘材料,所述无机绝缘材料包括氧化硅、氮化硅和氮氧化硅中的一种或多种。 In another embodiment, the material is an inorganic insulating material of the protective layer 370, the inorganic insulating material comprises one or more of silicon oxide, silicon nitride and silicon oxide.

[0073] 所述封装结构还包括焊球380,所述焊球380位于第二焊盘340表面。 [0073] The package structure further includes a ball 380, the ball 380 is located in a second surface of the pad 340.

[0074] 所述焊球380的材料包括锡。 Materials [0074] The solder balls 380 comprises tin.

[0075] 在所述第二焊盘340与所述焊球380之间,还能具有球下金属结构(Under BallMetal,简称UBM)。 [0075] between the second pad 340 and the ball 380, can also have a metal structure (Under BallMetal, referred to as UBM) under the ball. 所述球下金属结构能够包括单层金属层或多层重叠的金属层;所述单层金属层或多层金属层的材料包括铜、铝、镍、钴、钛、钽中的一种或多种组合。 The metal structure can comprise a single layer of metal balls lower layer or multi-layer overlapping metal; a single metal layer or multiple metal layers of materials include copper, aluminum, nickel, cobalt, titanium, tantalum, one or a variety of combinations.

[0076]下面结合图3至图13详细介绍上述实施例中封装结构的形成过程。 [0076] below with reference to FIGS. 3 to 13 in detail the formation of the above-described embodiments of the package structure.

[0077]参考图3,提供载板200,所述载板200包括第五表面201。 [0077] Referring to FIG 3, a carrier plate 200, the carrier plate 200 includes a fifth surface 201.

[0078]所述载板200为后续工艺提供工作平台,用于承载第一芯片、后续形成的部分塑封结构、以及后续形成的部分连接键结构。 [0078] The carrier plate 200 to provide a working platform for the subsequent process, for carrying a first chip structure subsequently formed plastic portion, and a portion of the linkage structure subsequently formed.

[0079]所述载板200具有相对的第五表面201和第六表面202。 [0079] The carrier plate 200 has a fifth surface 201 and an opposite sixth surface 202.

[0080]在本实施例中,所述载板200为硬性基板,所述硬性基板为PCB基板、玻璃基板、金属基板、半导体基板或聚合物基板。 [0080] In the present embodiment, the carrier plate 200 is a rigid substrate, the rigid substrate is a PCB substrate, a glass substrate, a metal substrate, a semiconductor substrate or a polymer substrate. 所述硬性基板具有较高的硬度,不易发生形变,在后续工艺中提供足够的支撑力。 The rigid substrate has a high hardness, less prone to deformation, providing sufficient support force in a subsequent process.

[0081 ]在其它实施例中,所述载板还能够为软性基板。 [0081] In other embodiments, the carrier plate can also be of a flexible substrate.

[0082]继续参考图3,在所述载板200的第五表面201固定第一芯片210,第一芯片210具有相对的功能面211和非功能面212,所述功能面211包括功能区,所述第一芯片210的功能面211朝向第五表面201设置。 [0082] With continued reference to FIG. 3, the carrier plate 200 is fixed to the fifth surface 201 of the first chip 210, chip 210 having opposing first surface 211 and a function non-functional surface 212, surface 211 includes a function of the functional region, the first functional surface 210 of the chip 211 toward the fifth surface 201 is provided.

[0083]所述第一芯片210能够为传感器芯片、逻辑电路芯片、存储芯片等。 [0083] The first chip 210 can be a sensor chip, logic chip, memory chips. 所述功能面211的功能区内能够具有晶体管、无源器件(例如电阻、电容和电感等)、存储器件、传感器、电互连结构中的一者或多者。 The surface features can have a function of a transistor region 211, passive components (e.g. resistors, capacitors and inductors, etc.), a memory, a sensor, an electrical interconnect structure of one or more.

[0084]所述第一芯片210的形成步骤包括:提供衬底,所述衬底具有若干芯片区,所述衬底包括相对的第一初始表面和第二初始表面,所述衬底的第二初始表面的芯片区内具有功能区;对所述衬底进行切割,使若干芯片区相互分离,形成独立的第一芯片210。 Forming step [0084] 210 of the first chip comprising: providing a substrate having a plurality of chip regions, the substrate comprising a first opposing surface and a second initial initial surface of the second substrate two initial surface area of ​​the chip having a functional area; the substrate is cut so that a plurality of chip regions are separated from each independent of the first chip 210 is formed.

[0085]在本实施例中,所述第一芯片210的功能区表面暴露出初始焊盘;所述初始焊盘表面具有凸块213,所述凸块213突出于所述第一芯片210的功能面211,所述第一芯片210的功能区表面即所述凸块213的底部表面。 [0085] In the present embodiment, the first functional region 210 of the chip surface is exposed initial pad; the initial surface having a bump pad 213, the bump 213 protruding from the first chip 210 functional surface 211, 210 of the first chip surface of the ribbon i.e., the bottom surface 213 of the bump.

[0086]所述凸块213的材料包括铜、金或锡,所述凸块213具有预设厚度。 Materials [0086] The bump 213 comprises copper, gold or tin, the bumps 213 having a predetermined thickness. 所述凸块213能够与功能区内的电路或器件实现电连接。 The bump 213 can be electrically connected to the circuit or device function area. 所述凸块213用于与后续设置的连接键结构进行电连接,从而实现第一芯片210的功能区与后续形成的第二芯片和无源器件、以及外部电路之间的电连接。 The bumps 213 for electrical connection with the connection set subsequent key structure, thereby achieving an electrical connection between the first chip and the second functional region 210 and the passive chip devices subsequently formed, and an external circuit.

[0087]所述第一芯片210的功能面211通过粘结层(未图示)固定于所述载板200的第五表面201。 [0087] The first functional surface 210 of the chip 211 by an adhesive layer (not shown) is fixed to the fifth surface 200 of the carrier plate 201.

[0088]本实施例中,所述粘结层的材料为UV胶,所述UV胶经紫外线照射后粘性降低,以便后续将载板200从封装结构中剥离。 [0088] In this embodiment, the material of the adhesive layer is a UV adhesive, the UV adhesive by ultraviolet irradiation after the reduction in viscosity, the carrier plate 200 for subsequent release from the package structure. 所述粘结层的材料还可以为其它粘性材料。 The material of the adhesive layer may also be other viscous materials.

[0089]在一个实施例中,在所述第一芯片210的功能面211粘附粘结层,再将所述粘结层粘附于载板200的第五表面201,以实现第一芯片210与载板200之间的粘结。 [0089] In one embodiment, the functional surface of the first chip 210 of the adhesive layer 211 adhesive, then the adhesive layer is adhered to the carrier plate 200 of the fifth surface 201 to achieve a first chip 210 and the adhesion between the carrier plate 200. 在另一个实施例中,在所述载板的第五表面需要固定第一芯片的对应位置形成粘结层,再将第一芯片的功能面粘附于所述粘结层表面,使所述第一芯片固定于载板的第五表面。 In another embodiment, necessary to fix the position corresponding to the first chip surface of the carrier plate in the fifth adhesive layer is formed, and then a first functional surface of the chip is adhered to the surface of the adhesive layer, the the first chip is fixed to a carrier plate of the fifth surface.

[0090]在本实施例中,所述载板200的第五表面201全局覆盖所述粘结层。 [0090] In the present embodiment, the fifth surface 200 of the carrier plate 201 a global layer covering the adhesive.

[0091 ] 本实施例中,还包括:在所述载板200的第五表面201固定无源器件220。 [0091] In this embodiment, further comprising: a passive device 201 is fixed on the fifth surface 220 of the carrier plate 200. 所述无源器件220通过所述粘结层固定于所述载板200的第五表面201。 The passive device 220 through the adhesive layer fixed to the carrier plate 200. The fifth surface 201.

[0092]所述无源器件220具有相对的第三表面和第四表面,所述第三表面和第五表面201固定。 [0092] The passive component 220 has opposite third and fourth surfaces, the third surface and the fifth surface 201 is fixed.

[0093] 所述无源器件220可以为电阻、电容、电感、转换器、渐变器、谐振器、滤波网、混频器或开关。 [0093] The device 220 may be a passive resistors, capacitors, inductors, switches, fader, a resonator, a filter network, a switch or a mixer.

[0094] 参考图4,在所述第五表面201形成第一塑封层230和贯穿第一塑封层230的第一连接键240,所述第一塑封层230包围第一芯片210。 [0094] Referring to FIG 4, the fifth surface 201 and a first plastic layer 230 through the first plastic layer 240 of a first linkage 230 is formed, the first plastic layer 230 surrounds the first chip 210.

[0095]本实施例中,所述第一塑封层230还覆盖所述无源器件220。 [0095] In this embodiment, the first plastic layer 230 also covers the passive device 220.

[0096]所述第一连接键240用于后续构成连接键结构的一部分。 [0096] The first linkage 240 for constituting a part of a subsequent linkage structure. 所述第一连接键240的材料为导电材料,所述导电材料为铜、钨、铝、金或银。 The first linkage 240 material is a conductive material, the conductive material is copper, tungsten, aluminum, gold, or silver.

[0097]所述第一塑封层230为感光干膜、非感光干膜或者塑封材料膜。 [0097] The first plastic photosensitive dry film layer 230, the non-photosensitive dry film or plastic material film.

[0098]在一实施例中,所述第一塑封层230为感光干膜,所述第一塑封层230的形成工艺为真空贴膜工艺。 [0098] In one embodiment, the first plastic layer is a photosensitive dry film 230, the process of forming the first plastic film layer 230 is a vacuum process. 在另一实施中,所述第一塑封层230的材料为塑封材料,所述塑封材料包括环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、乙烯-醋酸乙烯共聚物、聚乙烯醇或其它合适的聚合物材料。 In another embodiment, the plastic material of the first layer 230 of plastic material, said plastic material comprises an epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polyethylene polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene - vinyl acetate ethylene copolymers, polyvinyl alcohol, or other suitable polymeric material. 在其它实施例中,所述第一塑封层材料也可以为其它绝缘材料。 In other embodiments, the first layer of plastic material may be other insulating materials.

[0099] 本实施例中,在所述第五表面201形成第一塑封层230,所述第一塑封层230包围所述第一芯片210且暴露出所述非功能面212,所述第一塑封层230还覆盖所述无源器件220,所述第一塑封层230中具有第一开口(未图不),所述第一开口暴露出载板200的第五表面201;采用电镀工艺或者溅射工艺在所述第一开口中形成第一连接键240。 [0099] In this embodiment, the first plastic layer 230 on the fifth surface 201 is formed, the first plastic 230 surrounding the chip a first layer 210 and expose the non-functional surface 212, the first plastic layer 230 also covers the passive component 220, the first plastic layer having a first opening 230 (FIG does not), the fifth surface 201 to expose the first opening 200 of the carrier plate; using an electroplating process or a first linkage sputtering process in the first opening 240.

[0100]所述第一连接键240具有相对的第一端和第二端,第一端朝向第五表面201设置,第一塑封层230暴露出第一连接键240的第二端。 [0100] The first linkage 240 having opposite first and second ends, the first end disposed toward the fifth surface 201, a first plastic layer 230 to expose the first end 240 of a second linkage. 后续形成的中间连接键与第一连接键240的第二端连接。 The intermediate linkage to the subsequent formation of a first linkage 240 is connected to a second end.

[0101]具体的,形成第一塑封层230的步骤包括:在所述第五表面201形成覆盖所述第一芯片210和无源器件220的第一塑封膜;对所述第一塑封膜进行抛光,直至暴露出所述第一芯片210的非功能面212;然后图形化所述初始塑封层,从而形成第一塑封层230,第一塑封层230中具有第一开口。 [0101] Specifically, the step 230 includes a first plastic layer is formed: the first chip 201 is formed to cover the first plastic film 210 and the passive device 220 of the fifth surface; the first plastic film polishing, until exposing the surface 212 of the first chip 210 is non-functional; then patterning the initial plastic layer, to thereby form a first plastic layer 230, a first plastic layer 230 having a first opening.

[0102]在其它实施例中,所述第一塑封层还可以覆盖所述非功能面。 [0102] In other embodiments, the first plastic layer also may cover the non-functional surface. 相应的,形成第一塑封层的步骤为:在所述第一子表面形成覆盖所述第一芯片和无源器件的第一塑封膜;图形化所述第一塑封膜,从而形成第一塑封层,第一塑封层中具有第一开口。 A respective step, a first plastic layer is formed as follows: forming a first plastic film covering the first chip and passive components in the first sub-surface; patterning said first plastic film, to thereby form a first plastic layer, a first plastic layer having a first opening.

[0Ί03] 所述第一塑封膜的形成工艺包括注塑工艺(inject1n molding)、转塑工艺(transfer molding)或丝网印刷工艺。 [0Ί03] The process of forming a first film comprising a plastic injection molding processes (inject1n molding), transfer molding process (transfer molding) or a screen printing process.

[0104]形成第一塑封膜采用的注塑工艺包括:提供模具;在所述模具中填充塑封材料,使所述塑封材料包覆所述第一芯片210和无源器件220;对所述塑封材料进行升温固化,形成第一塑封膜。 [0104] a first plastic film is formed using an injection molding process comprising: providing a mold; molding material filled in the mold, the plastic material covering the first chip 210 and the passive device 220; the plastic material heating for curing, a first plastic film.

[0105]在其它实施例中,可以是:在所述第一芯片周围的第五表面固定第一连接键,所述第一连接键具有相对的第一端和第二端,所述第一端与第五表面固定,所述第一连接键的第二端部高于非功能面或者与所述非功能面齐平;在所述第五表面形成包围所述第一芯片的第一塑封层,所述第一塑封层暴露出第二端。 [0105] In other embodiments, may be: the fifth surface of the first chip secured around a first linkage, said first linkage having a first end and a second opposite end, said first the fixed end of the fifth surface, the second end of the first linkage surface is higher than the non-functional or non-functional surface of said flush; is formed surrounding the first chip of the fifth surface of the first plastic layer, the first plastic layer to expose a second end.

[0106]具体的,所述第一连接键的第一端部通过所述粘结层固定在第五表面。 [0106] Specifically, a first end of the first linkage by the adhesive layer is fixed on the fifth surface.

[0107] 参考图5,在所述第一塑封层230和第一连接键240的表面、以及第一芯片210上形成第二塑封层250和贯穿所述第二塑封层250的中间连接键260,所述中间连接键260与第一连接键240连接。 [0107] Referring to FIG 5, a second molding layer on a surface of the first plastic layer 230 and the first linkages 240 and the first chip 210 through 250 and the second plastic layer of the intermediate linkages 260 250 the intermediate linkage 260 is connected to the first linkage 240.

[0108]所述第二塑封层250的材料参照第一塑封层230的材料;所述中间连接键260的材料参照第一连接键240的材料,不再详述。 Materials [0108] The second plastic material of the first layer 250 of the plastic layer 230. Referring; said intermediate connecting material of the material of the first reference key 260 of the linkages 240, not described in detail.

[0109]所述中间连接键260用于后续构成连接键结构的一部分。 [0109] The intermediate connection portion constituting a subsequent linkage structure 260 for the key.

[0110]所述第一连接键240通过中间连接键260与后续形成的第二连接键连接,从而实现第一连接键240和后续形成的第二连接键的电学连接。 [0110] The first linkage 240 and second linkage 260 connected to subsequent linkage formed by the intermediate, thereby achieving an electrical connection of the second linkage and first linkage 240 subsequently formed.

[0111]所述中间连接键260具有相对的第一连接端和第二连接端,第一连接端到第一芯片210的距离小于第二连接端到第一芯片210的距离,第一连接端与第一连接键240连接,第二连接端与后续形成的第二连接键连接。 [0111] The intermediate linkage 260 having opposite first connection end and a second connection end, connected to a first distance from the first end to the second chip 210 is less than the distance of the first end connected to the chip 210, a first connecting end , and a second end connected to a second linkage connected to the subsequent formation of a first linkage 240 is connected.

[0112]具体的,所述中间连接键260的第一连接端与第一连接键240的第二端连接。 [0112] Specifically, the intermediate linkage 260 is connected to a first end of the first linkage 240 is connected to a second end.

[0113]本实施例中,在所述第一塑封层230和第一连接键240的表面、以及第一芯片210上形成第二塑封层250,所述第二塑封层250中具有暴露出第一连接键240的第二开口(未图示),具体的,所述第二开口暴露出第一连接键240第二端;采用电镀工艺或者溅射工艺在所述第二开口中形成中间连接键260。 [0113] In this embodiment, the second plastic layer 250 is formed on a surface of said first plastic layer 230 and the first linkages 240, and a first chip 210, the second plastic layer 250 having a first exposing a bond connecting the second opening 240 (not shown). specifically, the second opening 240 exposes the first linkage second end; using an electroplating process or a sputtering process in the second intermediate connection opening key 260.

[0114]具体的,所述第二塑封层250的形成步骤包括:在所述第一塑封层230和第一连接键240的表面、以及第一芯片210上形成第二塑封膜;对所述第二塑封膜进行图形化,形成第二塑封层250,且所述第二塑封层250内具有第二开口。 [0114] Specifically, the step of forming the second plastic layer 250 comprises: a second plastic film is formed on a surface of said first plastic layer 230 and the first linkages 240, and a first chip 210; the patterning a second plastic film, a second plastic layer 250 is formed, and the second plastic layer 250 having a second opening.

[0115]在其它实施例中,可以是:在所述第一连接键的表面和部分第一塑封层的表面先形成中间连接键;然后在所述第一塑封层的表面和第一芯片上形成包围所述中间连接键的第二塑封层,所述第二塑封层暴露出中间连接键的表面。 [0115] In other embodiments, may be: the first surfaces and the linkage portion of the first plastic layer is formed to the intermediate connector; then the surface of the first plastic layer and a first chip forming a second plastic layer surrounding the intermediate linkages, the intermediate layer to expose the second plastic of the connecting surface of the key.

[0116]参考图6,在所述第二塑封层250和中间连接键260的表面形成第三塑封层270和贯穿第三塑封层270的第二连接键280,第二连接键280与中间连接键260连接。 [0116] Referring to FIG 6, the second intermediate layer 250 and the molding surface of the key 260 is connected to the third layer 270 and the plastic through a third plastic layer 280 of the second linkages 270 is formed, a second linkage 280 connected to the intermediate key 260 is connected.

[0117]所述第三塑封层270的材料参照第一塑封层230的材料,第二连接键280的材料参照第一连接键240的材料,不再详述。 Materials [0117] The third layer 270 of the plastic material of the first reference layer 230 of the plastic material of the second linkage 280 connected to a first reference keying material 240, not described in detail.

[0118]具体的,第二连接键280与中间连接键260的第二连接端连接。 [0118] Specifically, the second linkage 280 connected to a second end connected to the intermediate bond 260 is connected.

[0119]所述第二连接键280用于后续构成连接键结构的一部分。 [0119] The second linkage 280 for constituting a part of a subsequent linkage structure.

[0120]由于第二连接端到第一芯片210的距离大于第一连接端到第一芯片210的距离,第一连接键240与第一连接端连接,第二连接键280与第二连接端连接,因此使得在平行于第一子表面201的方向上,第二连接键280到第一芯片210的距离大于第一连接键240到第一芯片210的距离。 [0120] Since the second end connected to the first chip 210 is greater than a first distance from a first end connected to the chip 210, a first linkage 240 is connected to the first connecting end, a second linkage 280 is connected to the second end connection, thus making the sub-surface 201 is parallel to the first direction, the second key is connected to a first distance 280 from the chip 210 to 240 of the first chip 210 is greater than a first linkage.

[0121]本实施例中,在所述第二塑封层250和中间连接键260的表面形成第三塑封层270,所述第三塑封层270中具有暴露出中间连接键260的第三开口(未图示),具体的,所述第三开口暴露出第二连接端;采用电镀工艺或者溅射工艺在所述第三开口中形成第二连接键280。 [0121] In this embodiment, the connection surface of the key 260 is formed in a third molding the second plastic layer 270 and intermediate layer 250, the third plastic layer 270 having a third opening exposing the intermediate linkage 260 ( not shown). specifically, the third opening exposing a second connection end; and a second linkage 280 using a sputtering process or plating process is formed in the third opening.

[0122]具体的,所述第三塑封层270的形成步骤包括:在所述第二塑封层250和中间连接键260的表面形成第三塑封膜;对所述第三塑封膜进行图形化,形成第三塑封层270,且所述第三塑封层270内具有第三开口。 [0122] Specifically, the step of forming a third plastic layer 270 comprising: a connection surface of the key 260 in the second plastic layer 250 and the third intermediate plastic film is formed; the third patterned plastic film, forming a third plastic layer 270, and a third opening having a third plastic layer 270.

[0123]在其它实施例中,可以是:在所述第二连接端固定连接第二连接键;之后,在所述第二塑封层和中间连接键的表面形成包围所述第二连接键的第三塑封层,所述第三塑封层暴露出第二连接键的表面。 [0123] In other embodiments, may be: in the second connecting end is fixedly connected to a second linkage; Thereafter, a second linkage surrounds the surface of the plastic layer and the second intermediate linkages a third layer of plastic, plastic surface of the third layer to expose a second linkages.

[0124] 参考图7,在第二连接键280和第三塑封层270的表面形成第一焊盘300和包围第一焊盘300的第四塑封层290,所述第四塑封层290暴露出第一焊盘300的表面,第一焊盘300与第二连接键280连接。 [0124] Referring to Figure 7, a first pad 300 is formed surrounding the first pad and the fourth plastic layer 290 on the surface 300 of the second linkages 280 and 270 of the third plastic layer, the plastic layer 290 to expose the fourth surface of the first pad 300, the first pad 300 and the second linkage 280 is connected.

[0125]所述第一焊盘300的材料为金属,如铜、钨、铝、金或银。 Materials [0125] The first pad 300 is a metal, such as copper, tungsten, aluminum, gold, or silver.

[0126]所述第一焊盘300具有相对的第一焊面和第二焊面,第一焊面与第二连接键280连接,第二焊面与后续形成的键合金属线连接。 [0126] The first pad 300 having a first opposing face and the second solder bonding surface, the first weld surface and the second linkage 280 is connected, is connected to the second bonding surface bonded to a metal wire formed later.

[0127] 本实施例中,先形成第一焊盘300,第一焊盘300位于第二连接键280表面和部分第三塑封层270的表面;然后在所述第三塑封层270的表面形成包围所述第一焊盘300的第四塑封层290,所述第四塑封层290暴露出第一焊盘300的第二焊面。 [0127] In this embodiment, the first pad 300 is first formed, the first pad 300 located on the surface 280 and the second linkage surface of the plastic portion of the third layer 270; then formed on the surface of the third plastic layer 270 the surround 290, the fourth plastic layer 290 exposing the first solder pad of the second surface of the first pad 300 of the fourth layer 300 of plastic.

[0128] 形成所述第四塑封层290的工艺为丝网印刷工艺,如丝网印刷绿油工艺。 [0128] The process of forming the fourth layer 290 of plastic screen printing process, such as screen printing process green oil.

[0129]本实施例中,所述第四塑封层290还覆盖部分第一焊盘300的第二焊面。 [0129] In this embodiment, the fourth plastic layer 290 also covers the second surface portion of the first bonding pad 300.

[0130]在其它实施例中,可以是:先形成第四塑封层,所述第四塑封层中具有暴露出第二连接键表面的第四开口,在所述第四开口中形成第一焊盘。 [0130] In other embodiments, it may be: plastic to form a fourth layer, the fourth layer of plastic having a fourth opening to expose a second surface of the linkage, said fourth opening formed in a first weld plate.

[0131]参考图8,形成第一焊盘300和第四塑封层290后,去除载板200(参考图7),所述第一塑封层230的表面暴露出功能面211和第一连接键240的第一端表面。 [0131] Referring to Figure 8, a first pad 300 and the fourth plastic layer 290 after removing the carrier sheet 200 (see FIG. 7) to expose the surface of the functional surface 230 of the first plastic layer 211 and the first linkages a first end surface 240.

[0132]具体的,去除载板200后,所述第一塑封层230的表面暴露出功能区的表面。 The surface area of ​​the exposed surface of the first plastic layer features 230 [0132] Specifically, after removing the carrier plate 200.

[0133]本实施例中,所述第一塑封层230的表面还暴露出无源器件220的第三表面。 [0133] In this embodiment, the molding surface of the first layer 230 also exposes the third surface 220 of the passive devices.

[0134]在本实施例中,由于所述载板200的第五表面201全局覆盖所述粘结层,所述粘结层的材料为UV胶,所述第一芯片210、第一连接键240和无源器件220通过所述粘结层与所述载板200的第五表面201固定,且所述第一塑封层230形成于所述粘结层表面,因此能够通过对所述粘结层进行紫外光照射,使粘结层的粘性降低,然后将所述载板200从所述第一芯片210的功能面211、第一连接键240的第一端和第一塑封层230表面剥离,从而暴露出第一芯片210的功能面、第一连接键240的第一端表面和无源器件220的第三表面。 [0134] In the present embodiment, since the fifth surface 200 of the carrier plate 201 covering the global layer of adhesive, the adhesive material is a UV adhesive layer, the first chip 210, a first linkage 240 and passive components 220 is fixed by the adhesive layer and the fifth surface 200 of the carrier plate 201, and the first molding layer 230 is formed on the surface of the adhesive layer by the adhesive can be layer was irradiated with ultraviolet light, to reduce the viscosity of the adhesive layer, and then the carrier plate 200 from the first chip 210 is functional surface 211, a first end of a first linkage 240 and the release surface of the first plastic layer 230 , thereby exposing the surface of the third functional surface of the first chip 210, a first end surface of the first linkages 240 and 220 passive components.

[0135]在剥离所述载板200之后,采用清洗工艺以去除残留的粘结层。 [0135] After peeling off the carrier plate 200 by the cleaning process to remove the remaining adhesive layer.

[0136]在其它实施例中,还能够通过刻蚀工艺或化学机械抛光工艺去除所述载板。 [0136] In other embodiments, the carrier plate can also be removed by an etching process or chemical mechanical polishing process.

[0137]参考图9,去除所述载板200后,在所述第一塑封层230和第一连接键240的第一端表面、以及功能面211形成第五塑封层310和多个第三连接键320,所述第三连接键320贯穿所述第五塑封层310,所述第三连接键320分别连接于第一连接键240的第一端表面和功能面211。 [0137] Referring to FIG 9, after removing the carrier plate 200, forming a fifth layer 310, and a plurality of third molding the first plastic layer 230 and a first end of a first linkage surface 240, surface 211 and a function linkage 320, the third through the fifth linkage 320 plastic layer 310, the third linkage 320 are respectively connected to the first end surface and a first linkage surface 211 functions 240.

[0138]具体的,所述第三连接键320连接于功能区的表面。 [0138] Specifically, the third linkage 320 is connected to the ribbon surface.

[0139]本实施例中,所述无源器件220的第三表面也连接有第三连接键320。 [0139] In this embodiment, the third surface 220 of the passive device is also connected to the third linkage 320.

[0140]具体的,在所述第一塑封层230和第一连接键240的第一端表面、无源器件220的第三表面、以及功能面211形成第五塑封层310,所述第五塑封层310中具有多个第五开口(未图示),第一连接键240的第一端表面、无源器件220的第三表面以及功能面211均对应有第五开口;采用电镀工艺或者溅射工艺在所述第五开口中形成第三连接键320。 [0140] Specifically, a first end of the molding surface of the first layer 230 and the first linkage 240, the third surface 220 of the passive components, the fifth surface 211 and a functional plastic layer 310 is formed, the fifth plastic layer 310 having a fifth plurality of openings (not shown), a first end surface of the first linkage 240, passive components 220, and a third surface function corresponding to a fifth surface 211 are opening; electroplating process or sputtering a third linkage 320 is formed in the fifth opening.

[0141]在其它实施例中,将第三连接键分别固定于第一连接键的第一端表面、无源器件的第三表面、以及功能面;之后,在所述第一塑封层的表面、功能面和无源器件的第三表面形成包围所述第三连接键的第五塑封层,所述第五塑封层暴露出第三连接键的表面。 A first end surface [0141] In other embodiments, the third connection are respectively fixed to the first bond linkages, passive components of the third surface, and the functional surface; after the surface of the first plastic layer third surface functional surfaces and passive devices formed plastic layer surrounding the fifth linkages third, fifth plastic layer to expose the surface of the third linkages.

[0142] 参考图10,在所述第五塑封层310和第三连接键320的表面形成第六塑封层330和贯穿所述第六塑封层330的第二焊盘340,所述第二焊盘340通过多个第三连接键320分别与第一连接键240的第一端表面以及功能面连接。 [0142] Referring to FIG 10, and 330 are formed through the sixth layer of the second plastic molding sixth pad 340 on the surface of the layer 330 is a fifth plastic layer 310 and the third linkage 320, the second solder plate 340 are respectively connected to a first end of a first linkage 240 and the surface of the functional surface 320 by a plurality of third linkages.

[0143]所述功能区的表面连接有第三连接键320,所述第二焊盘340通过功能区表面的第三连接键320与功能区连接。 [0143] The surface of the functional region is connected to the third linkage 320, the second pad 340 is connected by a third key function region 320 is connected to the surface of the ribbon.

[0144]所述第二焊盘340的材料参照第一焊盘300的材料。 [0144] The second pad 340 of the pad 300 of material of the first reference.

[0145]本实施例中,所述第二焊盘340还与无源器件220的第三表面的第三连接键320连接。 [0145] In this embodiment, the second pad 340 is also connected to the third linkage 220 third surface 320 of passive components.

[0146]具体的,在所述第五塑封层310和第三连接键320的表面形成第六塑封层330,所述第六塑封层330中具有多个第六开口(未图示),所述第六开口暴露出所述第三连接键320;采用电镀工艺或者溅射工艺在所述第六开口中形成第二焊盘340。 [0146] Specifically, the plastic layer 330 is formed on the sixth surface of the plastic layer 310 and the third fifth linkage 320, the sixth layer 330 having a plurality of plastic sixth opening (not shown), the said sixth opening exposing the third linkage 320; plating process or a sputtering process using a second pad 340 is formed in the sixth opening.

[0147]在其它实施例中,将第二焊盘固定于第三连接键和第五塑封层表面;之后,在所述第五塑封层表面形成包围所述第二焊盘的第六塑封层,所述第六塑封层暴露出第二焊盘的表面。 [0147] In other embodiments, the second pad is fixed to the third and fifth linkages plastic surface layer; after forming a sixth plastic layer surrounding the second pad in said fifth surface plastic layer the sixth layer is exposed plastic surface of the second pad.

[0148] 其中,所述第一塑封层230、第二塑封层250、第三塑封层270、第四塑封层290、第五塑封层310和第六塑封层330构成塑封结构;第一连接键240、中间连接键260和第二连接键280构成连接键结构。 [0148] wherein said first plastic layer 230, a second plastic layer 250, the third plastic layer 270, a fourth plastic layer 290, fifth layer 310, and a sixth plastic plastic plastic layer 330 constituting the structure; a first linkage 240, the intermediate linkage and the second linkage 260 280. linkage structure.

[0149]所述塑封结构、连接键结构、第一焊盘300,第三连接键320和第二焊盘340构成基板核心层。 [0149] The plastic structure, the structure of linkages, the first pad 300, the third linkage 320 and the second pad 340 of the substrate constituting the core layer.

[0150]所述基板核心层具有相对的第一表面和第二表面。 The [0150] core layer of the substrate having a first surface and a second opposing surface.

[0151]所述第二表面对应暴露出的第四塑封层的表面和第一焊盘300的第二焊面。 [0151] The second surface corresponding to the exposed surface of the plastic layer and the first pad of the fourth surface 300 of the second solder.

[0152]参考图11,在所述基板核心层的第二表面固定第二芯片350,所述第二芯片350和第一芯片210位于连接键结构的同一侧。 [0152] Referring to FIG 11, a second core layer surface of the substrate 350 is fixed a second chip, the second chip 350 and the first chip 210 on the same side of the linkage structure.

[0153]所述第二芯片350能够为传感器芯片、逻辑电路芯片、存储芯片等。 [0153] The second chip 350 can be a sensor chip, logic chip, memory chips.

[0154]所述第二芯片350通过主粘结剂(未图示)固定在第二表面。 [0154] The second chip 350 through the main adhesive (not shown) fixed to the second surface. 所述主粘结剂的材料参照所述粘结剂的材料,不再详述。 The primary material the binder material of the binder reference, not described in detail.

[0155]由于第二连接键280与第一芯片210的距离大于第一连接键240与第一芯片210的距离,且第二芯片350和第一芯片210位于连接键结构的同一侧,因此使得第二连接键280与第二芯片350的距离大于第一连接键240与第二芯片400的距离。 [0155] Since the distance between the second linkage 280 to the first chip 210 is greater than the first distance 240 and the linkage 210 of the first chip and the second chip 350 and the chip 210 on the same side of the first linkage structure, so that from the second linkage 280 and the second chip 350 is greater than the first distance 240 and the linkage 400 of the second chip.

[0156]继续参考图11,采用打线工艺形成键合金属线360,所述键合金属线360的一端与第一焊盘300连接,所述键合金属线360的另一端与第二芯片350连接。 [0156] With continued reference to FIG. 11, using wire bonding process for forming a metal line 360, the bonding metal wire 300 connected to one end of the first pad 360, the other end of said bond wire bonded metal chip 360 and the second 350 connection.

[0157]所述键合金属线360的材料为金属,如铜、钨、铝、金或银。 [0157] The bonding metal wire material 360 is a metal, such as copper, tungsten, aluminum, gold, or silver.

[0158]本实施例中,所述键合金属线360的一端连接第二焊面,所述键合金属线360的一端通过第一焊盘300与第二连接键280电学连接。 [0158] In this embodiment, the bond end of the metal wire 360 ​​connected to the second weld surface, the bond end of the metal wire 360 ​​is connected by a first pad 300 and second linkage 280 electrically. 所述第二芯片350表面具有引线端,所述键合金属线360的另一端与所述引线端连接。 Said second surface having a lead end chip 350, the bonding metal wires 360 connected to the other end of said pin.

[0159]本实施例中,所述打线工艺要求键合金属线360具有一定的弧度,因此需要第一焊盘300表面的打线点与第二芯片350表面的打线点之间的距离不能过小,若第一焊盘300表面的打线点与第二芯片350表面的打线点之间的距离过小,则导致打线工艺不能正常进行,使得封装结构的可靠性降低。 The distance between the point of the wire [0159] In this embodiment, the wire bonding process requires a metal wire 360 ​​having a certain curvature, it is necessary wire pad point 300 and the surface of the first surface of the second chip 350 can not be too small, if the distance between the wire-line dot dot playing surface of the first pad 300 and the surface of the second chip 350 is too small, the lead wire can not be normal process, so that the reliability of the package structure is reduced.

[0160]当第二芯片350投影在第二表面的面积大于第一芯片210投影在第二表面的面积时,若连接键结构靠近第二表面的一端与第二芯片350的距离等于连接键结构远离第二表面的一端与第二芯片350的距离,导致连接键结构靠近第二表面的一端与第二芯片350的距离过小,不能为键合金属线360提供足够的空间,影响键合金属线360的形成。 [0160] When the second chip 350 projected area of ​​the second surface of the first projection 210 is greater than the area of ​​the second surface of the chip, if the linkage structure from the near end of the second surface of the second chip structure 350 is equal to the linkages One end of the second distance away from the second surface of the chip 350, resulting in close linkage structure from the end of the second surface of the second chip 350 is too small to provide enough space for bonding a metal wire 360, bonding metal Effect line 360 ​​is formed.

[0161]本实施例中,由于第二连接键280与第二芯片350的距离大于第一连接键240与第二芯片350的距离,使得第二连接键280与第二芯片350的距离较大,为形成键合金属360线提供了足够的空间,使得打线工艺能够正常进行,从而提高了封装结构的可靠性。 [0161] In this embodiment, since the distance between the second linkage 280 and the second chip 350 is greater than the first distance 240 and the linkage 350 of the second chip, such that the distance between the second linkage 280 and the second chip 350 is large provides sufficient space to form a bonding metal wire 360, so that the wire bonding process can be properly performed, thereby improving the reliability of the packaging structure.

[0162]参考图12,形成覆盖所述第二芯片350、键合金属线360和第二表面的保护层370。 [0162] Referring to FIG 12, is formed covering the second chip 350, bonding layer 370, the protective surface 360 ​​and the second metal line.

[0163] 所述保护层370覆盖第一焊盘300和第四塑封层290。 [0163] The protective layer 370 covers the first pad 300 and the fourth layer 290 is plastic.

[0164]所述保护层370的材料为绝缘材料,所述绝缘材料为有机绝缘材料或无机绝缘材料。 Materials [0164] The protective layer 370 is an insulating material, the insulating material is an organic insulating material or inorganic insulating material.

[0165]在一实施例中,所述保护层370的材料为有机绝缘材料时,所述有机绝缘材料包括聚氯乙烯或树脂;所述树脂包括环氧树脂、聚酰亚胺树脂、苯并环丁烯树脂或聚苯并恶唑树月旨。 The material [0165] In one embodiment, the protective insulating layer 370 is an organic material, the organic insulating material or a resin include polyvinyl chloride; the resin comprises an epoxy resin, a polyimide resin, a coumarone cyclobutene resin or polybenzoxazole purpose tree months. 相应的,所述保护层370的形成工艺能够为喷涂工艺或注塑工艺。 Accordingly, the process of forming the protective layer 370 is capable of spraying process or an injection molding process.

[0166]在另一实施例中,所述保护层370的材料为无机绝缘材料,所述无机绝缘材料包括氧化硅、氮化硅和氮氧化硅中的一种或多种。 [0166] In another embodiment, the material is an inorganic insulating material of the protective layer 370, the inorganic insulating material comprises one or more of silicon oxide, silicon nitride and silicon oxide. 相应的,所述保护层370的形成工艺能够化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺。 Accordingly, the protective layer forming process 370 can be a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process.

[0167]参考图13,形成保护层370后,在所述第二焊盘340表面形成焊球380。 After [0167] Referring to FIG 13, a protective layer 370, solder balls 380 are formed on the surface of the second pad 340.

[0168] 所述焊球380的材料包括锡。 Materials [0168] The solder balls 380 comprises tin.

[0169]本实施例中,所述焊球380的形成步骤包括:在所述第二焊盘340的表面印刷锡膏;对所述锡膏进行高温回流,在表面张力作用下,形成焊球380。 [0169] In this embodiment, the step of forming the solder balls 380 comprises: the second pad 340 in the surface of the printed solder paste; the paste for high temperature reflow, surface tension in the form of solder balls 380. 在另一实施例中,还能够先在第二焊盘的表面印刷助焊剂和焊球颗粒,再高温回流形成焊球。 In another embodiment, the solder balls can also be formed in the first surface of the second pad printing flux and solder particles, and then at reflux temperature. 在又一实施例中,在所述第二焊盘的表面电镀锡柱,再高温回流形成焊球。 In yet another embodiment, the tin plating on the surface of the second pad column, and then high-temperature reflow solder balls are formed.

[0170] 在所述第二焊盘340与所述焊球380之间,还能形成有球下金属结构(Under BallMetal,简称UBM)。 [0170] between the second pad 340 and the ball 380, can form the metal structure (Under BallMetal, referred to as UBM) next have the ball. 所述球下金属结构能够包括单层金属层或多层重叠的金属层;所述单层金属层或多层金属层的材料包括铜、铝、镍、钴、钛、钽中的一种或多种组合。 The metal structure can comprise a single layer of metal balls lower layer or multi-layer overlapping metal; a single metal layer or multiple metal layers of materials include copper, aluminum, nickel, cobalt, titanium, tantalum, one or a variety of combinations.

[0171]虽然本发明披露如上,但本发明并非限定于此。 [0171] Although the present invention is disclosed as above, but the present invention is not limited thereto. 任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。 Anyone skilled in the art, without departing from the spirit and scope of the present invention, various changes or modifications may be made, and therefore the scope of the present invention reference should be made to the scope defined by the claims.

Claims (14)

  1. 1.一种封装结构,其特征在于,包括: 第一芯片,第一芯片具有功能面; 基板核心层,所述基板核心层具有相对的第一表面和第二表面,基板核心层包括:塑封结构和位于塑封结构内的连接键结构; 所述塑封层包围所述第一芯片,且所述第一芯片的功能面朝向所述第一表面设置; 所述连接键结构包括电学连接的第一连接键和第二连接键,第二连接键到第一表面的距离大于第一连接键到第一表面的距离,所述第二连接键到第一芯片的距离大于第一连接键到第一芯片的距离,所述第一连接键与所述功能面电学连接; 第二芯片,位于第二表面,所述第二芯片和第一芯片位于连接键结构的同一侧; 键合金属线,所述键合金属线的一端与第二连接键电学连接,键合金属线的另一端与第二芯片电学连接。 A package structure comprising: a first chip having a first chip surface function; core layer of the substrate, the substrate core layer having opposing first and second surfaces, the core layer substrate comprising: Plastic linkage structure positioned within the plastic structure and the structure; the first plastic layer surrounding the chip, the first chip and the functional surface disposed toward the first surface; the key structure comprises a first connector electrically connected linkage and a second linkage, linkage to a second distance greater than the distance of the first surface of the first surface of the first linkage to said second linkage to the first distance is greater than the first chip to the first linkage from the chip, the first linkage connected to the electrically functional surface; a second chip located on a second surface, said first chip and the second chip located on the same side of the linkage structure; bonding metal wires, the said bonding end of the metal wire electrically connected to the second linkage, the other bonding metal wire chip is electrically connected to the second end.
  2. 2.根据权利要求1所述的封装结构,其特征在于,所述连接键结构还包括中间连接键,第一连接键和第二连接键通过中间连接键电学连接。 2. The package structure according to claim 1, wherein said structure further includes an intermediate linkage linkages, the first linkage and the second linkage is connected electrically through an intermediate linkage.
  3. 3.根据权利要求2所述的封装结构,其特征在于,第一连接键、第二连接键和中间连接键的材料为铜、妈、招、金或银。 3. The package structure according to claim 2, characterized in that the first linkage, second linkage and the intermediate linkage connecting material is copper, mother, strokes, gold or silver.
  4. 4.根据权利要求2所述的封装结构,其特征在于,所述中间连接键具有相对的第一连接端和第二连接端,第一连接端到第一芯片的距离小于第二连接端到第一芯片的距离,第一连接端与第一连接键连接,第二连接端与第二连接键连接。 4. The package structure according to claim 2, wherein said intermediate linkage having a first connection end and an opposite second end connected to a first end connected to a second distance less than the first chip connection end from the first chip, a first connection terminal connected to the first linkage, the second connecting terminal connected to the second linkage.
  5. 5.根据权利要求1所述的封装结构,其特征在于,所述第二芯片的表面具有引线端;所述键合金属线的另一端与所述引线端连接。 5. The package structure according to claim 1, characterized in that the surface of the second chip having a lead end; the other end of the bonding metal wire connected to said pin connector.
  6. 6.根据权利要求1所述的封装结构,其特征在于,所述键合金属线的材料为铜、钨、铝、金或银。 6. The package structure according to claim 1, wherein said bonding material of the metal wire is made of copper, tungsten, aluminum, gold, or silver.
  7. 7.根据权利要求1所述的封装结构,其特征在于,所述基板核心层还包括: 第一焊盘,所述第一焊盘具有相对的第一焊面和第二焊面,第一焊面与第二连接键连接,第二焊面与键合金属线连接。 7. The package structure according to claim 1, wherein the core layer substrate further comprises: a first pad, the pad having a first surface opposite to a first weld and the second weld surface, the first welding surface and the second linkage is connected to the second bonding surface and the bonding wires connected to the metal.
  8. 8.根据权利要求1所述的封装结构,其特征在于,所述第一连接键包括相对的第一端和第二端,第一端朝向第一表面设置,第二端与第二连接键电学连接。 8. The package structure according to claim 1, wherein said first linkage includes opposing first and second ends, a first surface disposed toward the first end, a second end and a second linkage electrically connected.
  9. 9.根据权利要求8所述的封装结构,其特征在于,所述基板核心层还包括: 第二焊盘和多个第三连接键,所述第二焊盘通过多个第三连接键分别与第一连接键的第一端表面以及功能面连接。 9. The package structure according to claim 8, wherein the core layer substrate further comprises: a second plurality of pads and the third linkages, the plurality of second pads by a third linkages respectively a first end connected to the first surface of the functional surface and linkages.
  10. 10.根据权利要求9所述的封装结构,其特征在于,所述功能面包括功能区, 所述功能区的表面连接有第三连接键,所述第二焊盘通过功能区表面的第三连接键与功能区连接。 10. The third package structure according to claim 9, characterized in that said ribbon comprises a functional surface, the functional surface region is connected to a third linkage, the second pad region through surface functional linkage connected to the functional region.
  11. 11.根据权利要求9所述的封装结构,其特征在于,还包括:焊球,位于第二焊盘表面。 11. The package structure according to claim 9, characterized in that, further comprising: a solder ball pads located on a second surface.
  12. 12.根据权利要求1所述的封装结构,其特征在于,还包括:保护层,所述保护层覆盖所述第二芯片、键合金属线和第二表面。 12. The package structure according to claim 1, characterized in that, further comprising: a protective layer, the second protective layer covers the chip, the bonding wire and the second surface.
  13. 13.根据权利要求1所述的封装结构,其特征在于,还包括:主粘结层,位于第二芯片和第二表面之间。 13. A package according to claim 1, characterized in that, further comprising: a primary adhesive layer disposed between the second chip and a second surface.
  14. 14.根据权利要求1所述的封装结构,其特征在于,还包括:无源器件,嵌在塑封结构中,所述无源器件与第一连接键电学连接;所述第一连接键位于所述无源器件和第一芯片之间。 14. A package according to claim 1, characterized in that, further comprising: a passive device, embedded in the plastic structure, the passive component electrically connected to the first linkage; the first linkage being positioned between said first chip and passive devices.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080272464A1 (en) * 2007-05-04 2008-11-06 Stats Chippac, Ltd. Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer
CN101814474A (en) * 2009-02-20 2010-08-25 联发科技股份有限公司 Wire bond chip package
US20110304015A1 (en) * 2010-06-10 2011-12-15 Samsung Electronics Co., Ltd. Semiconductor package
KR101237587B1 (en) * 2011-08-08 2013-02-26 앰코 테크놀로지 코리아 주식회사 Semiconductor package and fabricating method thereof
KR101238213B1 (en) * 2011-01-31 2013-03-04 하나 마이크론(주) Stack semiconductor package and method of manufacturing the same
CN104538375A (en) * 2014-12-30 2015-04-22 华天科技(西安)有限公司 Fan-out PoP packaging structure and manufacturing method thereof
CN104733463A (en) * 2013-12-18 2015-06-24 瑞萨电子株式会社 Semiconductor device
CN105428334A (en) * 2014-09-15 2016-03-23 联发科技股份有限公司 Semiconductor package assembly

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080272464A1 (en) * 2007-05-04 2008-11-06 Stats Chippac, Ltd. Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer
CN101814474A (en) * 2009-02-20 2010-08-25 联发科技股份有限公司 Wire bond chip package
US20110304015A1 (en) * 2010-06-10 2011-12-15 Samsung Electronics Co., Ltd. Semiconductor package
KR101238213B1 (en) * 2011-01-31 2013-03-04 하나 마이크론(주) Stack semiconductor package and method of manufacturing the same
KR101237587B1 (en) * 2011-08-08 2013-02-26 앰코 테크놀로지 코리아 주식회사 Semiconductor package and fabricating method thereof
CN104733463A (en) * 2013-12-18 2015-06-24 瑞萨电子株式会社 Semiconductor device
CN105428334A (en) * 2014-09-15 2016-03-23 联发科技股份有限公司 Semiconductor package assembly
CN104538375A (en) * 2014-12-30 2015-04-22 华天科技(西安)有限公司 Fan-out PoP packaging structure and manufacturing method thereof

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