CN105047672A - Pixel array substrate, display panel and mother board thereof - Google Patents
Pixel array substrate, display panel and mother board thereof Download PDFInfo
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- CN105047672A CN105047672A CN201510446804.9A CN201510446804A CN105047672A CN 105047672 A CN105047672 A CN 105047672A CN 201510446804 A CN201510446804 A CN 201510446804A CN 105047672 A CN105047672 A CN 105047672A
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- 239000000758 substrate Substances 0.000 title claims abstract description 219
- 239000011241 protective layer Substances 0.000 claims abstract description 132
- 239000010410 layer Substances 0.000 claims abstract description 108
- 239000010409 thin film Substances 0.000 claims abstract description 61
- 230000004888 barrier function Effects 0.000 claims description 141
- 239000000463 material Substances 0.000 claims description 47
- 239000004065 semiconductor Substances 0.000 claims description 32
- 208000034699 Vitreous floaters Diseases 0.000 claims description 25
- 238000000926 separation method Methods 0.000 claims description 22
- 239000003292 glue Substances 0.000 claims description 21
- 239000012212 insulator Substances 0.000 claims description 12
- 238000004891 communication Methods 0.000 claims description 4
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims 2
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 230000000875 corresponding effect Effects 0.000 description 49
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 229910052757 nitrogen Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 125000004430 oxygen atom Chemical group O* 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910005949 NiCo2O4 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- QTZWZWHIGHUPPD-UHFFFAOYSA-N [Ge]=O.[O-2].[Cd+2] Chemical compound [Ge]=O.[O-2].[Cd+2] QTZWZWHIGHUPPD-UHFFFAOYSA-N 0.000 description 1
- KSHLPUIIJIOBOQ-UHFFFAOYSA-N [O--].[O--].[O--].[O--].[Co++].[Ni++] Chemical compound [O--].[O--].[O--].[O--].[Co++].[Ni++] KSHLPUIIJIOBOQ-UHFFFAOYSA-N 0.000 description 1
- JYMITAMFTJDTAE-UHFFFAOYSA-N aluminum zinc oxygen(2-) Chemical compound [O-2].[Al+3].[Zn+2] JYMITAMFTJDTAE-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The embodiment of the invention discloses a pixel array substrate, a display panel and a motherboard thereof. The substrate has a display area and at least one peripheral circuit area. The thin film transistor is arranged on the substrate and positioned in the display area, and the thin film transistor is provided with an insulating layer extending to the peripheral circuit area. The first signal line, the second signal line and the pixel electrode are arranged on the substrate, are positioned in the display area and are connected with the thin film transistor. The first conductive pattern is arranged in the peripheral circuit area and adjacent to the edge of the substrate, and is overlapped with the insulating layer to form a mark. The thin film transistor, the mark and the insulating layer on the peripheral circuit area are covered by a first protective layer, wherein the dielectric constant of the first protective layer is larger than that of the insulating layer. The technical scheme of the embodiment of the invention reduces the probability of deterioration of the internal circuit caused by water vapor.
Description
Technical field
The present invention relates to technical field of display panel, particularly relate to a kind of image element array substrates of applied film transistor technology, display floater and motherboard thereof.
Background technology
Be widely used in the field of display floater with the image element array substrates that thin-film transistor technique makes.Because integrated circuit can be implemented on glass substrate by thin-film transistor, therefore can be used for producing the display floater of high degree of integration.
But the display floater made by thin-film transistor technologies, after long-time use, often has the phenomenon of colour cast in edge.Trace it to its cause, because the steam in environment enters image element array substrates from the image element array substrates edge of display floater, make the oxide semiconductor in the thin-film transistor of part absorb steam and make deterioration in characteristics.Therefore, how stoping steam to enter image element array substrates to improve the life-span of the display floater produced, is a problem demanding prompt solution.
Summary of the invention
Because above problem, the present invention proposes a kind of image element array substrates, display floater and motherboard design thereof, makes the probability of internal circuit deterioration in order to reduce steam.
Image element array substrates disclosed in this invention, has substrate, thin-film transistor, the first holding wire, secondary signal line, pixel electrode, the first conductive pattern and the first protective layer.Substrate has viewing area and at least one perimeter circuit district, and viewing area has multiple pixel region.Thin-film transistor to be arranged on substrate and to be positioned on pixel region at least partially, thin-film transistor has grid, source electrode, drain electrode, insulating barrier and oxide semiconductor layer, wherein, insulating barrier is between grid and oxide semiconductor layer, and source/drain contacts with oxide semiconductor layer, and insulating barrier extends to perimeter circuit district.First holding wire, to be arranged on substrate and to be positioned in partial pixel district, and connecting grid.Secondary signal line to be arranged on substrate and to be positioned in partial pixel district, and connects source electrode.Pixel electrode to be arranged on substrate and to be positioned in partial pixel district, and connects drain electrode.First conductive pattern is arranged at the edge of perimeter circuit district and adjacent substrates, wherein, the insulating barrier and the first conductive pattern ply that are positioned at perimeter circuit district mark to form, insulating barrier has the first opening, expose the inner surface of substrate, and the first opening to be positioned in perimeter circuit district and around viewing area, and avoid mark.First protective layer is formed on substrate; and be formed at thin-film transistor, mark, be positioned on insulating barrier in perimeter circuit district and the first opening; wherein the dielectric constant of the first protective layer is greater than the dielectric constant of insulating barrier, and the dielectric constant of insulating barrier is less than 6, is greater than 1.
In an embodiment, also comprising one second conductive pattern layer is arranged in described multiple perimeter circuit district, wherein, this second conductive pattern layer and this first conductive pattern ply, and this insulating barrier, this first conductive pattern layer and this second conductive pattern ply that are positioned in this perimeter circuit district are to form this mark.
In an embodiment, this insulating barrier is in the markers located between this first conductive pattern layer and this second conductive pattern layer.
In an embodiment; also comprise one second protective layer; be formed on this substrate; and be formed at this thin-film transistor, this mark and be positioned on this insulating barrier in this perimeter circuit district; wherein; this second protective layer is located between this insulating barrier and this first protective layer; this second protective layer has one second opening and corresponds to this first opening; to expose the inner surface of this substrate, and this first protective layer is formed on this thin-film transistor, this mark, this insulating barrier be positioned in this perimeter circuit district, this second protective layer, this first opening and this second opening.
In an embodiment, the dielectric constant of this first protective layer is greater than the dielectric constant of this second protective layer, and the dielectric constant of this second protective layer and the dielectric constant of this insulating barrier are less than 6, are greater than 1.
In an embodiment, also comprise a dielectric layer, be formed on this substrate, and be formed at this thin-film transistor, this mark is with on this insulating barrier be positioned in this perimeter circuit district, wherein, this dielectric layer is located between this second protective layer and this first protective layer, this second protective layer has one the 3rd opening and corresponds to this second opening, to expose the inner surface of this substrate, and this first protective layer forms this thin-film transistor, this mark, be positioned at this insulating barrier in this perimeter circuit district, this second protective layer, this first opening, on this second opening and the 3rd opening.
In an embodiment, this dielectric layer has one the 4th opening, is positioned at the top of this mark, and this first protective layer is formed on the 4th opening, and the 4th opening not with this first opening, this second opening and the 3rd open communication.
In an embodiment, the dielectric constant of this insulating barrier is less than 5, is greater than 1.
In an embodiment, this mark is positioned at four corners of this substrate, this first opening has two Part I and a Part II, respectively this Part I exposes this substrate edges and itself and this substrate edges has the distance being greater than 0, this Part II is communicated with respectively this Part I respectively, and it is not this mark contiguous, but overlapping with this substrate edges.
In an embodiment, this mark is not positioned at four corners in this precut district, this first opening has two Part I and a Part II, respectively this Part I exposes this substrate edges and itself and this substrate edges has the distance being greater than 0, this Part II is communicated with respectively this Part I respectively, and it is not this mark contiguous, but overlapping with this substrate edges.
In an embodiment, what this insulating barrier comprised a gate insulator or this gate insulator and an etch stop layer stacks rete.
A kind of display floater disclosed in this invention, comprises:
As above arbitrary described a kind of image element array substrates;
One subtend substrate;
One frame glue, is arranged between this image element array substrates and this subtend substrate, and wherein, this frame glue is around this viewing area to form a space, and this frame glue is between this first opening and this viewing area; And
One display dielectric layer, is formed in this space.
In an embodiment, also comprise at least one smooth separation material and be arranged between this subtend substrate and this image element array substrates, and corresponding to this first opening and this substrate edges, there is the place of the distance being greater than 0.
Motherboard disclosed in this invention, has substrate, thin-film transistor, the first holding wire, secondary signal line, pixel electrode, the first conductive pattern and the first protective layer.Substrate has multiple display unit, defines precut district between display unit, and each display unit comprises viewing area and perimeter circuit district, and wherein viewing area has multiple pixel region.Thin-film transistor to be arranged on substrate and to be positioned on pixel region at least partially, thin-film transistor has grid, source electrode, drain electrode, insulating barrier and oxide semiconductor layer, wherein, insulating barrier is between grid and oxide semiconductor layer, and source/drain contacts with oxide semiconductor layer, and insulating barrier extends in the perimeter circuit district of each display unit.First holding wire to be arranged on substrate and to be positioned at least partially on pixel region, and connects grid.Secondary signal line to be arranged on substrate and to be positioned at least partially on pixel region, and connects source electrode.Pixel electrode to be arranged on substrate and to be positioned at least partially on pixel region, and connects drain electrode.First conductive pattern is arranged in the precut district of a part, and a part of first conductive pattern is arranged in perimeter circuit district, wherein, be positioned at that insulating barrier in perimeter circuit district is overlapping with the first conductive pattern to be marked to form, insulating barrier has the first opening, expose the inner surface of substrate, and the first opening to be positioned in perimeter circuit district and around viewing area, and to avoid mark.First protective layer is formed on substrate; and be formed at thin-film transistor, mark, be positioned on insulating barrier in perimeter circuit district and the first opening, wherein, the dielectric constant of the first protective layer is greater than the dielectric constant of insulating barrier; and the dielectric constant of insulating barrier is less than 6, is greater than 1.
In an embodiment, also comprising one second conductive pattern layer is arranged in this precut district of a part, and this second conductive pattern layer of a part is arranged in described multiple perimeter circuit district, wherein, this second conductive pattern layer and this first conductive pattern ply, be positioned at this insulating barrier in this perimeter circuit district, this first conductive pattern layer and this second conductive pattern ply to form this mark.
In an embodiment, this insulating barrier is in the markers located between this first conductive pattern layer and this second conductive pattern layer.
In an embodiment; also comprise one second protective layer; be formed on this substrate; and be formed at this thin-film transistor, this mark and be positioned on this insulating barrier in this perimeter circuit district; wherein; this second protective layer is located between this insulating barrier and this first protective layer; this second protective layer has one second opening and corresponds to this first opening; to expose the inner surface of this substrate, and this first protective layer is formed on this thin-film transistor, this mark, this insulating barrier be positioned in this perimeter circuit district, this second protective layer, this first opening and this second opening.
In an embodiment, the dielectric constant of this first protective layer is greater than the dielectric constant of this second protective layer, and the dielectric constant of this second protective layer and the dielectric constant of this insulating barrier are less than 6, are greater than 1.
In an embodiment, also comprise a dielectric layer, be formed on this substrate, and be formed at this thin-film transistor, this mark is with on this insulating barrier be positioned in this perimeter circuit district, wherein, this dielectric layer is located between this second protective layer and this first protective layer, this second protective layer has one the 3rd opening and corresponds to this second opening, to expose the inner surface of this substrate, and this first protective layer forms this thin-film transistor, this mark, be positioned at this insulating barrier in this perimeter circuit district, this second protective layer, this first opening, on this second opening and the 3rd opening.
In an embodiment, this dielectric layer has one the 4th opening, is positioned at the top of this mark, and this first protective layer is formed on the 4th opening, and the 4th opening not with this first opening, this second opening and the 3rd open communication.
In an embodiment, the dielectric constant of this insulating barrier is less than 5, is greater than 1.
In an embodiment, this mark is positioned at four corners in this precut district, and this first opening has two Part I and a Part II, respectively this Part I and this precut area overlapping, this Part II is communicated with respectively this Part I respectively, and this mark contiguous, but not precut area overlapping with this.
In an embodiment, this mark is not positioned at four corners in this precut district, this first opening has two Part I and a Part II, respectively this Part I and this precut area overlapping, this Part II is communicated with respectively this Part I respectively, and this mark contiguous, but not precut area overlapping with this.
In an embodiment, what this insulating barrier comprised a gate insulator or this gate insulator and an etch stop layer stacks rete.
Display floater motherboard disclosed in this invention comprises:
As above arbitrary described a kind of motherboard;
One subtend substrate;
One frame glue, is arranged between this substrate of respectively this display unit and this subtend substrate, and wherein, this frame glue is around this viewing area of each this display unit to form a space, and this frame glue is between this first opening and this viewing area of each this display unit; And
One display dielectric layer, is formed in this space.
In an embodiment, also comprise at least one smooth separation material and be arranged between this subtend substrate and this substrate, and correspond to this precut district.
In sum; image element array substrates disclosed in this invention and motherboard thereof; because the water-resisting ability of the lower material (such as insulating barrier) of dielectric constant is limited; and the material that dielectric constant is higher (the first protective layer) is suitable for isolated external environment aqueous vapor; and coordinate the relevant design of opening; therefore be not easy to absorb steam in the process of processing and in the process used, thus improve yield and the life-span of image element array substrates and motherboard thereof.
The above explanation about content of the present invention and the explanation of following execution mode are in order to demonstration and explanation spirit of the present invention and principle, and provide patent claim of the present invention further to explain.
Accompanying drawing explanation
Fig. 1 is the image element array substrates motherboard vertical view according to one embodiment of the invention.
Fig. 2 A is the partial cutaway schematic view corresponding to cutting line AA ' in Fig. 1.
Fig. 2 B figure is the partial cutaway schematic view corresponding to cutting line BB ' and DD ' in Fig. 1.
Fig. 2 C figure is the partial cutaway schematic view corresponding to cutting line CC ' in Fig. 1.
Fig. 3 is the motherboard vertical view according to another embodiment of the present invention.
Fig. 4 is the partial cutaway schematic view of the cutting line CC ' according to Fig. 1 in another embodiment of the present invention.
Fig. 5 A is the partial cutaway schematic view corresponding to cutting line AA ' according to the motherboard in yet another embodiment of the invention.
Fig. 5 B is the partial cutaway schematic view corresponding to cutting line BB ' according to the motherboard in yet another embodiment of the invention.
Fig. 5 C is the partial cutaway schematic view corresponding to cutting line CC ' according to the motherboard in yet another embodiment of the invention.
Fig. 6 is the partial cutaway schematic view corresponding to cutting line CC ' according to the motherboard in another embodiment of the present invention.
Fig. 7 is the partial cutaway schematic view of the panel motherboard according to another embodiment of the present invention.
Fig. 8 is that the motherboard corresponded in Fig. 1 is split the image element array substrates vertical view obtained.
Fig. 9 A is the partial cutaway schematic view corresponding to cutting line aa ' in Fig. 8.
Fig. 9 B is the partial cutaway schematic view corresponding to cutting line bb ' in Fig. 8.
Fig. 9 C is the partial cutaway schematic view corresponding to cutting line cc ' in Fig. 8.
Fig. 9 D is the partial cutaway schematic view corresponding to cutting line dd ' in Fig. 8.
Figure 10 is the image element array substrates vertical view according to another embodiment of the present invention.
Figure 11 is the partial cutaway schematic view of the cutting line cc ' according to Fig. 8 in another embodiment of the present invention.
Figure 12 A is the partial cutaway schematic view corresponding to cutting line aa ' according to the image element array substrates in yet another embodiment of the invention.
Figure 12 B is the partial cutaway schematic view corresponding to cutting line bb ' according to the image element array substrates in yet another embodiment of the invention.
Figure 12 C is the partial cutaway schematic view corresponding to cutting line cc ' according to the image element array substrates in yet another embodiment of the invention.
Figure 12 D is the partial cutaway schematic view corresponding to cutting line dd ' according to the image element array substrates in yet another embodiment of the invention.
Figure 13 is the partial cutaway schematic view corresponding to cutting line cc ' according to the image element array substrates in another embodiment of the present invention.
Figure 14 is the generalized section of the display floater according to another embodiment of the present invention.
Wherein, description of reference numerals is as follows:
1000 motherboards
1100,3100 substrates
1101,3101 upper surfaces
310E edge
1110 display units
1111,3111 viewing areas
1113,3113 perimeter circuit districts
1130 precut districts
1300,3300 thin-film transistors
130G, 330G grid
130S, 330S source electrode
130D, 330D drain
130I, 330I insulating barrier
1400,1500,3400,3500 holding wires
1600,3600 pixel electrodes
1700,1710,3700,3710 conductive patterns
1800 ~ 1830,3800 ~ 3830 openings
1801,1803,1807,3801,3803,3807 Part I
1805,1809,3805,3809 Part II
380E sidewall
1900,1910,3900,3910 protective layers
1920,3920 dielectric layers
2000 panel motherboards
3000 image element array substrates
4000 display floaters
2100,4100 subtend substrates
2200,4200 frame glue
2300,4300 display dielectric layers
2400,4400 smooth separation materials
AA ', BB ', CC ', DD ' cutting line
Aa ', bb ', cc ', dd ' cutting line
Embodiment
Below detailed features of the present invention and advantage is described in embodiments in detail, its content is enough to make any relevant art of haveing the knack of understand technology contents of the present invention and implement according to this, and according to the content disclosed in this specification, claim and accompanying drawing, any those of ordinary skill in the art can understand the object and advantage that the present invention is correlated with easily.Following embodiment further describes viewpoint of the present invention, but non-to limit category of the present invention anyways.
Please refer to Fig. 1 to 2C to scheme, wherein Fig. 1 is the image element array substrates motherboard vertical view according to one embodiment of the invention, 2A figure is the partial cutaway schematic view corresponding to cutting line AA ' in Fig. 1, and 2B figure is the partial cutaway schematic view corresponding to cutting line BB ' and DD ' in Fig. 1,2C figure is the partial cutaway schematic view corresponding to cutting line CC ' in Fig. 1.And if Fig. 1,2A figure is with shown in 2B figure, the motherboard 1000 in one embodiment of the invention has substrate 1100.Substrate 1100 has multiple display unit 1110, defines at least one precut district 1130 between display unit.Each display unit 1110 comprises one and has the viewing area 1111 of multiple pixel region (sign) and at least one perimeter circuit district 1113 adjacent to viewing area 1111, embodiments of the invention are with at least one perimeter circuit district 1113 around viewing area 1113 for implementing example, but are not limited thereto.After must being noted that each display unit 1110 is cut, be exactly image element array substrates or the display floater of a display floater.
And as shown in 2A figure, at least part of pixel region (sign) in viewing area 1111, the upper surface in substrate 1100 is provided with thin-film transistor 1300.Grid 130G, drain electrode 130D, source electrode 130S, insulating barrier 130I and oxide semiconductor layer 130O is had in thin-film transistor 1300.Insulating barrier 130I is between grid 130G and oxide semiconductor layer 130O, and source electrode 130S contacts with oxide semiconductor layer 130O with drain electrode 130D, namely source electrode 130S all can partly overlap with oxide semiconductor layer 130O with drain electrode 130D, and insulating barrier 130I also extends to the perimeter circuit district 1113 of affiliated display unit 1110, wherein the dielectric constant of insulating barrier 130I is less than 6, is greater than 1.In special embodiment, the dielectric constant of insulating barrier 130I is less than 5, is greater than 1.Wherein, the material of insulating barrier 130I can be silicon dioxide, carbon Si oxide, silicon oxynitride, carborundum, silica-based macromolecule, spin-coating glass (SOG) or other suitable material, and the physical property of previous materials or voltinism can consult physical security tables of data, and the nitrogen percent of silicon oxynitride will be less than in fact 30% is greater than 0%, oxygen atom is greater than the percentage of nitrogen-atoms, atomic percent silicon is less than in fact nitrogen and oxygen atom summation, and nitrogen and oxygen atom summation are less than 67% is greater than 62%, wherein, nitrogen, oxygen, silicon atom summation is 100%, and the refractive index of silicon oxynitride is greater than 1.45 is less than 1.75, and its manufacture method can be chemical gaseous phase Shen area method, sputtering method or other suitable method.The present invention, but to be not limited thereto for silicon dioxide is for example with the material of insulating barrier 130I.In some embodiment, only have gate insulator in insulating barrier 130I, and in other embodiments, insulating barrier 130I is stacked by multi-layer insulation and forms, such as insulating barrier 130I is made up of the rete that stacks of gate insulator and etch stop layer.Although in the present embodiment, under grid 130G is positioned at oxide semiconductor layer 130O, namely lock type thin-film transistor is example at the end, is not limited thereto.In other embodiment, grid 130G is also positioned at the upper of oxide semiconductor layer 130O, and namely push up lock type thin-film transistor, or grid 130G is positioned on other position of oxide semiconductor layer 130O, namely the thin-film transistor of other type is also applicatory.Oxide semiconductor can be single or multiple lift structure, and its material comprises indium gallium zinc oxide (IGZO), indium-zinc oxide (IZO), indium gallium oxide (IGO), tin oxide (ZnO), cadmium oxide germanium oxide (CdO2.GeO2), cobalt nickel oxide (NiCo2O4), zinc oxide (ZnO), aluminium zinc oxide (AZO), gallium zinc oxide (GZO) or other suitable material.
In addition, on thin-film transistor 1300, be also provided with the first holding wire 1400, secondary signal line 1500 and pixel electrode 1600.First holding wire 1400 is connected to grid 130G, then the first holding wire 1400 can be considered scan line or gate line, secondary signal line 1500 is connected to source electrode 130S, then secondary signal line 1500 can be considered data wire, and pixel electrode 1600 is connected to drain electrode 130D.Wherein, the first holding wire 1400, secondary signal line 1500 are all with pixel electrode 1600 and describe briefly.In addition, the first conductive pattern 1700 is also had on substrate 1100, first conductive pattern 1700 is arranged at the precut district 1130 of a part, and the first conductive pattern 1700 of part is positioned at perimeter circuit district 1113, wherein, the insulating barrier 130I being arranged in perimeter circuit district 1113 is overlapping with the first conductive pattern 1700 with the mark M of pie graph 1.Insulating barrier 130I has the first opening 1800, the portion of upper surface 1101 (or can be described as inner surface) of substrate 1100 comes out via the first opening 1800, and the first opening 1800 to be positioned in perimeter circuit district 1113 and around viewing area 1111, and avoid marking M.Although in diagram in, the first conductive pattern 1700 covers insulating barrier 130I, however the first conductive pattern 1700 also can cover by insulating barrier 130I, the present invention is not limited.
Also have the first protective layer 1900, be formed on substrate 1100, and be formed at thin-film transistor 1300, mark M, be positioned on the insulating barrier 130I in perimeter circuit district 1113 and the first opening 1800.The dielectric constant of the first protective layer 1900 is greater than the dielectric constant of insulating barrier 130I.Wherein, the material of the first protective layer 1900 can be silicon nitride, silicon oxynitride, tantalum oxide (tantalumoxide), aluminium oxide, titanium oxide, hafnium oxide (HfO) or other suitable material, and the physical property of previous materials or voltinism can consult physical security tables of data, and the nitrogen percent of silicon oxynitride will be more than or equal in fact 30% is less than 58%, oxygen atom is less than the percentage of nitrogen-atoms and is greater than 0%, atomic percent silicon is less than in fact nitrogen and oxygen atom percentage summation, and nitrogen and oxygen atom percentage summation are less than or equal to 62% is greater than 57%, wherein, nitrogen, oxygen, silicon atom summation is 100%, and the refractive index of silicon oxynitride is more than or equal to 1.75 is less than 2.0, and its manufacture method can be chemical gaseous phase Shen area method, sputtering method or other suitable method.The present invention, but to be not limited thereto for silicon nitride is for example with the material of the first protective layer 1900.Therefore; as illustrated in fig. 2b; in partial cutaway schematic view corresponding to cutting line BB ' in place of precut district 1130; the first protective layer 1900 on substrate 1100 contacts in first opening 1800 place of insulating barrier 130I with substrate 1100; and the part beyond the first opening 1800, the upper surface of the first protective layer 1900 not contact substrate 1100.
And as shown in 2C figure, in the partial cutaway schematic view corresponding to the cutting line CC ' in mark M place, substrate 1100 has the first conductive pattern 1700, and the insulating barrier 130I on it.The first protective layer 1900 is coated with on insulating barrier 130I.
In some embodiment, go back to Fig. 1, mark M is positioned at four corners in the precut district 1130 around display unit 1110, then first opening 1800 at every nook and cranny place have two Part I 1801,1803 and Part II 1805, each Part I is overlapping with precut district 1130, Part II 1805 is communicated with Part I 1801 and Part I 1803 respectively, and Part II 1805 contiguous mark M, but not overlapping with precut district 1130, can be considered that Part II 1805 is not communicated with mark M.In the present embodiment, mark M can be used as contraposition and/or cut mark, and the projection of shape of mark M is to be essentially cross for example, but is not limited thereto.In other embodiment, the projection of shape of mark M can be L shape, T-shaped or other suitable projection of shape.
In another embodiment, please refer to Fig. 3, it is the motherboard vertical view according to another embodiment of the present invention.As shown in Figure 3, compared to the embodiment of Fig. 1, the mark M of the present embodiment is not positioned at four corners in precut district 1130, and the position that can be positioned at outside four corners, and the first opening 1800 has two Part I, 1801,1807 and Part II 1809, each Part I 1801,1807 is overlapping with precut district 1130, Part II 1809 is communicated with Part I 1801 and Part I 1807 respectively, and contiguous mark M, but not overlapping with precut district 1130, can be considered that Part II 1809 is not communicated with mark M.And the cross-section structure of hatching AA ', BB ', CC ', DD ' and the EE ' shown in Fig. 3 can consult Fig. 2 A ~ 2C and Fig. 4 ~ 7.Suppose that each display unit 1110 has multiple limit, then each limit can have the mark M shown at least one Fig. 3.In the present embodiment, mark M can be used as contraposition and/or cut mark, and the projection of shape of mark M is to be essentially linear for example, but is not limited thereto, and such as, the projection of shape of mark M can be curve or other suitable projection of shape.In other embodiment, in Fig. 3, also can comprise the mark M shown in Fig. 1, then all have the effect marking and can strengthen contraposition and/or cutting again in corner and non-corner.In like manner, in Fig. 1, also can comprise the mark M shown in Fig. 3, then all have the effect marking and can strengthen contraposition and/or cutting again in corner and non-corner.
In another embodiment, please refer to Fig. 4, it is the partial cutaway schematic view of the cutting line CC ' according to Fig. 1 in another embodiment of the present invention.As shown in Figure 4, in the present embodiment, in the cut-away section structure of mark M position, be with the difference of the embodiment of 2C figure, the motherboard 1000 in the present embodiment has more the second conductive pattern 1710.Second conductive pattern 1710 is arranged at the precut district 1130 of part, and part second conductive pattern 1710 is positioned at perimeter circuit district 1113.Second conductive pattern 1710 is overlapping with the first conductive pattern 1700, and mark M be by the insulating barrier 130I being positioned at perimeter circuit district 1113, the first conductive pattern 1700 is overlapping with the second conductive pattern 1710 and form.And mark in the part of M, insulating barrier 130I is located between the first conductive pattern 1700 and the second conductive pattern 1710.
In an embodiment again, please refer to 5A figure to 5C to scheme, wherein 5A figure is the partial cutaway schematic view corresponding to cutting line AA ' according to the motherboard in yet another embodiment of the invention, and 5B figure is the partial cutaway schematic view corresponding to cutting line BB ' according to the motherboard in yet another embodiment of the invention, 5C figure is the partial cutaway schematic view corresponding to cutting line CC ' according to the motherboard in yet another embodiment of the invention.As 5A figure, 5B figure is with shown in 5C figure, the embodiment of motherboard 1000 compared to 2A figure to 2C figure in the present embodiment, have more the second protective layer 1910, second protective layer 1910 is formed at the upper of substrate 1100, and be formed at thin-film transistor 1300, mark M and be positioned on the insulating barrier 130I in perimeter circuit district 1113, wherein, second protective layer 1910 is located between insulating barrier 130I and the first protective layer 1900, this second protective layer 1910 has the second opening 1810 corresponding to the first opening 1800, (inner surface is can be described as with the portion of upper surface 1101 exposing substrate 1100, because the remainder of the upper surface 1101 of substrate 1100 cover by each material layer and do not expose), and the first protective layer 1900 is formed at thin-film transistor 1300, mark M, be positioned at the insulating barrier 130I in perimeter circuit district 1113, second protective layer 1910, on first opening 1800 and the second opening 1810.In addition, the dielectric constant of the first protective layer 1900 can be greater than the dielectric constant of the second protective layer 1910.For example, the dielectric constant of the second protective layer 1910 is optionally less than 6 and is greater than 1, and the second protective layer 1910 is optional from the material described in insulating barrier 130I or other suitable material.
In addition, same reference 5A figure to 5C schemes, and the motherboard 1000 in some embodiment can have more dielectric layer 1920, in other embodiments, then can not there is dielectric layer 1920.Dielectric layer 1920 is formed on substrate 1100, and is formed at thin-film transistor 1300, mark M and is positioned on the insulating barrier 130I in perimeter circuit district 1113.Wherein, dielectric layer 1920 is located between the second protective layer 1910 and the first protective layer 1900; dielectric layer 1920 has the 3rd opening 1820 corresponding to the second opening 1810; to expose the portion of upper surface 1101 of substrate 1100, and the first protective layer 1900 is formed at thin-film transistor 1300, marks M, is positioned at the insulating barrier 130I in perimeter circuit district 1113, on the second protective layer 1910, dielectric layer 1920, first opening 1800, second opening 1810 and the 3rd opening 1820.
In another embodiment, please refer to Fig. 6, it is the partial cutaway schematic view corresponding to cutting line CC ' according to the motherboard in another embodiment of the present invention.As shown in Figure 6, compared to the embodiment of 5C figure, the dielectric layer 1920 of the present embodiment has the 4th opening 1830.4th opening 1830 is positioned at the top of mark M, and the first protective layer 1900 is formed on the 4th opening 1830, and the 4th opening 1830 alternative is not communicated with the first opening 1800, second opening 1810 and the 3rd opening 1820.In other embodiment, the 4th opening 1830 can be communicated with the first opening 1800, second opening 1810 and the 3rd opening 1820.Due to the existence of the 4th opening 1830, high low head between mark M and precut district 1130 is less to the embodiment of 2C figure compared to 2A, thus cutting motherboard can be improved with the yield producing image element array substrates, and aqueous vapor obstructing capacity can be strengthened, promote display floater reliability.
In another embodiment, the panel motherboard made with aforesaid motherboard, please refer to Fig. 7, and it is the partial cutaway schematic view of the panel motherboard according to another embodiment of the present invention.Refer to shown in Fig. 7 and Fig. 1 or Figure 14 and Fig. 3, just like the motherboard 1000 of aforementioned any embodiment, subtend substrate 2100, frame glue 2200, display dielectric layer 2300 and light separation material 2400 in panel motherboard 2000.Its center glue 2200 is arranged at the substrate 1100 corresponding to each display unit 1110 on motherboard 1000 and between subtend substrate 2100.Frame glue 2200 is between the first opening 1800 and the viewing area 1111 of each display unit 1110, and frame glue 2200 with Special composition (space), has display dielectric layer 2300 around the viewing area 1111 of each display unit 1110 in this space in filling out.Light separation material (photospacer) 2400 is arranged between subtend substrate 2100 and substrate 1100, and corresponds to precut district 1130 at least partially.The thickness of light separation material 2400 is optionally less than or equals in fact the thickness of display dielectric layer 2300, and light separation material 2400 more can improve the appropriate rate of cutting substrate again.In other words, in the present embodiment, precut district 1130 can through first opening 1800 (such as two Part I 1801 and 1805 or 1801 and 1807) of mark M with part, then light separation material 2400 can be stored in correspond to and mark on the position of M at least partially, and is arranged between this subtend substrate and this substrate; Or light separation material 2400 can be stored on the position of the first opening 1800 (such as two Part I 1801 and 1805 or 1801 and 1807) corresponding to part, and be arranged between this subtend substrate and this substrate; Or light separation material 2400 can be stored on the position of the first opening 1800 (such as two Part I 1801 and 1805 or 1801 and 1807) corresponding to mark M and part at least partially, and be arranged between this subtend substrate and this substrate.Moreover the profile described in above-mentioned Fig. 5 B, 5C and/or Fig. 6, also optionally comprises the light separation material 2400 described in Fig. 7 and associated description thereof, and very clearly can understand that relative position and supporting pass are.But in some embodiment, if the appropriate rate of the program of cutting motherboard suitable not too impact cutting, then can correspond on the position precuting district 1130 and there is not light separation material 2400.After must being noted that each display unit 1110 is cut, be exactly image element array substrates or the display floater of a display floater.
Therefore, when motherboard 1000 cuts the multiple image element array substrates obtained, the vertical view of single image element array substrates and the generalized section of each several part please refer to Fig. 8 to Fig. 9 D, wherein Fig. 8 is that the motherboard corresponded in Fig. 1 is split single the image element array substrates vertical view obtained, Fig. 9 A is the partial cutaway schematic view corresponding to cutting line aa ' in Fig. 8, and Fig. 9 B is the partial cutaway schematic view corresponding to cutting line bb ' in Fig. 8, Fig. 9 C is the partial cutaway schematic view corresponding to cutting line cc ' in Fig. 8, and Fig. 9 D is the partial cutaway schematic view corresponding to cutting line dd ' in Fig. 8.
As shown in Fig. 8, Fig. 9 A and Fig. 9 B, the image element array substrates 3000 in one embodiment of the invention has substrate 3100.Substrate 3100 comprises one and there is the viewing area 3111 of multiple pixel (sign) and at least one perimeter circuit district 3113 adjacent to viewing area 3111, embodiments of the invention are with at least one perimeter circuit district 3113 around viewing area 3113 for implementing example, but are not limited thereto.Must be noted that, after each display unit 1110 is cut from motherboard (motherboard 1100 of such as Fig. 1) along precut district (the precut district 1130 of such as Fig. 1), be exactly the image element array substrates of a display floater, then the edge of array of display pixels substrate is exactly precut district.
As shown in Figure 9 A, at least part of pixel region (sign) in viewing area 3111, the upper surface in substrate 3100 is provided with thin-film transistor 3300.Grid 330G, drain electrode 330D, source electrode 330S, insulating barrier 330I and oxide semiconductor layer 330O is had in thin-film transistor 3300.Insulating barrier 330I is between grid 330G and oxide semiconductor layer 330O, and source electrode 330S contacts with oxide semiconductor layer 330O with drain electrode 330D, namely source electrode 330S all can partly overlap with oxide semiconductor layer 330O with drain electrode 330D, and insulating barrier 330I also extends to perimeter circuit district 3113, wherein the dielectric constant of insulating barrier 330I is less than 6, is greater than 1.In special embodiment, the dielectric constant of insulating barrier 330I is less than 5, is greater than 1.Wherein, the material of insulating barrier 330I can be selected from the material of the insulating barrier 130I in above-described embodiment.In some embodiment, only have gate insulator in insulating barrier 330I, and in other embodiments, insulating barrier 330I is stacked by multi-layer insulation and forms, such as insulating barrier 330I is made up of the rete that stacks of gate insulator and etch stop layer.Although in the present embodiment, under grid 330G is positioned at oxide semiconductor layer 330O, namely lock type thin-film transistor is example at the end, is not limited thereto.In other embodiment, grid 330G is also positioned at the upper of oxide semiconductor layer 330O, and namely push up lock type thin-film transistor, or grid 330G is positioned on other position of oxide semiconductor layer 330O, namely the thin-film transistor of other type is also applicatory.Wherein oxide semiconductor layer 330O can be single or multiple lift structure, and its material is selected from the material in above-described embodiment described in oxide semiconductor layer 130O.
In addition, on thin-film transistor 3300, be also provided with the first holding wire 3400, secondary signal line 3500 and pixel electrode 3600.First holding wire 3400 is connected to grid 330G, then the first holding wire 3400 can be considered scan line or gate line, secondary signal line 3500 is connected to source electrode 330S, then secondary signal line 3500 can be considered data wire, and pixel electrode 3600 is connected to drain electrode 330D.Wherein, the first holding wire 3400, secondary signal line 3500 are all with pixel electrode 3600 and describe briefly.In addition, the first conductive pattern 3700 is also had on substrate 3100, first conductive pattern 3700 is arranged at perimeter circuit district 3113 and the edge of adjacent substrates 3100 (or being called side or sidewall) 310E, wherein, the insulating barrier 330I being arranged in perimeter circuit district 3113 is overlapping with the first conductive pattern 3700 with the mark m of pie graph 8.Insulating barrier 330I has the first opening 3800, the portion of upper surface 3101 (or can be described as inner surface) of substrate 3100 comes out via the first opening 3800, and the first opening 3800 to be positioned in perimeter circuit district 3113 and around viewing area 3111, and avoid marking m.Although in diagram in, the first conductive pattern 3700 covers insulating barrier 330I, however the first conductive pattern 3700 also can cover by insulating barrier 330I, the present invention is not limited.
Also have the first protective layer 3900, be formed on substrate 3100, and be formed at thin-film transistor 3300, mark m, be positioned on the insulating barrier 330I in perimeter circuit district 3113 and the first opening 3800.The dielectric constant of the first protective layer 3900 is greater than the dielectric constant of insulating barrier 330I.Wherein, the material of the first protective layer 3900 can be selected from the material of the first protective layer 1900 described in previous embodiment.Therefore; as shown in Figure 9 B; in the edge 310E of substrate 3100 cutting line bb ' corresponding to partial cutaway schematic view in; the first protective layer 3900 on substrate 3100 contacts in first opening 3800 place of insulating barrier 330I with substrate 3100; and the part beyond the first opening 3800, the upper surface of the first protective layer 3900 not contact substrate 3100.
And as shown in Figure 9 C, in the partial cutaway schematic view corresponding to the cutting line cc ' in mark m place, substrate 3100 has the first conductive pattern 3700, and the insulating barrier 330I on it.The first protective layer 3900 is coated with on insulating barrier 330I.
In some embodiment, go back to Fig. 8, mark m is positioned at four corners of image element array substrates 3000, first opening 3800 at least has two Part I, 3801,3803 and Part II 3805, the edge 310E of each Part I adjacent substrates 3100, Part II 3805 is communicated with Part I 3801 and Part I 3803 respectively, and Part II 3805 contiguous mark m, but be not adjacent to the edge 310E of substrate 3100.Now, Part II 3805 is not communicated with mark m, and the projection of shape of mark m after cutting can be L-type or other suitable shape.Wherein, when the sidewall 380E of each Part I and the edge 310E of substrate is projected on a plane, the distance d between both (i.e. the sidewall 380E of the sidewall 380E of Part I 3801 and the edge 310E of substrate and the Part I 3083 and edge 310E of substrate) is greater than 0.
And as shown in fig. 9d, in the partial cutaway schematic view corresponding to the cutting line dd ' in Part II 3805 place of other first opening 3800 of mark m.In the partial cutaway schematic view corresponding to cutting line bb ', the first protective layer 3900 on substrate 3100 covers insulating barrier 330I, and covers the sidewall of the first opening 3800, extends the upper surface 3101 of covered substrate 3100 until 310E place, edge always.By the first opening 3800, the insulating barrier 330I that dielectric constant is lower, because coated by the first protective layer 3900 that dielectric constant is higher, can't directly be exposed in air.Although in mark m place, namely the insulating barrier 330I at cutting line cc ' place can be exposed to air, but pass through the Part II 3805 of the first opening 3800, in Fig. 9 D, the insulating barrier 330I of left side (in Fig. 8, dd ' cutting line is away from the part of mark m) can't be connected with the insulating barrier 330I of right side (in Fig. 8, dd ' cutting line is near the part marking m).Even if therefore absorb the aqueous vapor in air near the insulating barrier 330I of mark m, aqueous vapor can't be absorbed near the insulating barrier 330I of viewing area, thus the probability making aqueous vapor affect the element of viewing area declines, and extends the life-span of panel.In like manner; the first opening 1800 in previous embodiment image element array substrates and motherboard thereof on relevant position; by the first opening 1800; the insulating barrier 130I that dielectric constant is lower is because coated by the first protective layer 1900 that dielectric constant is higher; directly can't be exposed in air after dicing and absorb aqueous vapor; thus the probability making aqueous vapor affect the element of viewing area declines, and extends the life-span of panel.
In another embodiment, please refer to Figure 10, it is the image element array substrates vertical view according to another embodiment of the present invention.As shown in Figure 10, compared to the embodiment of Fig. 8, the mark m of the present embodiment is not positioned at four corners of image element array substrates 3000, and the position that can be positioned at outside four corners, and the first opening 3800 at least has two Part I 3801,3807 and Part II 3809, each Part I is adjacent to edge 310E, Part II 3809 is communicated with Part I 3801 and Part I 3807 respectively, and contiguous mark m, but be not adjacent to edge 310E, can be considered that Part II 3809 is not communicated with mark m.Suppose that each display unit 1110 has multiple limit, then each limit can have the mark m shown at least one Figure 10, and the projection of shape of mark m is to be essentially linear for example, but is not limited thereto, such as, the projection of shape marking m can be curve or other suitable projection of shape.In other embodiment, in Figure 10, the mark m shown in Fig. 8 also can be comprised.In like manner, in Fig. 8, also can comprise the mark m shown in Figure 10, then all have mark m in corner and non-corner.Wherein, when the sidewall of each Part I and the edge 310E of substrate are projected on a plane, distance d ' between both (i.e. the sidewall of the sidewall of Part I 3081 and the edge 310E of substrate and Part I 3087 and the edge 310E of substrate) is greater than 0, and the cross-section structure of hatching aa ', bb ', cc ', dd ' and the ee ' shown in Figure 10 can consult Fig. 9 A ~ 9D and Figure 11 ~ 14.Be greater than 0 by distance d or d ', can ensure that, in the panel cut, insulating barrier 330I directly can't be exposed to air, between insulating barrier 330I and air, must have the first protective layer 3900 that insulating barrier 330I is isolated from air.
In another embodiment, please refer to Figure 11, it is the partial cutaway schematic view of the cutting line cc ' according to Fig. 8 in another embodiment of the present invention.As shown in figure 11, in the present embodiment, in the cut-away section structure of mark m position, be with the difference of the embodiment of Fig. 9 C, the image element array substrates 3000 in the present embodiment has more the second conductive pattern 3710.Second conductive pattern 3710 of part is positioned at perimeter circuit district 3113.Second conductive pattern 3710 is overlapping with the first conductive pattern 3700, and mark m be by the insulating barrier 330I being positioned at perimeter circuit district 3113, the first conductive pattern 3700 is overlapping with the second conductive pattern 3710 and form.And mark in the part of m, insulating barrier 330I is located between the first conductive pattern 3700 and the second conductive pattern 3710.
In an embodiment again, please refer to Figure 12 A to Figure 12 D, wherein Figure 12 A is the partial cutaway schematic view corresponding to cutting line aa ' according to the image element array substrates in yet another embodiment of the invention, and Figure 12 B is the partial cutaway schematic view corresponding to cutting line bb ' according to the image element array substrates in yet another embodiment of the invention, Figure 12 C is the partial cutaway schematic view corresponding to cutting line cc ' according to the image element array substrates in yet another embodiment of the invention, Figure 12 D is the partial cutaway schematic view corresponding to cutting line dd ' according to the image element array substrates in yet another embodiment of the invention.As shown in Figure 12 A to Figure 12 D, motherboard 3000 in the present embodiment is compared to the embodiment of Fig. 9 A to Fig. 9 D, have more the second protective layer 3910, second protective layer 3910 is formed at the upper of substrate 3100, and be formed at thin-film transistor 3300, mark m and be positioned on the insulating barrier 330I in perimeter circuit district 3113, wherein, second protective layer 3910 is located between insulating barrier 330I and the first protective layer 3900, second protective layer 3910 has the second opening 3810 corresponding to the first opening 3800, (inner surface is can be described as with the portion of upper surface 3101 exposing substrate 3100, because the remainder of the upper surface 3101 of substrate 3100 cover by each material layer and do not expose), and the first protective layer 3900 is formed at thin-film transistor 3300, mark m, be positioned at the insulating barrier 330I in perimeter circuit district 3113, second protective layer 3910, on first opening 3800 and the second opening 3810.In addition, the dielectric constant of the first protective layer 3900 can be greater than the dielectric constant of the second protective layer 3910.For example the dielectric constant of the second protective layer 3910 is optionally less than 6 and is greater than 1, and its material can be selected from insulating barrier in above-described embodiment or other suitable material.
In addition, same with reference to Figure 12 A to Figure 12 D, the image element array substrates 3000 in some embodiment can have more dielectric layer 3920, in other embodiments, then can not there is dielectric layer 3920.Dielectric layer 3920 is formed on substrate 3100, and is formed at thin-film transistor 3300, mark m and is positioned on the insulating barrier 330I in perimeter circuit district 3113.Wherein, dielectric layer 3920 is located between the second protective layer 3910 and the first protective layer 3900; dielectric layer 3920 has the 3rd opening 3820 corresponding to the second opening 3810; to expose the portion of upper surface 3101 of substrate 3100, and the first protective layer 3900 is formed at thin-film transistor 3300, marks m, is positioned at the insulating barrier 330I in perimeter circuit district 3113, on the second protective layer 3910, dielectric layer 3920, first opening 3800, second opening 3810 and the 3rd opening 3820.
In another embodiment, please refer to Figure 13, it is the partial cutaway schematic view corresponding to cutting line cc ' according to the image element array substrates in another embodiment of the present invention.As shown in figure 13, compared to the embodiment of Figure 12 C, the dielectric layer 3920 of the present embodiment has the 4th opening 3830.4th opening 3830 is positioned at the top of mark m, and the first protective layer 3900 is formed on the 4th opening 3830, and the 4th opening 3830 alternative is not communicated with the first opening 3800, second opening 3810 and the 3rd opening 3820.In other embodiment, the 4th opening 3830 can be communicated with the first opening 3800, second opening 3810 and the 3rd opening 3820.
In another embodiment, the display floater made with aforesaid image element array substrates, please refer to Figure 14, and it is the generalized section of the display floater according to another embodiment of the present invention.Refer to shown in Figure 14 and Fig. 8 or Figure 14 and Figure 10, just like the image element array substrates 3000 of aforementioned any embodiment, subtend substrate 4100, frame glue 4200, display dielectric layer 4300 and light separation material 4400 in display floater 4000.Its center glue 4200 is arranged between image element array substrates 3000 and subtend substrate 4100.Frame glue 4200 is between the first opening 3800 and viewing area 3111, and frame glue 4200 with Special composition (space), has display dielectric layer 4300 around viewing area 3111 in this space in filling out.Light separation material (photospacer) 4400 is arranged between subtend substrate 4100 and image element array substrates 3000, and the region corresponded between the sidewall of the first opening 3800 and the edge 310E of substrate 3100, and the thickness of light separation material 4400 is optionally less than or equal in fact the thickness of display dielectric layer 4300.In the present embodiment, light separation material 4400 can be stored in correspond to and mark on the position of m at least partially, and is arranged between this subtend substrate and this substrate; Or light separation material 4400 can be stored on the position of the first opening 3800 (such as two Part I 3801 and 3805 or 3801 and 3807) corresponding to part, and be arranged between this subtend substrate and this substrate; Or light separation material 4400 can be stored on the position of the first opening 3800 (such as two Part I 3801 and 3805 or 3801 and 3807) corresponding to mark m and part at least partially, and be arranged between this subtend substrate and this substrate.Moreover the profile described in above-mentioned Figure 12 B, 12C and/or Figure 13, also optionally comprises the light separation material 4400 described in Figure 14 and associated description thereof, and very clearly can understand that relative position and supporting pass are.But in some embodiment, then can there is not light separation material 4400 corresponding on the position in the precut district of motherboard in the appropriate rate of program suitable not too impact cutting of cutting motherboard.
By the image element array substrates disclosed in aforementioned multiple embodiment and motherboard thereof, due to the precut district part at motherboard, have opening directly by exposure of substrates, and directly cover opening and substrate by the first protective layer in herein, and opening also avoids mark.Therefore, when cutting motherboard and obtaining image element array substrates, what be directly exposed to air only has the first protective layer and substrate.In other words, all the other each layers, each element protect by the first protective layer and completely cut off air.Because the dielectric constant of the first protective layer is higher; aqueous vapor is easily barred from outside the first protective layer by the first protective layer; therefore the layers of material within the first protective layer not easily absorbs aqueous vapor, thus wherein oxide semiconductor is reduced because absorb moisture from degrading probability.Moreover; panel after cutting; although there are insulating barrier or other dielectric layers of the dielectric constant lower than the first protective layer in the region at its mark place; and aqueous vapor may from the side transmission of the dielectric layer of lower dielectric constant, but the opening (such as Fig. 7, Figure 14 etc.) that the mark after cutting has as aforementioned structure near frame Jiao Chu effectively can stop that aqueous vapor enters oxide semiconductor from the side of the dielectric layer of lower dielectric constant.In other words; there is each layer (such as insulating barrier) compared with low-k in viewing area because isolated from air by opening and the first protective layer; therefore described multiple layer can't be exposed in air; also therefore it absorbs the probability decline of aqueous vapor and deterioration, thus the life-span of panel and yield are promoted.
Although the present invention is with aforesaid embodiment openly as above, so itself and be not used to limit the present invention.Without departing from the spirit and scope of the present invention, the change of doing and retouching, all belong to scope of patent protection of the present invention.The protection range defined about the present invention please refer to appended claim.
Claims (26)
1. a motherboard, comprises:
One substrate, has multiple display unit, defines at least one precut district between described multiple display unit, and respectively this display unit comprises one and has the viewing area of multiple pixel region and at least one perimeter circuit district;
At least one thin-film transistor, to arrange on this substrate and to be positioned at least partially on described multiple pixel region, this thin-film transistor has a grid, one source pole, a drain electrode, an insulating barrier and monoxide semiconductor layer, wherein, this insulating barrier is between this grid and this oxide semiconductor layer, and this source/drain contacts with this oxide semiconductor layer, and this insulating barrier extends in this perimeter circuit district of respectively this display unit;
At least one first holding wire, to be arranged on this substrate and to be positioned at least partially on described multiple pixel region, and connecting this grid;
At least one secondary signal line, to be arranged on this substrate and to be positioned at least partially on described multiple pixel region, and connecting this source electrode;
At least one pixel electrode, to be arranged on this substrate and to be positioned at least partially on described multiple pixel region, and connecting this drain electrode;
One first conductive pattern, be arranged in this precut district of a part, and this first conductive pattern of a part is arranged in described multiple perimeter circuit district, wherein, this insulating barrier be positioned in this perimeter circuit district is overlapping with this first conductive pattern to form a mark, and this insulating barrier has one first opening, exposes the inner surface of this substrate, and this first opening to be positioned in this perimeter circuit district and around this viewing area, and avoid this mark; And
At least one first protective layer; be formed on this substrate; and be formed at this thin-film transistor, this mark, be positioned on this insulating barrier in this perimeter circuit district and this first opening; wherein; the dielectric constant of this first protective layer is greater than the dielectric constant of this insulating barrier; and the dielectric constant of this insulating barrier is less than 6, is greater than 1.
2. motherboard as claimed in claim 1, it is characterized in that, also comprising one second conductive pattern layer is arranged in this precut district of a part, and this second conductive pattern layer of a part is arranged in described multiple perimeter circuit district, wherein, this second conductive pattern layer and this first conductive pattern ply, be positioned at this insulating barrier in this perimeter circuit district, this first conductive pattern layer and this second conductive pattern ply to form this mark.
3. motherboard as claimed in claim 2, it is characterized in that, this insulating barrier is in the markers located between this first conductive pattern layer and this second conductive pattern layer.
4. motherboard as claimed in claim 2, it is characterized in that, also comprise one second protective layer, be formed on this substrate, and be formed at this thin-film transistor, this mark is with on this insulating barrier be positioned in this perimeter circuit district, wherein, this second protective layer is located between this insulating barrier and this first protective layer, this second protective layer has one second opening and corresponds to this first opening, to expose the inner surface of this substrate, and this first protective layer forms this thin-film transistor, this mark, be positioned at this insulating barrier in this perimeter circuit district, this second protective layer, on this first opening and this second opening.
5. motherboard as claimed in claim 4, it is characterized in that, the dielectric constant of this first protective layer is greater than the dielectric constant of this second protective layer, and the dielectric constant of this second protective layer and the dielectric constant of this insulating barrier are less than 6, are greater than 1.
6. motherboard as claimed in claim 4, it is characterized in that, also comprise a dielectric layer, be formed on this substrate, and be formed at this thin-film transistor, this mark is with on this insulating barrier be positioned in this perimeter circuit district, wherein, this dielectric layer is located between this second protective layer and this first protective layer, this second protective layer has one the 3rd opening and corresponds to this second opening, to expose the inner surface of this substrate, and this first protective layer forms this thin-film transistor, this mark, be positioned at this insulating barrier in this perimeter circuit district, this second protective layer, this first opening, on this second opening and the 3rd opening.
7. motherboard as claimed in claim 6; it is characterized in that, this dielectric layer has one the 4th opening, is positioned at the top of this mark; this first protective layer is formed on the 4th opening, and the 4th opening not with this first opening, this second opening and the 3rd open communication.
8. the motherboard as described in as arbitrary in claim 1 ~ 7, it is characterized in that, the dielectric constant of this insulating barrier is less than 5, is greater than 1.
9. the motherboard as described in as arbitrary in claim 1 ~ 7, it is characterized in that, this mark is positioned at four corners in this precut district, this first opening has two Part I and a Part II, respectively this Part I and this precut area overlapping, this Part II is communicated with respectively this Part I respectively, and this mark contiguous, but not precut area overlapping with this.
10. the motherboard as described in as arbitrary in claim 1 ~ 7, it is characterized in that, this mark is not positioned at four corners in this precut district, this first opening has two Part I and a Part II, respectively this Part I and this precut area overlapping, this Part II is communicated with respectively this Part I respectively, and this mark contiguous, but not precut area overlapping with this.
11. as arbitrary in claim 1 ~ 7 as described in motherboard, it is characterized in that, what this insulating barrier comprised a gate insulator or this gate insulator and an etch stop layer stacks rete.
12. 1 kinds of display floater motherboards, comprise:
A kind of motherboard as described in as arbitrary in claim 1 ~ 7;
One subtend substrate;
One frame glue, is arranged between this substrate of respectively this display unit and this subtend substrate, and wherein, this frame glue is around this viewing area of each this display unit to form a space, and this frame glue is between this first opening and this viewing area of each this display unit; And
One display dielectric layer, is formed in this space.
13. display floater motherboards as claimed in claim 12, is characterized in that, also comprise at least one smooth separation material and are arranged between this subtend substrate and this substrate, and correspond to this precut district.
14. 1 kinds of image element array substrates, comprise:
One substrate, comprises one and has the viewing area of multiple pixel region and at least one perimeter circuit district;
At least one thin-film transistor, to arrange on this substrate and to be positioned at least partially on described multiple pixel region, this thin-film transistor has a grid, one source pole, a drain electrode, an insulating barrier and monoxide semiconductor layer, wherein, this insulating barrier is between this grid and this oxide semiconductor layer, and this source/drain contacts with this oxide semiconductor layer, and this insulating barrier extends in this perimeter circuit district;
At least one first holding wire, to be arranged on this substrate and to be positioned at least partially on described multiple pixel region, and connecting this grid;
At least one secondary signal line, to be arranged on this substrate and to be positioned at least partially on described multiple pixel region, and connecting this source electrode;
At least one pixel electrode, to be arranged on this substrate and to be positioned at least partially on described multiple pixel region, and connecting this drain electrode;
One first conductive pattern, be arranged in described multiple perimeter circuit district and the edge of this substrate contiguous, wherein, be positioned at this insulating barrier in this perimeter circuit district and this first conductive pattern ply to form a mark, this insulating barrier has one first opening, expose the inner surface of this substrate, and this first opening to be positioned in this perimeter circuit district and around this viewing area, and to avoid this mark; And
At least one first protective layer; be formed on this substrate; and be formed at this thin-film transistor, this mark, be positioned on this insulating barrier in this perimeter circuit district and this first opening; wherein; the dielectric constant of this first protective layer is greater than the dielectric constant of this insulating barrier; and the dielectric constant of this insulating barrier is less than 6, is greater than 1.
15. image element array substrates as claimed in claim 14, it is characterized in that, also comprising one second conductive pattern layer is arranged in described multiple perimeter circuit district, wherein, this second conductive pattern layer and this first conductive pattern ply, and this insulating barrier, this first conductive pattern layer and this second conductive pattern ply that are positioned in this perimeter circuit district are to form this mark.
16. image element array substrates as claimed in claim 15, it is characterized in that, this insulating barrier is in the markers located between this first conductive pattern layer and this second conductive pattern layer.
17. image element array substrates as claimed in claim 15, it is characterized in that, also comprise one second protective layer, be formed on this substrate, and be formed at this thin-film transistor, this mark is with on this insulating barrier be positioned in this perimeter circuit district, wherein, this second protective layer is located between this insulating barrier and this first protective layer, this second protective layer has one second opening and corresponds to this first opening, to expose the inner surface of this substrate, and this first protective layer forms this thin-film transistor, this mark, be positioned at this insulating barrier in this perimeter circuit district, this second protective layer, on this first opening and this second opening.
18. image element array substrates as claimed in claim 17, it is characterized in that, the dielectric constant of this first protective layer is greater than the dielectric constant of this second protective layer, and the dielectric constant of this second protective layer and the dielectric constant of this insulating barrier are less than 6, are greater than 1.
19. image element array substrates as claimed in claim 17, it is characterized in that, also comprise a dielectric layer, be formed on this substrate, and be formed at this thin-film transistor, this mark is with on this insulating barrier be positioned in this perimeter circuit district, wherein, this dielectric layer is located between this second protective layer and this first protective layer, this second protective layer has one the 3rd opening and corresponds to this second opening, to expose the inner surface of this substrate, and this first protective layer forms this thin-film transistor, this mark, be positioned at this insulating barrier in this perimeter circuit district, this second protective layer, this first opening, on this second opening and the 3rd opening.
20. image element array substrates as claimed in claim 19; it is characterized in that, this dielectric layer has one the 4th opening, is positioned at the top of this mark; this first protective layer is formed on the 4th opening, and the 4th opening not with this first opening, this second opening and the 3rd open communication.
21. as arbitrary in claim 14 ~ 20 as described in image element array substrates, wherein, the dielectric constant of this insulating barrier is less than 5, is greater than 1.
22. as arbitrary in claim 14 ~ 20 as described in image element array substrates, it is characterized in that, this mark is positioned at four corners of this substrate, this first opening has two Part I and a Part II, respectively this Part I exposes this substrate edges and itself and this substrate edges has the distance being greater than 0, this Part II is communicated with respectively this Part I respectively, and this mark contiguous, but not overlapping with this substrate edges.
23. as arbitrary in claim 14 ~ 20 as described in image element array substrates, it is characterized in that, this mark is not positioned at four corners in this precut district, this first opening has two Part I and a Part II, respectively this Part I exposes this substrate edges and itself and this substrate edges has the distance being greater than 0, this Part II is communicated with respectively this Part I respectively, and this mark contiguous, but not overlapping with this substrate edges.
24. as arbitrary in claim 14 ~ 20 as described in image element array substrates, it is characterized in that, what this insulating barrier comprised a gate insulator or this gate insulator and an etch stop layer stacks rete.
25. 1 kinds of display floaters, comprise:
A kind of image element array substrates as described in as arbitrary in claim 14 ~ 20;
One subtend substrate;
One frame glue, is arranged between this image element array substrates and this subtend substrate, and wherein, this frame glue is around this viewing area to form a space, and this frame glue is between this first opening and this viewing area; And
One display dielectric layer, is formed in this space.
26. display floaters as claimed in claim 25, is characterized in that, also comprise at least one smooth separation material and are arranged between this subtend substrate and this image element array substrates, and have the place of the distance being greater than 0 corresponding to this first opening and this substrate edges.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104117031A TWI607552B (en) | 2015-05-27 | 2015-05-27 | Pixel array substrate, display panel, and master thereof |
| TW104117031 | 2015-05-27 |
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| Publication Number | Publication Date |
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| CN105047672A true CN105047672A (en) | 2015-11-11 |
| CN105047672B CN105047672B (en) | 2017-12-05 |
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| CN201510446804.9A Active CN105047672B (en) | 2015-05-27 | 2015-07-27 | Pixel array substrate, display panel and mother board thereof |
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| TW (1) | TWI607552B (en) |
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Also Published As
| Publication number | Publication date |
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| TWI607552B (en) | 2017-12-01 |
| TW201642448A (en) | 2016-12-01 |
| CN105047672B (en) | 2017-12-05 |
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