CN101728396A - Array substrate of thin film transistor and manufacturing method thereof - Google Patents
Array substrate of thin film transistor and manufacturing method thereof Download PDFInfo
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- CN101728396A CN101728396A CN200810167540A CN200810167540A CN101728396A CN 101728396 A CN101728396 A CN 101728396A CN 200810167540 A CN200810167540 A CN 200810167540A CN 200810167540 A CN200810167540 A CN 200810167540A CN 101728396 A CN101728396 A CN 101728396A
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Abstract
The invention relates a manufacturing method of an array substrate of a thin film transistor, which is characterized in that film layers is defined in each pattern manufacture procedure simultaneously to form a plurality of slash marks that are arranged in columns compactly along a vertical pre-slashing direction and formed on both sides of a pre-slashing position. Degree of excursion between an actual slashing position and the pre-slashing position can be displayed by means of the slash marks as scale marks. The slashing manufacturing procedure can be further adjusted to improve the yield of the manufacturing procedure.
Description
Technical field
The invention relates to a kind of thin-film transistor array base-plate and preparation method thereof, and particularly relevant for a kind of be formed with to cut split mark is cut the accuracy rate of splitting processing procedure with raising thin-film transistor array base-plate and manufacture method thereof.
Background technology
Thin Film Transistor-LCD (thin film transistor liquid crystaldisplay, TFT-LCD) fabrication schedule mainly can be divided into for three megastages, and it is respectively: thin-film transistor array processing procedure (TFT Array Process), liquid crystal cells processing procedure (LC CellProcess), module assembling processing procedure (Module Assembly Process).Wherein, the thin-film transistor array base-plate processing procedure is glass substrate to be seen through processing such as plated film, exposure, development, etching, is made into the processing procedure of the array base palte of thin-film transistor.The liquid crystal cells processing procedure mainly is that TFT substrate and colored filter that the array processing procedure is finished are done the orientation processing respectively, and carries out work such as contraposition pressing, cutting panel, injection liquid crystal, the attaching of polarisation version and detection.Module assembling processing procedure then is mainly to be that the TFT-LCD panel that cutting is finished is assembled processing procedure with outside spare parts such as drive IC, printed circuit board (PCB), versions backlight, is carrying out the final finished detection.
At present, domestic electronic industry manufacturing technology is quite skillful, and the yield of thin-film transistor array processing procedure and module assembling processing procedure all remains on more than 95% usually.But in stage of liquid crystal cells processing procedure degree of having difficulties problem of higher then, this also is the minimum part of yield of existing TFT-LCD panel processing procedure.
Particularly, " cut and the split " step in the liquid crystal cells processing procedure is one of important key that influences yield.Because the production capacity of electronic industry is required and will constantly promotes, and the raising of basic utilization rate, closely the design of setting type also has the trend of increase.Therefore, split the also just more raising of accuracy requirement of processing procedure for cutting of panel.
In addition, have exposure to split the correlation technique that cutting of processing procedure split the making and the design of mark about cutting at panel in some patent datas, for example US 6,717, and 629; TW 200702863; TW 554196.Above document is all the reference data of this case.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of thin-film transistor array base-plate exactly, has to judge that actual cutting split the position and cut the cutting of degrees of offset of splitting the position in advance and split mark, cuts the accuracy of splitting with further raising.
Another object of the present invention provides a kind of manufacture method of thin-film transistor array base-plate, can form to cut with easy method and split mark, and split mark and split the position and cut the degrees of offset of splitting the position in advance, and then can improve process rate to demonstrate actual cutting by cutting.
For reaching above-mentioned or other purpose, the present invention proposes a kind of thin-film transistor array base-plate, and it comprises: substrate, a plurality of dot structure and a plurality of cutting are split mark.Wherein, substrate has an assembly district and all split the mark zone.These dot structures are disposed in the assembly district, and each dot structure comprises a thin-film transistor, a pixel electrode and a protective layer that covers this thin-film transistor.These are cut and split marker ligand and place to cut and split the mark zone, and are positioned at one and cut the both sides of splitting the position in advance, and split direction and be closely aligned and embark on journey along vertically cutting in advance.And these are cut, and to split mark be by two or more at least colors, two or more at least shapes, at least a color and at least a shape matched combined or above-mentioned both matched combined form.
In one embodiment of this invention, the first, second, third, fourth, the 5th cuts and splits the identical shape of being shaped as of mark, but color is incomplete same.
In one embodiment of this invention, the first, second, third, fourth, the 5th cut and split the diverse shape of being shaped as of mark.
In one embodiment of this invention, the first, second, third, fourth, the 5th cut the shape that part is identical, part is different that is shaped as of splitting mark.
In one embodiment of this invention, each is cut and splits mark and to cut the distance of splitting the position in advance be the multiple of a fixed value.
In one embodiment of this invention, the first, second, third, fourth, the 5th cut that to split mark be that material difference according to mark is staggered.
In one embodiment of this invention, the first, second, third, fourth, the 5th cut that to split mark be that shape difference according to mark is staggered.
In one embodiment of this invention, these to cut the some of splitting in the mark identical with the material of the grid of thin-film transistor.
In one embodiment of this invention, these to cut the some of splitting in the mark identical with the material of the semiconductor layer of thin-film transistor.
In one embodiment of this invention, these materials of cutting the source electrode of the some split in the mark and thin-film transistor and drain electrode are identical.
In one embodiment of this invention, these to cut the some of splitting in the mark identical with the material of protective layer.
In one embodiment of this invention, these to cut the some of splitting in the mark identical with the material of pixel electrode.
For reaching above-mentioned or other purpose, the present invention proposes a kind of manufacture method of thin-film transistor array base-plate in addition, comprises the following steps.At first, provide a substrate, this substrate has an assembly district and all split the mark zone.Then, form one first conductive layer on substrate, this first conductive layer of patterning afterwards forming a plurality of grids on the substrate in assembly district, and forms at least one first and cuts and split mark in cutting simultaneously on the substrate that splits the mark zone.Then, on substrate, form a dielectric layer and semiconductor material layer in regular turn, cut and split mark to cover these grids and first.Subsequently, the patterned semiconductor material layer forming a channel layer on this dielectric layer of each grid top, and forms at least one second and cuts and split mark in cutting simultaneously on the dielectric layer that splits the mark zone.Continue it, on substrate, form one second conductive layer.Then, patterning second conductive layer forming an one source pole and a drain electrode in each grid top, and is cut and is split mark in cutting on the dielectric layer that splits the mark zone formation at least one the 3rd simultaneously.Afterwards, on substrate, form a protective layer.Subsequently, the patterning protective layer forming the contact window expose each drain electrode in the assembly district, and forms at least one the 4th and cuts and split mark in cutting simultaneously on the dielectric layer that splits the mark zone.Then, on substrate, form a transparent conductive material layer.Then, the patterning transparent conductive material layer, forming a plurality of pixel electrodes, each pixel electrode electrically connects via contact window and corresponding drain electrode, and forms at least one the 5th on the dielectric layer that splits the mark zone and cut and split mark in cutting simultaneously.Wherein, these are cut to split to be labeled as along vertically cutting in advance and split direction and be closely aligned and embark on journey, and these are cut and split mark and be formed at one and cut the both sides of splitting the position in advance.
In one embodiment of this invention, the first, second, third, fourth, the 5th cuts and splits the identical shape of being shaped as of mark, but color is incomplete same.
In one embodiment of this invention, the first, second, third, fourth, the 5th cut and split the diverse shape of being shaped as of mark.
In one embodiment of this invention, the first, second, third, fourth, the 5th cut the shape that part is identical, part is different that is shaped as of splitting mark.
In one embodiment of this invention, each is cut and splits mark and to cut the distance of splitting the position in advance be the multiple of a fixed value.
In one embodiment of this invention, the first, second, third, fourth, the 5th cut that to split mark be that material difference according to mark is staggered.
In one embodiment of this invention, the first, second, third, fourth, the 5th cut that to split mark be that shape difference according to mark is staggered.
Because, thin-film transistor array base-plate of the present invention has and a plurality ofly splits mark with as calibration with cutting of forming of shape and/or colour match, therefore can use and compare actual cutting and split the position and split the position and whether produce skew and degrees of offset with cutting in advance, and then can split processing procedure and do accurately and to adjust cutting, to improve process rate.In addition, of the present inventionly cut that to split mark be in the processing procedure of thin-film transistor array base-plate, when the patterning step of carrying out each time and form simultaneously, so manufacture method is simple and easy, and can save the processing procedure cost.In addition, of the present invention cut split mark also can be further used as layer with layer between the mark aimed at, can improve the accuracy rate of level to level alignment.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is according to looking schematic diagram on the thin-film transistor array base-plate that one embodiment of the invention illustrated.
Fig. 2 A, 2B, 2C, 2D are the schematic diagram that splits mark of cutting according to a plurality of embodiment of the present invention illustrated.
Fig. 3 A to Fig. 3 J is the making flow process generalized section according to a kind of thin-film transistor array base-plate that embodiments of the invention illustrated.
[primary clustering symbol description]
100: thin-film transistor array base-plate 116: dot structure
118: thin-film transistor 130: scan wiring
132: shared wiring 134: data wiring
110,300: substrate 112,301a: the assembly district
114,301b: cut and split 302: the first conductive layers in mark zone
124,303a: grid 303b: first cuts and splits mark
304: dielectric layer 306: semiconductor material layer
306a: channel layer 306b: semiconductor layer
308: nurse contact material layer 308a difficult to understand, 308b: ohmic contact layer
Cut at 309: the second and to split 310: the second conductive layers of mark
126,311a: source electrode 128,311b: drain electrode
311c: the 3rd cuts and splits mark 312,313a: protective layer
313b: the 4th cuts and splits mark 122,314: contact window
316: transparent conductive material layer 120,317a: pixel electrode
317b: the 5th cuts and splits mark 136,320: cut in advance and split the position
M1～Mn: cut and split mark
Embodiment
Fig. 1 is according to looking schematic diagram on the thin-film transistor array base-plate that one embodiment of the invention illustrated.
Please refer to Fig. 1, the substrate 110 of the thin-film transistor array base-plate 100 of present embodiment has an assembly district 112 and splits mark zone 114 with all.This substrate 110 can be the transparency carrier of a glass substrate or other material.In the assembly district 112 of substrate 110, dispose a plurality of dot structures 116.Each dot structure 116 includes a protective layer (not illustrating) of a thin-film transistor 118, a pixel electrode 120 and cover film transistor 118.Wherein, thin-film transistor 118 mainly is by grid 124, source electrode 126 and drains 128 and constitute, and also comprises between grid 124 and source electrode 126, the drain electrode 128 and dispose semiconductor layer (not illustrating).In addition, the contact hole that has drain electrode of exposing 128 in the protective layer opens 122, and pixel electrode 120 is via contact window 122 and corresponding drain electrode 128 electric connections.Certainly, on the substrate 110 in assembly district 112, also can comprise scan wiring 130, shared wiring 132 that electrically connects with grid 124 and the data wiring 134 that electrically connects with source electrode 126.
In addition, splitting in the mark zone 114 cutting of substrate 110 then is to dispose a plurality of cutting to split mark M1, M2, M3...Mn-1, Mn (n is a positive integer).These are cut and split mark M1～Mn and be positioned at one to cut the both sides of splitting position 136 in advance, and cut in advance and split direction and for example be the z direction, cut to split mark M1～Mn then for splitting direction (being the x direction) and be closely aligned and embark on journey along vertically cutting in advance.
On the other hand, these are cut each that split among mark M1, M2, M3...Mn-1, the Mn and cut and split mark and cut the multiple that the distance of splitting position 136 can be a fixed value in advance, and each is cut and splits mark and then can represent a specific scale value.Thus, split the position and these split the relative position relation of mark as cutting of calibration by actual cutting, can know that picking out actual cutting splits the position and split position 136 and whether produce skew and degrees of offset with cutting in advance, and can be further split processing procedure and do accurately and adjust cutting.
In addition, in the present embodiment, be to be all the trapezoidal explanation of doing, but the invention is not restricted to this that it can also be other kind shape to cut the shape of splitting mark M1, M2, M3...Mn-1, Mn.In one embodiment, of the present invention cutting split mark and be can be identical shape, but color is incomplete same, and for example each shape of cutting the row mark can be other polygons such as rhombus, square, triangle, but color is incomplete same.In addition, shown in Fig. 2 A, the shape of splitting mark of cutting of the present invention also can be diverse shape.Or, shown in Fig. 2 B, the shape that part is identical, part is different that is shaped as of splitting mark of cutting of the present invention.Or be shown in Fig. 2 C, of the present inventionly to cut that to split mark be that shape difference according to mark is staggered.
Be noted that especially, in the present invention, not only can utilize and cut the shape of splitting mark and represent specific scale value, can also using each, to cut the material of splitting mark different and the different characteristic of color that shown is split the position and cut the degrees of offset of splitting the position in advance more clearly to express actual cutting.In detail, of the present inventionly cut that to split mark can for example be when making dot structure and form simultaneously.Therefore, the some of splitting in the mark of cutting of the present invention can be identical with the material of the grid of thin-film transistor, semiconductor layer, source electrode, drain electrode, also can be identical with the material of protective layer, pixel electrode.
Hold above-mentionedly, of the present invention cutting split mark and can be staggered (shown in Fig. 2 D) according to cutting the material difference of splitting mark, just and split color that mark shows and can know and judge that actual cutting split the position and split the position and whether produce and be offset and degrees of offset with cutting in advance by cutting.
In other embodiments, of the present invention cutting split mark and also cut the shape of splitting mark by application and form with the matched combined of color, and can do design and adjustment according to actual needs.
Next, especially exemplified by an embodiment to explain the manufacture method of thin-film transistor array base-plate of the present invention.
Fig. 3 A to Fig. 3 J is the making flow process generalized section according to a kind of thin-film transistor array base-plate that embodiments of the invention illustrated.
At first, please refer to Fig. 3 A, a substrate 300 is provided, this substrate 300 has assembly district 301a and splits mark zone 301b with cutting.This substrate 300 can for example be the transparency carrier of glass substrate or other material.Then, on substrate 300, form first conductive layer 302.The material of this first conductive layer 302 for example is chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminium (A1) and alloy thereof or other electric conducting material that is fit to.
Then, please refer to Fig. 3 B, first conductive layer 302 is carried out patterning, forming grid 303a in assembly district 301a, and split mark zone 301b and form at least one and first cut and split mark 303b in cutting simultaneously.Be noted that first cuts and split mark 303b and grid 303a is formed by patterning first conductive layer 302.
Afterwards, please refer to Fig. 3 C, on substrate 300, form dielectric layer 304 in regular turn and cut with cover gate 303a and first with semiconductor material layer 306 and split mark 303b.Wherein, dielectric layer 304 is as gate insulation layer, and its material for example is silicon nitride, silica, silicon oxynitride or other suitable dielectric material.The material of semiconductor material layer 306 can be amorphous silicon (amorphoussilicon).In addition, in one embodiment, also can be formed with nurse contact material layer 308 difficult to understand more in addition on semiconductor material layer 306, its material can be through doped amorphous silicon.
Then, please refer to Fig. 3 D, nurse contact material layer 308 difficult to understand is carried out patterning with semiconductor material layer 306, forming channel layer 306a and ohmic contact layer 308a on the dielectric layer 304 of grid 303a top, and at least one second is cut and splits mark 309 in cutting on the dielectric layer 304 that splits mark zone 301b formation simultaneously.Second cuts and splits mark 309 and constituted by cutting the semiconductor layer 306b and the ohmic contact layer 308b that split mark zone 301b.In the present embodiment, second cut that to split mark 309 be to be formed in abutting connection with first to cut a side of splitting mark 303b.
Subsequently, please refer to Fig. 3 E, compliance ground forms second conductive layer 310 on substrate 300.The material of this second conductive layer 310 for example is chromium, tungsten, tantalum, titanium, molybdenum, aluminium or and alloy or other electric conducting material that is fit to.
Continue it, please refer to Fig. 3 F, ohmic contact layer 308a to second conductive layer 310 and assembly district 301a carries out patterning, make ohmic contact layer 308a expose the part channel layer 306a surface of grid 303a top, form an one source pole 311a and a drain electrode 311b with ohmic contact layer 308a both sides in grid 303a top.And, in patterning second conductive layer 310, form at least one the 3rd and cut and split mark 311c in cutting on the dielectric layer 304 that splits mark zone 301b.That is be, the 3rd cut split mark 311c and source electrode 311a, drain electrode 311b is formed by patterning second conductive layer 310.In the present embodiment, the 3rd cut and split mark 311c and be formed in abutting connection with second to cut a side of splitting mark 309.
Then, please refer to Fig. 3 G, compliance ground forms a protective layer 312 on substrate 300.The material of this protective layer 312 for example is silicon nitride, silica or other suitable dielectric material
Then, please refer to Fig. 3 H, protective layer 312 is carried out patterning, forming protective layer 313a in assembly district 301a, and protective layer 313a has the contact window 314 of the part of exposing drain electrode 311b.And, in the time of patterning protective layer 312, form at least one the 4th on the dielectric layer 304 that splits mark zone 301b and cut and split mark 313b in cutting.That is be that the 4th cuts and split mark 313b and protective layer 313a is formed by patterning protective layer 312.In the present embodiment, the 4th cut and split mark 313b and be formed in abutting connection with the 3rd to cut a side of splitting mark 310c.
Afterwards, please refer to Fig. 3 I, compliance ground forms a transparent conductive material layer 316 on substrate 300, the material of this transparent conductive material layer 316 for example be indium tin oxide (Indium tinoxide, ITO) or other suitable transparent conductive material.
Continue it, please refer to Fig. 3 J, transparent conductive material layer 316 is carried out patterning, to form via the pixel electrode 317a of contact window 314 with drain electrode 311b electric connection.And, in patterning transparent conductive material layer 316, form at least one the 5th and cut and split mark 317b in cutting on the dielectric layer 304 that splits mark zone 301b.That is be that the 5th cuts and split mark 317b and pixel electrode 317a is formed by patterning transparent conductive material layer 316.In the present embodiment, the 5th cut and split mark 317b and be formed in abutting connection with the 4th to cut a side of splitting mark 313b.So far, promptly finish the making flow process of thin-film transistor array base-plate.
In the present embodiment, shown in Fig. 3 J, label 320 is to represent to cut in advance to split the position, and it for example is that the position is cut second and split mark 309 and the 3rd and cut the adjoiner that splits mark 311c, and to split direction be the z direction and cut in advance.And first cuts and splits mark 303b, second and cut and split mark the 309, the 3rd and cut and split mark 311c, the 4th and cut and split mark 313b and the 5th and cut and split mark 317b for splitting direction (being the x direction) and be closely aligned and embark on journey along vertical cutting in advance.These are cut and split mark 303b, 309,311c, 313b and 317b and be formed to cut the both sides of splitting position 320 in advance, split the position and cut the degrees of offset of splitting position 320 in advance in order to demonstrate actual cutting, and can more improve so that cut the accuracy of splitting processing procedure.
In addition, in the present embodiment, these are cut and split mark 303b, 309,311c, 313b and 317b and form in the mode of adjacent arrangement in regular turn.Yet the manufacture method of present embodiment only is a wherein example as an illustration, is not in order to limiting the present invention, and the present invention is not split putting in order of mark and done special qualification cutting.In other embodiments, also can for example be: formation first be earlier cut and is split mark 303b, second cuts that to split mark 309 be to be separated by first to cut and split mark 303b one specific range and form, the 3rd cuts and splits mark 311c and be separated by second to cut and split mark 309 1 specific ranges and form, the 4th cuts and splits mark 313b and be formed at first and cut and split mark 303b and second and cut and split between the mark 309, and the 5th cuts and split mark 317b and be formed at second and cut and split mark 309 and the 3rd and cut and split between the mark 311c (this kind put in order be not illustrated in graphic in).Certainly, split putting in order of mark and can adjust according to actual demand and design formed the cutting of patterning step each time, and know those skilled in the art and should can implement according to this according to the method for the foregoing description institute teaching.
In addition, in the present embodiment, when the patterning step of carrying out each time, all be to cut and split mark explanation to show one.Yet the present invention does not cut the quantity of splitting mark to these and does special qualification, and its visual actual processing procedure need adjust.That is be, when the patterning step of carrying out each time, can form a plurality of cutting and split mark, and patterning step each time formed cut the quantity of splitting mark also can be inequality.
On the other hand, because when the patterning step of carrying out each time, all can be simultaneously split the mark zone and form to cut and split mark in cutting, and these are cut to split to be labeled as to be closely aligned and embark on journey, therefore formed the cutting of patterning step each time split the usefulness that mark also can be used as the alignment mark between each rete and the rete, to improve the accuracy rate of level to level alignment.
In sum, the present invention utilizes that configuration is a plurality of in thin-film transistor array base-plate splits mark as calibration with cutting of shape or colour match, split the position and split the position and whether produce skew and degrees of offset with cutting in advance to compare actual cutting, and then can split processing procedure and do accurately and to adjust cutting, to improve process rate.And because the present invention is in the processing procedure of thin-film transistor array base-plate, when the patterning step of carrying out each time and form these simultaneously and cut and split mark, so manufacture method is simple and easy, and can save the processing procedure cost.In addition, of the present invention cut split mark also can be further used as layer with layer between the mark aimed at, so can improve the accuracy rate of level to level alignment.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (19)
1. a thin-film transistor array base-plate is characterized in that, comprising:
One substrate, this substrate have an assembly district and all split the mark zone;
A most dot structure are disposed in this assembly district, and each dot structure comprises a thin-film transistor, a pixel electrode and a protective layer that covers this thin-film transistor; And
Cut for most and split mark, being disposed at this cuts and splits in the mark zone, those are cut to split to be labeled as along vertically cutting in advance and split direction and be closely aligned and embark on journey, and those are cut and split mark and be positioned at one and cut the both sides of splitting the position in advance, and wherein those cut that to split mark be by two or more at least colors, two or more at least shapes, at least a color and at least a shape matched combined or above-mentioned both matched combined form.
2. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, those are cut and split the identical shape of being shaped as of mark, but color is incomplete same.
3. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, those are cut and split the diverse shape of being shaped as of mark.
4. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, those cut the shape that part is identical, part is different that is shaped as of splitting mark.
5. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, each those cut and split mark and this to cut the distance of splitting the position in advance be the multiple of a fixed value.
6. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, those are cut, and to split mark be that material difference according to mark is staggered.
7. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, those are cut, and to split mark be that shape difference according to mark is staggered.
8. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, a part of those cut that to split mark identical with the material of the grid of this thin-film transistor.
9. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, a part of those cut that to split mark identical with the material of the semiconductor layer of this thin-film transistor.
10. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, the material that a part of those are cut the source electrode that splits mark and this thin-film transistor and drain electrode is identical.
11. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, a part of those cut that to split mark identical with the material of this protective layer.
12. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, a part of those cut that to split mark identical with the material of this pixel electrode.
13. the manufacture method of a thin-film transistor array base-plate is characterized in that, comprising:
One substrate is provided, and this substrate has an assembly district and all split the mark zone;
On this substrate, form one first conductive layer;
This first conductive layer of patterning forming most grids on this substrate in this assembly district, and is cut in this simultaneously and is formed at least one first on this substrate that splits the mark zone and cut and split mark;
On this substrate, form a dielectric layer, semiconductor material layer in regular turn, cut and split mark to cover those grids and this first;
This semiconductor material layer of patterning forming a channel layer on this dielectric layer of each those grids top, and is cut in this simultaneously and is formed at least one second on this dielectric layer that splits the mark zone and cut and split mark;
On this substrate, form one second conductive layer;
This second conductive layer of patterning forming one source poles and a drain electrode in each those grids top, and is cut on this dielectric layer that splits the mark zone formation at least one the 3rd in this simultaneously and is cut and split mark;
On this substrate, form a protective layer;
This protective layer of patterning forming a contact window that exposes each those drain electrode in this assembly district, and is cut in this simultaneously and is formed at least one the 4th on this dielectric layer that splits the mark zone and cut and split mark;
On this substrate, form a transparent conductive material layer; And
This transparent conductive material layer of patterning, forming most pixel electrodes, each pixel electrode electrically connects with corresponding this drain electrode via this contact window, and the while cut on this dielectric layer that splits the mark zone formation at least one the 5th in this and cut and split mark,
Wherein those are cut to split to be labeled as along vertically cutting in advance and split direction and be closely aligned and embark on journey, and those are cut and split mark and be formed at one and cut the both sides of splitting the position in advance.
14. the manufacture method of thin-film transistor array base-plate as claimed in claim 13 is characterized in that, those are cut and split the identical shape of being shaped as of mark, but color is incomplete same.
15. the manufacture method of thin-film transistor array base-plate as claimed in claim 13 is characterized in that, those are cut and split the diverse shape of being shaped as of mark.
16. the manufacture method of thin-film transistor array base-plate as claimed in claim 13 is characterized in that, those cut the shape that part is identical, part is different that is shaped as of splitting mark.
17. the manufacture method of thin-film transistor array base-plate as claimed in claim 13 is characterized in that, each those cut and split mark and this to cut the distance of splitting the position in advance be the multiple of a fixed value.
18. the manufacture method of thin-film transistor array base-plate as claimed in claim 13 is characterized in that, those are cut, and to split mark be that material difference according to mark is staggered.
19. the manufacture method of thin-film transistor array base-plate as claimed in claim 13 is characterized in that, those are cut, and to split mark be that shape difference according to mark is staggered.
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| CN2008101675403A CN101728396B (en) | 2008-10-10 | 2008-10-10 | Array substrate of thin film transistor and manufacturing method thereof |
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| CN2008101675403A CN101728396B (en) | 2008-10-10 | 2008-10-10 | Array substrate of thin film transistor and manufacturing method thereof |
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| CN101728396B CN101728396B (en) | 2012-08-15 |
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Cited By (4)
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| CN103969943A (en) * | 2013-01-25 | 2014-08-06 | 北京京东方光电科技有限公司 | Method for marking substrate |
| CN105047672A (en) * | 2015-05-27 | 2015-11-11 | 友达光电股份有限公司 | Pixel array substrate, display panel and mother board thereof |
| CN105428469A (en) * | 2014-09-19 | 2016-03-23 | 晶能光电（江西）有限公司 | Stealth cutting method for sapphire substrate LED chip |
| CN106328554A (en) * | 2016-08-26 | 2017-01-11 | 武汉华星光电技术有限公司 | Overlay structure, display device and method for measuring overlay precision by utilizing overlay structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20080061569A (en) * | 2006-12-28 | 2008-07-03 | 삼성전자주식회사 | Mother display panel for manufacturing a display panel |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103969943A (en) * | 2013-01-25 | 2014-08-06 | 北京京东方光电科技有限公司 | Method for marking substrate |
| CN105428469A (en) * | 2014-09-19 | 2016-03-23 | 晶能光电（江西）有限公司 | Stealth cutting method for sapphire substrate LED chip |
| CN105047672A (en) * | 2015-05-27 | 2015-11-11 | 友达光电股份有限公司 | Pixel array substrate, display panel and mother board thereof |
| CN105047672B (en) * | 2015-05-27 | 2017-12-05 | 友达光电股份有限公司 | Pixel array substrate, display panel and mother board thereof |
| CN106328554A (en) * | 2016-08-26 | 2017-01-11 | 武汉华星光电技术有限公司 | Overlay structure, display device and method for measuring overlay precision by utilizing overlay structure |
| CN106328554B (en) * | 2016-08-26 | 2019-05-21 | 武汉华星光电技术有限公司 | Aligning structure, display device and the method using aligning structure measurement aligning accuracy |
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