CN105047672B

CN105047672B - Pixel array substrate, display panel and mother board thereof

Info

Publication number: CN105047672B
Application number: CN201510446804.9A
Authority: CN
Inventors: 陈铭耀; 陈培铭
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2015-05-27
Filing date: 2015-07-27
Publication date: 2017-12-05
Anticipated expiration: 2035-07-27
Also published as: TWI607552B; CN105047672A; TW201642448A

Abstract

The embodiment of the invention discloses a pixel array substrate, a display panel and a motherboard thereof. The substrate has a display area and at least one peripheral circuit area. The thin film transistor is arranged on the substrate and positioned in the display area, and the thin film transistor is provided with an insulating layer extending to the peripheral circuit area. The first signal line, the second signal line and the pixel electrode are arranged on the substrate, are positioned in the display area and are connected with the thin film transistor. The first conductive pattern is arranged in the peripheral circuit area and adjacent to the edge of the substrate, and is overlapped with the insulating layer to form a mark. The thin film transistor, the mark and the insulating layer on the peripheral circuit area are covered by a first protective layer, wherein the dielectric constant of the first protective layer is larger than that of the insulating layer. The technical scheme of the embodiment of the invention reduces the probability of deterioration of the internal circuit caused by water vapor.

Description

Image element array substrates, display panel and its motherboard

Technical field

The present invention relates to technical field of display panel, more particularly to a kind of pel array base of applied film transistor technology Plate, display panel and its motherboard.

Background technology

It is widely used in the image element array substrates that thin film transistor (TFT) technique makes in the field of display panel.Due to thin Integrated circuit can be implemented on glass substrate by film transistor, therefore can be used for producing the display panel of high degree of integration.

However, the display panel made by thin-film transistor technologies often has colour cast after long-time use in edge Phenomenon.To find out its cause, because the steam in environment enters pel array base from the image element array substrates edge of display panel Plate so that the oxide semiconductor in the thin film transistor (TFT) of part absorbs steam and causes deterioration in characteristics.Therefore, how water is prevented Vapour enters image element array substrates to improve the life-span of produced display panel, is a urgent problem to be solved.

The content of the invention

The problem of in view of the above, the present invention propose a kind of image element array substrates, display panel and its motherboard design, to Reduce the probability that steam deteriorates internal circuit.

Image element array substrates disclosed in this invention, have substrate, thin film transistor (TFT), the first signal wire, secondary signal line, Pixel electrode, the first conductive pattern and the first protective layer.Substrate has viewing area and an at least perimeter circuit area, and viewing area has Multiple pixel regions.Thin film transistor (TFT) is arranged on substrate and at least one of pixel region, thin film transistor (TFT) has grid Pole, source electrode, drain electrode, insulating barrier and oxide semiconductor layer, wherein, insulating barrier between grid and oxide semiconductor layer, And source/drain contacts with oxide semiconductor layer, and insulating barrier extends to perimeter circuit area.First signal wire, is arranged at substrate Above and in partial pixel area, and connect grid.Secondary signal line is arranged on substrate and in partial pixel area, and even Connect source electrode.Pixel electrode is arranged on substrate and in partial pixel area, and connects drain electrode.First conductive pattern is arranged at week Side line areas and the edge of adjacent substrates, wherein, the insulating barrier positioned at perimeter circuit area is overlapping with the first conductive pattern layer with structure Into mark, insulating barrier has the first opening, exposes the inner surface of substrate, and the first opening in perimeter circuit area and is surround Viewing area, and avoid marking.First protective layer is formed on substrate, and is formed at thin film transistor (TFT), mark, positioned at perimeter circuit On insulating barrier and the first opening in area, wherein the dielectric constant of the first protective layer is more than the dielectric constant of insulating barrier, and insulate The dielectric constant of layer is less than 6, more than 1.

In an embodiment, also it is arranged at comprising one second conductive pattern layer in the multiple perimeter circuit area, wherein, should Second conductive pattern layer is overlapping with first conductive pattern layer, and the insulating barrier in the perimeter circuit area, this first leads Electrograph pattern layer is overlapping with second conductive pattern layer to form the mark.

In an embodiment, the insulating barrier in the markers is located in first conductive pattern layer and second conductive pattern Between layer.

In an embodiment, also comprising one second protective layer, be formed on the substrate, and be formed at the thin film transistor (TFT), The mark with the insulating barrier in the perimeter circuit area, wherein, second protective layer be located in the insulating barrier with this Between one protective layer, there is second protective layer one second opening to correspond to first opening, to expose the interior table of the substrate Face, and first protective layer formed the thin film transistor (TFT), the mark, the insulating barrier in the perimeter circuit area, this second In protective layer, first opening and second opening.

In an embodiment, the dielectric constant of first protective layer is more than the dielectric constant of second protective layer, and this The dielectric constant of two protective layers is less than 6 with the dielectric constant of the insulating barrier, more than 1.

In an embodiment, also comprising a dielectric layer, it is formed on the substrate, and is formed at the thin film transistor (TFT), the mark In note and the insulating barrier being located in the perimeter circuit area, wherein, the dielectric layer is located in second protective layer and first guarantor Between sheath, there is second protective layer one the 3rd opening to correspond to second opening, to expose the inner surface of the substrate, and First protective layer forms the thin film transistor (TFT), the mark, the insulating barrier in the perimeter circuit area, second protection In layer, first opening, second opening and the 3rd opening.

In an embodiment, the dielectric layer has one the 4th opening, and positioned at the top of the mark, first protective layer is formed In the 4th opening on, and the 4th opening not with this first opening, this second opening and the 3rd open communication.

In an embodiment, the dielectric constant of the insulating barrier is less than 5, more than 1.

In an embodiment, the mark is located at four corners of the substrate, first opening have two Part I with One Part II, respectively the Part I exposes the substrate edges and its has the distance for being more than 0 with the substrate edges, and this second Part is respectively communicated with the respectively Part I, and the neighbouring mark, but not overlapping with the substrate edges.

In an embodiment, the mark does not have 2 first positioned at four corners in the precut area, first opening Point with a Part II, respectively the Part I, which exposes the substrate edges and its, has distance more than 0 with the substrate edges, should Part II is respectively communicated with the respectively Part I, and the neighbouring mark, but not overlapping with the substrate edges.

In an embodiment, the insulating barrier includes a gate insulator or the heap of the gate insulator and an etch stop layer Repeatedly film layer.

A kind of display panel disclosed in this invention, comprising：

As above any described a kind of image element array substrates；

One opposite substrate；

One frame glue, be arranged between the image element array substrates and the opposite substrate, wherein, the frame glue around the viewing area with A space is formed, and the frame glue is located between first opening and the viewing area；And

One display dielectric layer, it is formed in the space.

In an embodiment, also comprising at least one smooth separation material be arranged at the opposite substrate and the image element array substrates it Between, and corresponding to first opening and place of the substrate edges with the distance more than 0.

Motherboard disclosed in this invention, there is substrate, thin film transistor (TFT), the first signal wire, secondary signal line, pixel electricity Pole, the first conductive pattern and the first protective layer.Substrate has multiple display units, and precut area is defined between display unit, Each display unit includes viewing area and perimeter circuit area, and wherein viewing area has multiple pixel regions.Thin film transistor (TFT) is arranged at base On plate and at least one of pixel region, thin film transistor (TFT) has grid, source electrode, drain electrode, insulating barrier and oxide half Conductor layer, wherein, insulating barrier is between grid and oxide semiconductor layer, and source/drain contacts with oxide semiconductor layer, And insulating barrier is extended in the perimeter circuit area of each display unit.First signal wire is arranged on substrate and positioned at least a portion On pixel region, and connect grid.Secondary signal line is arranged on substrate and at least a portion pixel region, and connects source Pole.Pixel electrode is arranged on substrate and at least a portion pixel region, and connects drain electrode.First conductive pattern is arranged at In the precut area of a part, and a part of first conductive pattern is located in perimeter circuit area, wherein, in perimeter circuit area Insulating barrier is overlapping with the first conductive pattern to form mark, and insulating barrier has the first opening, exposes the inner surface of substrate, and the One opening is avoided marking in perimeter circuit area and around viewing area.First protective layer is formed on substrate, and is formed at In thin film transistor (TFT), mark, the insulating barrier in perimeter circuit area and the first opening, wherein, the dielectric of the first protective layer is normal Number is more than the dielectric constant of insulating barrier, and the dielectric constant of insulating barrier is less than 6, more than 1.

In an embodiment, also it is arranged at comprising one second conductive pattern layer in a part precut area, and a part Second conductive pattern layer is located in the multiple perimeter circuit area, wherein, second conductive pattern layer and first conductive pattern Pattern layer is overlapping, and insulating barrier, first conductive pattern layer in the perimeter circuit area are overlapping with second conductive pattern layer To form the mark.

In an embodiment, the mark is located at four corners in the precut area, and first opening has two first Point with a Part II, respectively the Part I be respectively communicated with the respectively Part I with the precut area overlapping, the Part II, and The neighbouring mark, but do not precut area overlapping with this.

In an embodiment, the mark does not have two first positioned at four corners in the precut area, first opening Part and a Part II, respectively the Part I be respectively communicated with the respectively Part I with the precut area overlapping, the Part II, And the neighbouring mark, but do not precut area overlapping with this.

Display panel motherboard disclosed in this invention includes：

As above any described a kind of motherboard；

One opposite substrate；

One frame glue, it is arranged at respectively between the substrate and the opposite substrate of the display unit, wherein, the frame glue, which is surround, respectively should The viewing area of display unit is to form a space, and the frame glue is located at first opening and the viewing area of the respectively display unit Between；And

One display dielectric layer, it is formed in the space.

In an embodiment, also it is arranged at comprising at least one smooth separation material between the opposite substrate and the substrate, and correspondingly Area is precut in this.

In summary, image element array substrates and its motherboard disclosed in this invention, due to the relatively low material (example of dielectric constant Such as insulating barrier) water-resisting ability it is limited, and the material (the first protective layer) that dielectric constant is higher be suitable for completely cut off external environment Aqueous vapor, and coordinate the relevant design of opening, therefore be not easy to absorb steam during processing and during use, so as to carry High yield and the life-span of image element array substrates and its motherboard.

The above is to demonstrate and explain this hair on the explanation of present invention and the explanation of following embodiment Bright spirit and principle, and the patent claim for providing the present invention is further explained.

Brief description of the drawings

Fig. 1 is the image element array substrates motherboard top view according to one embodiment of the invention.

2A figures correspond to the partial cutaway schematic view of cutting line AA ' in Fig. 1.

2B figures correspond to the partial cutaway schematic view of cutting line BB ' and DD ' in Fig. 1.

2C figures correspond to the partial cutaway schematic view of cutting line CC ' in Fig. 1.

Fig. 3 is the motherboard top view according to another embodiment of the present invention.

Fig. 4 is the partial cutaway schematic view according to Fig. 1 cutting line CC ' in another embodiment of the present invention.

5A figures are the partial cutaway schematic views for corresponding to cutting line AA ' according to the motherboard in yet another embodiment of the invention.

5B figures are the partial cutaway schematic views for corresponding to cutting line BB ' according to the motherboard in yet another embodiment of the invention.

5C figures are the partial cutaway schematic views for corresponding to cutting line CC ' according to the motherboard in yet another embodiment of the invention.

Fig. 6 is the partial cutaway schematic view for corresponding to cutting line CC ' according to the motherboard in another embodiment of the present invention.

Fig. 7 is the partial cutaway schematic view of the panel motherboard according to another embodiment of the present invention.

The motherboard that Fig. 8 is corresponded in Fig. 1 is split obtained image element array substrates top view.

Fig. 9 A correspond to the partial cutaway schematic view of cutting line aa ' in Fig. 8.

Fig. 9 B correspond to the partial cutaway schematic view of cutting line bb ' in Fig. 8.

Fig. 9 C correspond to the partial cutaway schematic view of cutting line cc ' in Fig. 8.

Fig. 9 D correspond to the partial cutaway schematic view of cutting line dd ' in Fig. 8.

Figure 10 is the image element array substrates top view according to another embodiment of the present invention.

Figure 11 is the partial cutaway schematic view according to Fig. 8 cutting line cc ' in another embodiment of the present invention.

Figure 12 A are the cut-away sections for corresponding to cutting line aa ' according to the image element array substrates in yet another embodiment of the invention Schematic diagram.

Figure 12 B are the cut-away sections for corresponding to cutting line bb ' according to the image element array substrates in yet another embodiment of the invention Schematic diagram.

Figure 12 C are the cut-away sections for corresponding to cutting line cc ' according to the image element array substrates in yet another embodiment of the invention Schematic diagram.

Figure 12 D are the cut-away sections for corresponding to cutting line dd ' according to the image element array substrates in yet another embodiment of the invention Schematic diagram.

Figure 13 is shown according to cut-away section of the image element array substrates in another embodiment of the present invention corresponding to cutting line cc ' It is intended to.

Figure 14 is the diagrammatic cross-section of the display panel according to another embodiment of the present invention.

Wherein, description of reference numerals is as follows：

1000 motherboards

1100th, 3100 substrate

1101st, 3101 upper surface

310E edges

1110 display units

1111st, 3111 viewing area

1113rd, 3113 perimeter circuit area

1130 precut areas

1300th, 3300 thin film transistor (TFT)

130G, 330G grid

130S, 330S source electrode

130D, 330D drain

130I, 330I insulating barrier

1400th, 1500,3400,3500 signal wire

1600th, 3600 pixel electrode

1700th, 1710,3700,3710 conductive pattern

1800~1830,3800~3830 openings

1801st, 1803,1807,3801,3803,3807 Part I

1805th, 1809,3805,3809 Part II

380E side walls

1900th, 1910,3900,3910 protective layer

1920th, 3920 dielectric layer

2000 panel motherboards

3000 image element array substrates

4000 display panels

2100th, 4100 opposite substrate

2200th, 4200 frame glue

2300th, 4300 display dielectric layer

2400th, 4400 smooth separation material

AA ', BB ', CC ', DD ' cutting lines

Aa ', bb ', cc ', dd ' cutting lines

Embodiment

The detailed features and advantage of the narration present invention in detail in embodiments below, its content are enough to make any to be familiar with Relevant art understand the present invention technology contents simultaneously implement according to this, and according to content disclosed in this specification, apply for a patent Scope and accompanying drawing, any those of ordinary skill in the art can be readily understood upon the purpose and advantage of correlation of the invention.Following reality It is that the viewpoint of the present invention is further described to apply example, but non-anyways to limit scope of the invention.

Fig. 1 to 2C figures are refer to, wherein Fig. 1 is the image element array substrates motherboard vertical view according to one embodiment of the invention Figure, 2A figures correspond to the partial cutaway schematic view of cutting line AA ' in Fig. 1, and 2B figures correspond to cutting line in Fig. 1 BB ' and DD ' partial cutaway schematic view, 2C figures correspond to the partial cutaway schematic view of cutting line CC ' in Fig. 1.And such as scheme 1st, 2A figure with 2B figures shown in, the motherboard 1000 in one embodiment of the invention has substrate 1100.Substrate 1100 has multiple Display unit 1110, at least one precut area 1130 is defined between display unit.Each display unit 1110 includes one with more The viewing area 1111 of individual pixel region (not indicating) and at least perimeter circuit area 1113 adjacent to viewing area 1111, it is of the invention Embodiment is to implement example, but not limited to this to surround an at least perimeter circuit area 1113 for viewing area 1113.Necessarily say It is bright, it is exactly the image element array substrates or display panel of a display panel after each display unit 1110 is cut.

And as shown in 2A figures, at least part of pixel region (not indicating) in viewing area 1111, in substrate 1100 Upper surface be provided with thin film transistor (TFT) 1300.Have in thin film transistor (TFT) 1300 grid 130G, drain electrode 130D, source electrode 130S, absolutely Edge layer 130I and oxide semiconductor layer 130O.Insulating barrier 130I between grid 130G and oxide semiconductor layer 130O, And source electrode 130S contacts with drain electrode 130D with oxide semiconductor layer 130O, i.e. source electrode 130S all can be with oxide with drain electrode 130D Semiconductor layer 130O partly overlaps, and insulating barrier 130I also extends to the perimeter circuit area 1113 of affiliated display unit 1110, its Middle insulating barrier 130I dielectric constant is less than 6, more than 1.In special embodiment, insulating barrier 130I dielectric constant is less than 5, More than 1.Wherein, insulating barrier 130I material can be silica, carbon Si oxide, silicon oxynitride, carborundum, silicon substrate high score Son, spin-coating glass (SOG) or other suitable materials, and the physical property of previous materials or the property changed see physical security tables of data, And the nitrogen percent of silicon oxynitride will be substantially less than 30% and be more than 0%, oxygen atom is more than the percentage of nitrogen-atoms, and silicon is former Sub- percentage is substantially less than nitrogen and oxygen atom summation, and nitrogen is less than 67% with oxygen atom summation and is more than 62%, wherein, nitrogen, oxygen, Silicon atom summation is 100%, and the refractive index of silicon oxynitride is more than 1.45 and is less than 1.75, and its manufacture method can be chemical gaseous phase Depositing method, sputtering method or other suitable methods.The present invention using insulating barrier 130I material be silica as example, it is but unlimited In this.In some embodiments, there was only gate insulator in insulating barrier 130I, and in other embodiments, insulating barrier 130I Stacked and formed by multi-layer insulation, such as insulating barrier 130I is to stack film layer structure by gate insulator and etch stop layer Into.Although in the present embodiment, grid 130G is located under oxide semiconductor layer 130O, i.e., bottom lock type thin film transistor (TFT) is model Example, but not limited to this.In other embodiments, grid 130G also positioned at the upper of oxide semiconductor layer 130O, that is, it is thin to push up lock type Film transistor, or grid 130G are located in oxide semiconductor layer 130O other positions, i.e., other types of thin film transistor (TFT) Also it is applicatory.Oxide semiconductor can be single or multiple lift structure, and its material includes indium gallium zinc oxide (IGZO), indium zinc Oxide (IZO), indium gallium oxide (IGO), tin oxide (ZnO), cadmium oxide germanium oxide (CdO2.GeO2), cobalt nickel oxide (NiCo2O4), zinc oxide (ZnO), aluminium zinc oxide (AZO), gallium zinc oxide (GZO) or other suitable materials.

In addition, in being additionally provided with the first signal wire 1400, secondary signal line 1500 and pixel electrode on thin film transistor (TFT) 1300 1600.First signal wire 1400 is connected to grid 130G, then the first signal wire 1400 can be considered scan line or gate line, the second letter Number line 1500 is connected to source electrode 130S, then secondary signal line 1500 can be considered data wire, and pixel electrode 1600 is connected to drain electrode 130D.Wherein, the first signal wire 1400, secondary signal line 1500 are all briefly to describe with pixel electrode 1600.In addition, in base There is the first conductive pattern 1700 on plate 1100, the first conductive pattern 1700 is arranged at the precut area 1130 of a part, and part The first conductive pattern 1700 be located at perimeter circuit area 1113, wherein, positioned at the insulating barrier 130I in perimeter circuit area 1113 and One conductive pattern, the 1700 overlapping mark M with pie graph 1.Insulating barrier 130I has the first opening 1800, the portion of substrate 1100 Point upper surface 1101 (or can be described as inner surface) is exposed via the first opening 1800, and the first opening 1800 is located at perimeter line In road area 1113 and around viewing area 1111, and avoid marking M.Although in diagram, the covering insulation of the first conductive pattern 1700 Layer 130I, but the first conductive pattern 1700 can also be covered by insulating barrier 130I, the present invention is not any limitation as.

Also the first protective layer 1900, is formed on substrate 1100, and is formed at thin film transistor (TFT) 1300, mark M, is located at In the openings of the insulating barrier 130I in perimeter circuit area 1113 and first 1800.The dielectric constant of first protective layer 1900 is more than insulating barrier 130I dielectric constant.Wherein, the material of the first protective layer 1900 can be silicon nitride, silicon oxynitride, tantalum oxide (tantalum Oxide), aluminum oxide, titanium oxide, hafnium oxide (HfO) or other suitable materials, and the physical property of previous materials or the property changed see Physical security tables of data, and the nitrogen percent of silicon oxynitride will be substantially greater than and be equal to 30% less than 58%, oxygen atom is small In nitrogen-atoms percentage and more than 0%, atomic percent silicon is substantially less than nitrogen and oxygen atom percentage summation, and nitrogen and oxygen Atomic percent summation is less than or equal to 62% and is more than 57%, wherein, nitrogen, oxygen, silicon atom summation are 100%, and silicon oxynitride Refractive index is more than or equal to 1.75 and is less than 2.0, and its manufacture method can be chemical gaseous phase depositing method, sputtering method or other suitable sides Method.The present invention using the material of the first protective layer 1900 be silicon nitride as example, but not limited to this.Therefore, as illustrated in fig. 2b, in In the partial cutaway schematic view corresponding to cutting line BB ' at precut area 1130, the first protective layer 1900 on substrate 1100 It is in contact at insulating barrier 130I the first opening 1800 with substrate 1100, and the part beyond the first opening 1800, first Protective layer 1900 does not contact the upper surface of substrate 1100.

And as shown in 2C figures, in mark M at cutting line CC ' corresponding to partial cutaway schematic view in, substrate 1100 On have the first conductive pattern 1700, and insulating barrier 130I thereon.In on insulating barrier 130I covered with the first protective layer 1900。

In some embodiments, Fig. 1 is gone back to, mark M is located around the four of the precut area 1130 of display unit 1110 Individual corner, then the first opening at every nook and cranny 1800 there is two Part I 1801,1803 and a Part II 1805th, each Part I is overlapping with precut area 1130, and Part II 1805 is respectively communicated with Part I 1801 and Part I 1803, and the neighbouring mark M of Part II 1805, but not overlapping with precut area 1130, can be considered Part II 1805 not with mark Remember M connections.In the present embodiment, mark M can be used as contraposition and/or cut mark, and mark M projection of shape to be essentially ten Font is example, but not limited to this.In other embodiments, the projection of shape for marking M can be L-shaped, T-shaped or other suitable throwings Shadow shape.

In another embodiment, Fig. 3 is refer to, it is the motherboard top view according to another embodiment of the present invention.Such as Fig. 3 institutes Show, the embodiment compared to Fig. 1, the mark M of the present embodiment can be located at four not positioned at four corners in precut area 1130 Position outside corner, and the first opening 1800 has two Part I 1801,1807 and a Part II 1809, each the A part 1801,1807 is overlapping with precut area 1130, and Part II 1809 is respectively communicated with Part I 1801 and Part I 1807, and neighbouring mark M, but it is not overlapping with precut area 1130, it can be considered that Part II 1809 does not connect with mark M.And Fig. 3 Shown in hatching AA ', BB ', CC ', DD ' and EE ' cross-section structure see Fig. 2A~2C and Fig. 4~7.It is assuming that each aobvious Show that unit 1110 has multiple sides, then there can be the mark M shown at least one Fig. 3 on each side.In the present embodiment, mark M can be used as contraposition and/or cut mark, and mark M projection of shape using be essentially linear as example, but not limited to this, For example, mark M projection of shape can be curve or other suitable projection of shape.Figure can be also included in other embodiments, Fig. 3 Mark M shown in 1, then all there is mark to strengthen the effect for aligning and/or cutting again in corner and non-corner.Similarly, in Fig. 1 Also the mark M shown in Fig. 3 can be included, then all has mark to strengthen the effect for aligning and/or cutting again in corner and non-corner.

In another embodiment, Fig. 4 is refer to, it is the portion according to Fig. 1 cutting line CC ' in another embodiment of the present invention Divide diagrammatic cross-section.As shown in figure 4, in the present embodiment, in the cut-away section structure of mark M positions, scheme with 2C The difference of embodiment be that the motherboard 1000 in the present embodiment has more the second conductive pattern 1710.Second conductive pattern 1710 are arranged at the precut area 1130 of part, and the second conductive pattern of part 1710 is located at perimeter circuit area 1113.Second leads Electrical pattern 1710 is overlapping with the first conductive pattern 1700, and it is by the insulating barrier 130I positioned at perimeter circuit area 1113, to mark M One conductive pattern 1700 is overlapping with the second conductive pattern 1710 and forms.And in the part for marking M, insulating barrier 130I is located in Between first conductive pattern 1700 and the second conductive pattern 1710.

In another embodiment, 5A figures are refer to 5C figures, wherein 5A figures are according to yet another embodiment of the invention In motherboard correspond to cutting line AA ' partial cutaway schematic view, and 5B figures are according to the mother in yet another embodiment of the invention Plate corresponds to cutting line BB ' partial cutaway schematic view, and 5C figures are corresponded to according to the motherboard in yet another embodiment of the invention Cutting line CC ' partial cutaway schematic view.As shown in 5A figures, 5B figures and 5C figures, the motherboard 1000 in the present embodiment For embodiment compared to 2A figures to 2C figures, with more the second protective layer 1910, the second protective layer 1910 is formed at base Plate 1100 it is upper, and be formed at thin film transistor (TFT) 1300, mark M with positioned at perimeter circuit area 1113 insulating barrier 130I on, its In, the second protective layer 1910 is located between insulating barrier 130I and the first protective layer 1900, second protective layer 1910 have pair Should in first opening 1800 second opening 1810, with expose the portion of upper surface 1101 of substrate 1100 (can be described as inner surface, Because the remainder of the upper surface 1101 of substrate 1100 is to be covered by each material layer without exposed), and the first protective layer 1900 are formed at thin film transistor (TFT) 1300, mark M, the insulating barrier 130I in perimeter circuit area 1113, the second protective layer 1910th, in the first opening 1800 and the second opening 1810.In addition, the dielectric constant of the first protective layer 1900 can be more than the second protection The dielectric constant of layer 1910.For example, the dielectric constant of the second protective layer 1910 is optionally less than 6 and is more than 1, and the Two protective layers 1910 may be selected from the material or other suitable materials described in insulating barrier 130I.

In addition, scheming referring again to 5A figures to 5C, the motherboard 1000 in some embodiments can have more dielectric layer 1920, and dielectric layer 1920 can then be not present in other embodiments.Dielectric layer 1920 is formed on substrate 1100, and shape Into in thin film transistor (TFT) 1300, mark M and on the insulating barrier 130I in perimeter circuit area 1113.Wherein, dielectric layer 1920 presss from both sides Between the second protective layer 1910 and the first protective layer 1900, dielectric layer 1920 has correspond to the second opening 1810 the 3rd Opening 1820, to expose the portion of upper surface 1101 of substrate 1100, and the first protective layer 1900 is formed at thin film transistor (TFT) 1300th, M, the insulating barrier 130I positioned at perimeter circuit area 1113, the second protective layer 1910, dielectric layer 1920, first is marked to be open 1800th, in the second opening 1810 and the 3rd opening 1820.

In another embodiment, Fig. 6 is refer to, it is to correspond to cutting line according to the motherboard in another embodiment of the present invention CC ' partial cutaway schematic view.As shown in fig. 6, compared to the embodiment of 5C figures, the dielectric layer 1920 of the present embodiment has the Four openings 1830.Positioned at mark M top, the first protective layer 1900 is formed in the 4th opening 1,830 4th opening 1830, and The alternative of 4th opening 1830 does not connect with first opening the 1800, second opening 1810 and the 3rd opening 1820.In other realities Apply in example, the 4th opening 1830 can connect with first opening the 1800, second opening 1810 and the 3rd opening 1820.Open due to the 4th Mouthfuls 1830 presence, high low head between mark M and precut area 1130 compared to 2A to the embodiment of 2C figures and Speech is smaller, so that cutting motherboard can improve to produce the yield of image element array substrates, and can strengthen aqueous vapor obstructing capacity, To lift display panel reliability.

In another embodiment, with the panel motherboard of foregoing motherboard making, Fig. 7 is refer to, it is another according to the present invention The partial cutaway schematic view of the panel motherboard of one embodiment.Refer to shown in Fig. 7 and Fig. 1 or Figure 14 and Fig. 3, panel motherboard 2000 In just like the motherboard 1000 of foregoing any embodiment, opposite substrate 2100, frame glue 2200, display dielectric layer 2300 and light separation material 2400.Wherein frame glue 2200 is arranged at substrate 1100 and opposite substrate corresponding to each display unit 1110 on motherboard 1000 Between 2100.Frame glue 2200 is between the first opening 1800 and the viewing area 1111 of each display unit 1110, the ring of frame glue 2200 Around the viewing area 1111 of each display unit 1110 with Special composition (space), there is display dielectric layer 2300 in being filled out in this space.Light Separation material (photo spacer) 2400 is arranged between opposite substrate 2100 and substrate 1100, and corresponding at least one of Precut area 1130.The thickness of light separation material 2400 is optionally less than or the substantially equal to thickness of display dielectric layer 2300 Degree, and light separation material 2400 can more improve the appropriate rate of cutting substrate again.In other words, in the present embodiment, area is precut 1130 can pass through 1800 (such as two Part I 1801 and 1805 or 1801 and 1807) of opening of mark M and partial first, Then light separation material 2400 can be stored on the position corresponding at least a portion mark M, and is arranged at the opposite substrate and the substrate Between；Either light separation material 2400 can be stored in (such as two Hes of Part I 1801 of the first opening 1800 corresponding to part 1805 or 1801 and position 1807) on, and be arranged between the opposite substrate and the substrate；Either light separation material 2400 can Be stored in corresponding at least a portion mark M and partial first opening 1800 (such as two Part I 1801 and 1805 or 1801 and position 1807) on, and be arranged between the opposite substrate and the substrate.Furthermore above-mentioned Fig. 5 B, 5C and/or Fig. 6 institute The profile stated, also optionally comprising the light separation material 2400 and its associated description described in Fig. 7, and what can be will be apparent that understands Relative position with it is supporting pass be.But in some embodiments, less influence to cut appropriate rate if the program of cutting motherboard is suitable, Then can correspond on the position in precut area 1130 that light separation material 2400 is not present.It must be noted that each display is single It is exactly the image element array substrates or display panel of a display panel after member 1110 is cut.

Therefore, when motherboard 1000 cuts multiple image element array substrates to obtain, single individual image element array substrates are bowed The diagrammatic cross-section of view and each several part refer to Fig. 8 to Fig. 9 D, and the motherboard that wherein Fig. 8 is corresponded in Fig. 1 is split to obtain Single individual image element array substrates top view, Fig. 9 A correspond to the partial cutaway schematic view of cutting line aa ' in Fig. 8, and Fig. 9 B The partial cutaway schematic view of cutting line bb ' in Fig. 8 is corresponded to, the cut-away section that Fig. 9 C correspond to cutting line cc ' in Fig. 8 shows It is intended to, and Fig. 9 D correspond to the partial cutaway schematic view of cutting line dd ' in Fig. 8.

As shown in Fig. 8, Fig. 9 A and Fig. 9 B, the image element array substrates 3000 in one embodiment of the invention have substrate 3100. Include a viewing area 3111 with multiple pixels (not indicating) and at least one week adjacent to viewing area 3111 on substrate 3100 Side line areas 3113, embodiments of the invention are to surround an at least perimeter circuit area 3113 for viewing area 3113 to implement model Example, but not limited to this.Each display unit 1110 must be noted that from motherboard (such as Fig. 1 motherboard 1100) along pre- After cutting area (such as Fig. 1 precut area 1130) is cut, it is exactly the image element array substrates of a display panel, then shows The edge for showing image element array substrates is exactly precut area.

As shown in Figure 9 A, at least part of pixel region in viewing area 3111 (not indicating), in the upper of substrate 3100 Surface is provided with thin film transistor (TFT) 3300.There are grid 330G, drain electrode 330D, source electrode 330S, insulating barrier in thin film transistor (TFT) 3300 330I and oxide semiconductor layer 330O.Insulating barrier 330I is between grid 330G and oxide semiconductor layer 330O, and source Pole 330S is contacted with drain electrode 330D with oxide semiconductor layer 330O, i.e. source electrode 330S all can partly be led with drain electrode 330D with oxide Body layer 330O partly overlaps, and insulating barrier 330I also extends to the dielectric constant in perimeter circuit area 3113, wherein insulating barrier 330I Less than 6, more than 1.In special embodiment, insulating barrier 330I dielectric constant is less than 5, more than 1.Wherein, insulating barrier 330I Material may be selected from the material of the insulating barrier 130I in above-described embodiment.In some embodiments, there was only grid in insulating barrier 330I Pole insulating barrier, and in other embodiments, insulating barrier 330I is stacked by multi-layer insulation and formed, such as insulating barrier 330I is It is made up of the film layer that stacks of gate insulator and etch stop layer.Although in the present embodiment, grid 330G is located at oxide half Under conductor layer 330O, i.e. bottom lock type thin film transistor (TFT) is example, but not limited to this.In other embodiments, grid 330G is also Positioned at the upper of oxide semiconductor layer 330O, that is, lock type thin film transistor (TFT) is pushed up, or grid 330G is located at oxide semiconductor layer In 330O other positions, i.e., other types of thin film transistor (TFT) is also applicatory.Wherein oxide semiconductor layer 330O can be single Layer or sandwich construction, and its material is selected from the material described in oxide semiconductor layer 130O in above-described embodiment.

In addition, in being additionally provided with the first signal wire 3400, secondary signal line 3500 and pixel electrode on thin film transistor (TFT) 3300 3600.First signal wire 3400 is connected to grid 330G, then the first signal wire 3400 can be considered scan line or gate line, the second letter Number line 3500 is connected to source electrode 330S, then secondary signal line 3500 can be considered data wire, and pixel electrode 3600 is connected to drain electrode 330D.Wherein, the first signal wire 3400, secondary signal line 3500 are all briefly to describe with pixel electrode 3600.In addition, in base There is the first conductive pattern 3700 on plate 3100, the first conductive pattern 3700 is arranged at perimeter circuit area 3113 and adjacent substrates 3100 edge (or being side or side wall) 310E, wherein, the insulating barrier 330I positioned at perimeter circuit area 3113 is led with first The overlapping mark m with pie graph 8 of electrical pattern 3700.Insulating barrier 330I has the first opening 3800, on the part of substrate 3100 Surface 3101 (or can be described as inner surface) is exposed via the first opening 3800, and the first opening 3800 is located at perimeter circuit area On 3113 and around viewing area 3111, and avoid marking m.Although in diagram, the first conductive pattern 3700 covering insulating barrier 330I, but the first conductive pattern 3700 can also be covered by insulating barrier 330I, the present invention is not any limitation as.

Also the first protective layer 3900, is formed on substrate 3100, and is formed at thin film transistor (TFT) 3300, mark m, is located at In the openings of the insulating barrier 330I in perimeter circuit area 3113 and first 3800.The dielectric constant of first protective layer 3900 is more than insulating barrier 330I dielectric constant.Wherein, the material of the first protective layer 3900 may be selected from the first protective layer described in previous embodiment 1900 material.Therefore, as shown in Figure 9 B, the cut-away section corresponding to the cutting line bb ' in the edge 310E of substrate 3100 shows In intention, the first protective layer 3900 on substrate 3100 connects at insulating barrier 330I the first opening 3800 with substrate 3100 Touch, and the part beyond the first opening 3800, the first protective layer 3900 do not contact the upper surface of substrate 3100.

And as shown in Figure 9 C, in mark m at cutting line cc ' corresponding to partial cutaway schematic view in, on substrate 3100 There are the first conductive pattern 3700, and insulating barrier 330I thereon.In on insulating barrier 330I covered with the first protective layer 3900.

In some embodiments, Fig. 8 is gone back to, mark m is located at four corners of image element array substrates 3000, the first opening 3800 at least have two Part I 3801,3803 and a Part II 3805, each Part I adjacent substrates 3100 Edge 310E, Part II 3805 are respectively communicated with Part I 3801 and Part I 3803, and the neighbouring mark of Part II 3805 Remember m, but be not adjacent to the edge 310E of substrate 3100.Now, Part II 3805 does not connect with mark m, and the mark after cutting The projection of shape for remembering m can be L-type or other suitable shapes.Wherein, the side wall 380E of each Part I and the edge of substrate When 310E is projected on a plane, both (i.e. side wall 380E and the edge 310E of substrate and first of Part I 3801 The side wall 380E of the part 3083 and edge 310E of substrate) the distance between d be more than 0.

And as shown in fig. 9d, in mark m by first opening 3800 Part II 3805 at cutting line dd ' corresponding to In partial cutaway schematic view.In the partial cutaway schematic view corresponding to cutting line bb ', the first protective layer on substrate 3100 3900 covering insulating barrier 330I, and the side wall of the first opening 3800 is covered, the upper surface of substrate 3100 is extended over always 3101 at edge 310E.By first opening 3800, the relatively low insulating barrier 330I of dielectric constant because by dielectric constant compared with The first high protective layer 3900 coats, and can't be directly exposed in air.Although at mark m, that is, cutting line cc ' places Insulating barrier 330I can be exposed to air, but by the Part II 3805 of the first opening 3800, left side (Fig. 8 in Fig. 9 D Part of the middle dd ' cutting lines away from mark m) insulating barrier 330I and right side (dd ' cutting lines are close to mark m part in Fig. 8) Insulating barrier 330I can't be connected.Therefore even if the insulating barrier 330I close to mark m absorbs the aqueous vapor in air, close to aobvious Aqueous vapor can't be absorbed to by showing the insulating barrier 330I in area, so that the probability that aqueous vapor influences the element of viewing area declines, be extended Life-span of panel.Similarly, the first opening 1800 in previous embodiment image element array substrates and its motherboard on relevant position, leads to The first opening 1800 is crossed, the relatively low insulating barrier 130I of dielectric constant by the first higher protective layer 1900 of dielectric constant because wrapped Cover, can't be directly exposed to after dicing in air to absorb aqueous vapor, so that aqueous vapor influences the machine of the element of viewing area Rate declines, and extends the life-span of panel.

In another embodiment, Figure 10 is refer to, it is the image element array substrates vertical view according to another embodiment of the present invention Figure.As shown in Figure 10, the embodiment compared to Fig. 8, the mark m of the present embodiment are not located at four angles of image element array substrates 3000 Fall, and the position outside four corners can be located at, and the first opening 3800 at least has two Part I 3801,3807 and the Two parts 3809, each Part I are adjacent to edge 310E, and Part II 3809 is respectively communicated with Part I 3801 and first Divide 3807, and neighbouring mark m, but be not adjacent to edge 310E, can be considered that Part II 3809 does not connect with mark m.It is assuming that every Individual display unit 1110 has multiple sides, then can have the mark m shown at least one Figure 10 on each side, and mark m throwing Shadow shape using be essentially linear as example, but not limited to this, for example, mark m projection of shape can be curve or other conjunctions Suitable projection of shape.The mark m shown in Fig. 8 can be also included in other embodiments, Figure 10.Similarly, Figure 10 can be also included in Fig. 8 Shown mark m, then all there is mark m in corner and non-corner.Wherein, the edge 310E of the side wall of each Part I and substrate When being projected on a plane, both (i.e. edge 310E and Part I 3087 of the side wall of Part I 3081 and substrate Side wall and substrate edge 310E) the distance between d ' be more than 0, and hatching aa ', bb ', cc ', dd ' shown in Figure 10 Fig. 9 A~9D and Figure 11~14 are see with ee ' cross-section structure.It is more than 0 by distance d or d ', it is ensured that the face cut In plate, insulating barrier 330I can't be directly exposed to air, between insulating barrier 330I and air, necessarily there is the first protective layer Insulating barrier 330I is isolated from air by 3900.

In another embodiment, Figure 11 is refer to, it is the cutting line cc ' according to Fig. 8 in another embodiment of the present invention Partial cutaway schematic view.As shown in figure 11, in the present embodiment, in the cut-away section structure of mark m positions, with Fig. 9 C The difference of embodiment be that the image element array substrates 3000 in the present embodiment have more the second conductive pattern 3710.Partial Second conductive pattern 3710 is located at perimeter circuit area 3113.Second conductive pattern 3710 is overlapping with the first conductive pattern 3700, and It is by the insulating barrier 330I positioned at perimeter circuit area 3113, the first conductive pattern 3700 and the weight of the second conductive pattern 3710 to mark m Fold and form.And in the part for marking m, insulating barrier 330I is located in the first conductive pattern 3700 and the second conductive pattern 3710 Between.

In another embodiment, Figure 12 A to Figure 12 D are refer to, wherein Figure 12 A are according in yet another embodiment of the invention Image element array substrates correspond to cutting line aa ' partial cutaway schematic view, and Figure 12 B are according in yet another embodiment of the invention Image element array substrates correspond to cutting line bb ' partial cutaway schematic view, and Figure 12 C are according to the picture in yet another embodiment of the invention Pixel array substrate corresponds to cutting line cc ' partial cutaway schematic view, and Figure 12 D are according to the pixel in yet another embodiment of the invention Array base palte corresponds to cutting line dd ' partial cutaway schematic view.As shown in Figure 12 A to Figure 12 D, the motherboard in the present embodiment For 3000 embodiment compared to Fig. 9 A to Fig. 9 D, with more the second protective layer 3910, the second protective layer 3910 is formed at base Plate 3100 it is upper, and be formed at thin film transistor (TFT) 3300, mark m with positioned at perimeter circuit area 3113 insulating barrier 330I on, its In, the second protective layer 3910 is located between insulating barrier 330I and the first protective layer 3900, and the second protective layer 3910 has corresponding In first opening 3800 second opening 3810, with expose the portion of upper surface 3101 of substrate 3100 (can be described as inner surface, because Remainder by the upper surface 3101 of substrate 3100 is to be covered by each material layer without exposed), and the first protective layer 3900 It is formed at thin film transistor (TFT) 3300, mark m, the insulating barrier 330I in perimeter circuit area 3113, the second protective layer 3910, the In one opening 3800 and the second opening 3810.In addition, the dielectric constant of the first protective layer 3900 can be more than the second protective layer 3910 Dielectric constant.For example the dielectric constant of the second protective layer 3910 is optionally less than 6 more than 1, and its material is optional From the insulating barrier in above-described embodiment or other suitable materials.

In addition, referring again to Figure 12 A to Figure 12 D, the image element array substrates 3000 in some embodiments can have more Dielectric layer 3920, and dielectric layer 3920 can then be not present in other embodiments.Dielectric layer 3920 is formed at substrate 3100 On, and thin film transistor (TFT) 3300, mark m are formed at being located on the insulating barrier 330I in perimeter circuit area 3113.Wherein, dielectric layer 3920 are located between the second protective layer 3910 and the first protective layer 3900, and dielectric layer 3920, which has, corresponds to the second opening 3810 The 3rd opening 3820, to expose the portion of upper surface 3101 of substrate 3100, and the first protective layer 3900 is formed at film crystalline substance Body pipe 3300, mark m, the insulating barrier 330I positioned at perimeter circuit area 3113, the second protective layer 3910, dielectric layer 3920, first In the opening 3820 of the opening of opening 3800, second 3810 and the 3rd.

In another embodiment, Figure 13 is refer to, it is according to the image element array substrates pair in another embodiment of the present invention Should be in cutting line cc ' partial cutaway schematic view.As shown in figure 13, compared to Figure 12 C embodiment, the dielectric layer of the present embodiment 3920 have the 4th opening 3830.For 4th opening 3830 positioned at mark m top, the first protective layer 3900 is formed at the 4th opening On 3830, and the alternative of the 4th opening 3830 does not connect with first opening the 3800, second opening 3810 and the 3rd opening 3820. In other embodiments, the 4th opening 3830 can connect with first opening the 3800, second opening 3810 and the 3rd opening 3820.

In another embodiment, with the display panel of foregoing image element array substrates making, Figure 14 is refer to, it is foundation The diagrammatic cross-section of the display panel of another embodiment of the present invention.Refer to shown in Figure 14 and Fig. 8 or Figure 14 and Figure 10, display surface Just like the image element array substrates 3000 of foregoing any embodiment, opposite substrate 4100, frame glue 4200, display dielectric layer in plate 4000 4300 with light separation material 4400.Wherein frame glue 4200 is arranged between image element array substrates 3000 and opposite substrate 4100.Frame glue 4200 between the first opening 3800 and viewing area 3111, frame glue 4200 around viewing area 3111 with Special composition (space), There is display dielectric layer 4300 in being filled out in this space.Light separation material (photo spacer) 4400 is arranged at opposite substrate 4100 and picture Between pixel array substrate 3000, and the region corresponded between the side wall of the first opening 3800 and the edge 310E of substrate 3100, And the thickness of light separation material 4400 is optionally less than or the substantially equal to thickness of display dielectric layer 4300.In the present embodiment In, light separation material 4400 can be stored on the position corresponding at least a portion mark m, and is arranged at the opposite substrate and the substrate Between；Either light separation material 4400 can be stored in (such as two Hes of Part I 3801 of the first opening 3800 corresponding to part 3805 or 3801 and position 3807) on, and be arranged between the opposite substrate and the substrate；Either light separation material 4400 can Be stored in corresponding at least a portion mark m and partial first opening 3800 (such as two Part I 3801 and 3805 or 3801 and position 3807) on, and be arranged between the opposite substrate and the substrate.Furthermore above-mentioned Figure 12 B, 12C and/or figure Profile described in 13, also optionally comprising the light separation material 4400 and its associated description described in Figure 14, and it can will be apparent that Understand relative position with it is supporting pass be.But in some embodiments, the suitable less influence cutting of program for cutting motherboard is appropriate Kind rate, then light separation material 4400 is not present on the position in the precut area that can correspond to motherboard.

As the image element array substrates and its motherboard disclosed in aforesaid plurality of embodiment, due in the precut portion of area of motherboard Point, there is opening directly to expose substrate, and opening and substrate are directly covered in herein by the first protective layer, and opening is also avoided marking Note.Therefore when cutting motherboard obtains image element array substrates, only the first protective layer and the substrate of air are directly exposed to.Change sentence Talk about, remaining each layer, each element are protected by the first protective layer and completely cut off air.Due to the first protective layer dielectric constant compared with Height, aqueous vapor are easily barred from outside the first protective layer by the first protective layer, therefore the layers of material within the first protective layer is not easy Aqueous vapor is absorbed, so that wherein oxide semiconductor is because absorbing moisture from degrading probability reduces.Furthermore the face after cutting Although there are the insulating barrier or other dielectric layers of the dielectric constant more relatively low than the first protective layer, and water in plate, its region where marking Gas may transmit from the side of the dielectric layer of relatively low dielectric constant, however the mark after cutting there are at frame glue as The opening (such as Fig. 7, Figure 14 etc.) of aforementioned structure can effectively stop aqueous vapor from the side of the dielectric layer of relatively low dielectric constant Side enters in oxide semiconductor.In other words, in viewing area have compared with low-k each layer (such as insulating barrier) because To isolate from air by opening and the first protective layer, therefore the multiple layer can't be exposed in air, also therefore its absorption Aqueous vapor and the probability that deteriorates declines, lifted so as to the life-span of panel with yield.

Although the present invention is disclosed as above with foregoing embodiment, so it is not limited to the present invention.This hair is not being departed from In bright spirit and scope, carried out by change and retouching, belong to the present invention scope of patent protection.Defined on the present invention Protection domain refer to appended claim.

Claims

1. a kind of motherboard, comprising：

One substrate, there are multiple display units, at least one precut area, the respectively display are defined between the multiple display unit Unit includes a viewing area and an at least perimeter circuit area with multiple pixel regions；

An at least thin film transistor (TFT), set on the substrate and on the multiple pixel region of at least a portion, the film crystal Pipe has a grid, a source electrode, a drain electrode, an insulating barrier and monoxide semiconductor layer, wherein, the insulating barrier is located at the grid Between the oxide semiconductor layer, and the source/drain is contacted with the oxide semiconductor layer, and the insulating barrier is extended to and respectively should In the perimeter circuit area of display unit；

At least one first signal wire, it is arranged on the substrate and on the multiple pixel region of at least a portion, and connects and be somebody's turn to do Grid；

An at least secondary signal line, it is arranged on the substrate and on the multiple pixel region of at least a portion, and connects and be somebody's turn to do Source electrode；

An at least pixel electrode, it is arranged on the substrate and on the multiple pixel region of at least a portion, and connects the leakage Pole；

One first conductive pattern, it is arranged in a part precut area, and a part of first conductive pattern is positioned at described more In individual perimeter circuit area, wherein, the insulating barrier in the perimeter circuit area is overlapping with first conductive pattern to form one Mark, the insulating barrier have one first opening, expose the inner surface of the substrate, and first opening is located at the perimeter circuit area Above and around the viewing area, and avoid the mark；And

At least one first protective layer, is formed on the substrate, and is formed at the thin film transistor (TFT), the mark, positioned at the perimeter line On insulating barrier and first opening in the area of road, wherein, the dielectric constant of first protective layer is more than the dielectric of the insulating barrier Constant, and the dielectric constant of the insulating barrier is less than 6, more than 1.

2. motherboard as claimed in claim 1, it is characterised in that being also arranged at a part comprising one second conductive pattern layer, this is pre- On cutting area, and a part of second conductive pattern layer is located in the multiple perimeter circuit area, wherein, second conductive pattern Layer is overlapping with first conductive pattern layer, the insulating barrier, first conductive pattern layer in the perimeter circuit area and this Two conductive pattern layers are overlapping to form the mark.

3. motherboard as claimed in claim 2, it is characterised in that the insulating barrier in the markers is located in first conductive pattern Between layer and second conductive pattern layer.

4. motherboard as claimed in claim 2, it is characterised in that also comprising one second protective layer, it is formed on the substrate, and shape Into in the thin film transistor (TFT), the mark with the insulating barrier in the perimeter circuit area, wherein, the second protective layer sandwiched Between the insulating barrier and first protective layer, there is second protective layer one second opening to correspond to first opening, with sudden and violent Expose the inner surface of the substrate, and first protective layer forms the thin film transistor (TFT), the mark, in the perimeter circuit area In the insulating barrier, second protective layer, first opening and second opening.

5. motherboard as claimed in claim 4, it is characterised in that the dielectric constant of first protective layer is more than second protective layer Dielectric constant, and the dielectric constant of the dielectric constant of second protective layer and the insulating barrier is less than 6, more than 1.

6. motherboard as claimed in claim 4, it is characterised in that also comprising a dielectric layer, be formed on the substrate, and be formed at The thin film transistor (TFT), the mark with the insulating barrier in the perimeter circuit area, wherein, the dielectric layer be located in this second Between protective layer and first protective layer, there is second protective layer one the 3rd opening to correspond to second opening, to expose The inner surface of the substrate, and first protective layer formed the thin film transistor (TFT), the mark, in the perimeter circuit area this is exhausted In edge layer, second protective layer, first opening, second opening and the 3rd opening.

7. motherboard as claimed in claim 6, it is characterised in that the dielectric layer has one the 4th opening, positioned at the upper of the mark Side, first protective layer are formed in the 4th opening, and the 4th opening not with first opening, second opening and this Three open communications.

8. the motherboard as described in claim 1~7 is any, it is characterised in that the dielectric constant of the insulating barrier is less than 5, more than 1.

9. the motherboard as described in claim 1~7 is any, it is characterised in that the mark is located at four corners in the precut area, First opening has two Part I and a Part II, respectively the Part I and the precut area overlapping, this second The respectively Part I, and the neighbouring mark are respectively communicated with, but does not precut area overlapping with this.

10. the motherboard as described in claim 1~7 is any, it is characterised in that the mark is not positioned at four angles in the precut area Fall, first opening has two Part I and a Part II, respectively the Part I and the precut area overlapping, and this second Part is respectively communicated with the respectively Part I, and the neighbouring mark, but does not precut area overlapping with this.

11. the motherboard as described in claim 1~7 is any, it is characterised in that the insulating barrier includes a gate insulator or the grid Pole insulating barrier and an etch stop layer stack film layer.

12. a kind of display panel motherboard, comprising：

A kind of motherboard as described in claim 1~7 is any；

One opposite substrate；

One frame glue, it is arranged at respectively between the substrate and the opposite substrate of the display unit, wherein, the frame glue is around the respectively display The viewing area of unit to form a space, and the frame glue be located at first opening and the respectively display unit the viewing area it Between；And

One display dielectric layer, it is formed in the space.

13. display panel motherboard as claimed in claim 12, it is characterised in that be also arranged at this comprising at least one smooth separation material Between opposite substrate and the substrate, and corresponding to the precut area.

14. a kind of image element array substrates, comprising：

One substrate, include a viewing area and an at least perimeter circuit area with multiple pixel regions；

An at least thin film transistor (TFT), set on the substrate and on the multiple pixel region of at least a portion, the film crystal Pipe has a grid, a source electrode, a drain electrode, an insulating barrier and monoxide semiconductor layer, wherein, the insulating barrier is located at the grid Between the oxide semiconductor layer, and the source/drain contacts with the oxide semiconductor layer, and the insulating barrier extends to this week On the line areas of side；

One first conductive pattern, it is arranged in the multiple perimeter circuit area and adjacent to the edge of the substrate, wherein, positioned at this week The insulating barrier on the line areas of side is overlapping with first conductive pattern layer to form a mark, and the insulating barrier has one first to open Mouth, the inner surface of the substrate is exposed, and first opening in the perimeter circuit area and surround the viewing area, and avoid this Mark；And

15. image element array substrates as claimed in claim 14, it is characterised in that be also arranged at comprising one second conductive pattern layer In the multiple perimeter circuit area, wherein, second conductive pattern layer is overlapping with first conductive pattern layer, and is located at the periphery The insulating barrier, first conductive pattern layer on line areas are overlapping with second conductive pattern layer to form the mark.

16. image element array substrates as claimed in claim 15, it is characterised in that the insulating barrier in the markers be located in this Between one conductive pattern layer and second conductive pattern layer.

17. image element array substrates as claimed in claim 15, it is characterised in that also comprising one second protective layer, be formed at this On substrate, and be formed at the thin film transistor (TFT), the mark with the insulating barrier in the perimeter circuit area, wherein, this Two protective layers are located between the insulating barrier and first protective layer, second protective layer have one second opening correspond to this One opening, to expose the inner surface of the substrate, and first protective layer forms the thin film transistor (TFT), the mark, positioned at this week On insulating barrier, second protective layer, first opening and second opening on the line areas of side.

18. image element array substrates as claimed in claim 17, it is characterised in that the dielectric constant of first protective layer is more than should The dielectric constant of second protective layer, and the dielectric constant of the dielectric constant of second protective layer and the insulating barrier is less than 6, more than 1.

19. image element array substrates as claimed in claim 17, it is characterised in that also comprising a dielectric layer, be formed at the substrate On, and be formed at the thin film transistor (TFT), the mark with the insulating barrier in the perimeter circuit area, wherein, the dielectric layer It is located between second protective layer and first protective layer, second protective layer there is one the 3rd opening to correspond to this second open Mouthful, to expose the inner surface of the substrate, and first protective layer forms the thin film transistor (TFT), the mark, positioned at the perimeter line On insulating barrier, second protective layer, first opening, second opening and the 3rd opening in the area of road.

20. image element array substrates as claimed in claim 19, it is characterised in that the dielectric layer has one the 4th opening, is located at The top of the mark, first protective layer be formed at the 4th opening on, and the 4th opening not with this first opening, this second Opening and the 3rd open communication.

21. the image element array substrates as described in claim 14~20 is any, wherein, the dielectric constant of the insulating barrier is less than 5, greatly In 1.

22. the image element array substrates as described in claim 14~20 is any, it is characterised in that the mark is located at the four of the substrate Individual corner, this first opening there is two Part I and a Part II, respectively the Part I expose the substrate edges and It has the distance more than 0 with the substrate edges, and the Part II is respectively communicated with the respectively Part I, and the neighbouring mark, but It is not overlapping with the substrate edges.

23. the image element array substrates as described in claim 14~20 is any, it is characterised in that the mark is not positioned at precut area Four corners, this first opening there is two Part I and a Part II, respectively the Part I exposes the substrate edges And it has the distance more than 0 with the substrate edges, the Part II is respectively communicated with the respectively Part I, and the neighbouring mark, It is but not overlapping with the substrate edges.

24. the image element array substrates as described in claim 14~20 is any, it is characterised in that it is exhausted that the insulating barrier includes a grid Edge layer or the gate insulator and an etch stop layer stack film layer.

25. a kind of display panel, comprising：

A kind of image element array substrates as described in claim 14~20 is any；

One opposite substrate；

One frame glue, it is arranged between the image element array substrates and the opposite substrate, wherein, the frame glue surround the viewing area to form One space, and the frame glue is located between first opening and the viewing area；And

One display dielectric layer, it is formed in the space.

26. display panel as claimed in claim 25, it is characterised in that also comprising at least one smooth separation material be arranged at this to Between substrate and the image element array substrates, and corresponding to first opening and place of the substrate edges with the distance more than 0.