TW201642448A - Pixel array substrate, display panel, and master thereof - Google Patents

Abstract

A pixel array substrate includes a substrate, a thin-film-transistor (TFT), a first signal line, a second signal line, a pixel electrode, a first conductive pattern, and a first protection layer. The substrate includes a display area and at least one spherical circuit area. The TFT is disposed on the substrate within the display area and has an insulating layer extended to the spherical circuit area. The first signal line, the second signal line, and the pixel electrode are all disposed on the substrate within the display area and connected to the TFT. The first conductive pattern is disposed in the spherical circuit area and adjacent to the edge of the substrate. The first conductive pattern is overlapped by the insulating layer to form a mark. The TFT, the mark, the insulating layer within the spherical circuit area are all covered by the first protection layer, wherein the permittivity of the first protection layer is larger than the permittivity of the insulating layer.

Description

Pixel array substrate, display panel and motherboard thereof

The present invention relates to a pixel array substrate and a mother board thereof, and more particularly to a pixel array substrate and a mother board using the thin film transistor technology.

A pixel array substrate fabricated by a thin film transistor process is widely used in the field of display panels. Since the thin film transistor can realize the integrated circuit on the glass substrate, it can be used to produce a highly integrated display panel.

However, the display panel manufactured by the thin film transistor technology tends to have a color shift at the edge after being used for a long time. The reason is that water vapor in the environment enters the pixel array substrate from the edge of the pixel array substrate of the display panel, so that the oxide semiconductor in part of the thin film transistor absorbs moisture and deteriorates characteristics. Therefore, how to prevent water vapor from entering the pixel array substrate to improve the life of the produced display panel is an urgent problem to be solved.

In view of the above problems, the present invention provides a pixel array substrate and a motherboard design thereof for reducing the probability of water vapor degrading internal circuits.

The pixel array substrate disclosed in the present invention has a substrate, a thin film transistor, a first signal line, a second signal line, a pixel electrode, and a first conductive pattern. Case with the first protective layer. The substrate has a display area and at least one peripheral line area, and the display area has a plurality of pixel areas. The thin film transistor is disposed on the substrate and located on at least a portion of the pixel region, the thin film transistor having a gate, a source, a drain, an insulating layer and an oxide semiconductor layer, wherein the insulating layer is located at the gate and the oxide Between the semiconductor layers, the source/drain is in contact with the oxide semiconductor layer, and the insulating layer extends to the peripheral wiring region. The first signal line is disposed on the substrate and located on a part of the pixel area and connected to the gate. The second signal line is disposed on the substrate and located on a part of the pixel area, and is connected to the source. The pixel electrode is disposed on the substrate and located on a part of the pixel area and connected to the drain. The first conductive pattern is disposed on the peripheral line region and adjacent to the edge of the substrate, wherein the insulating layer located in the peripheral line region overlaps with the first conductive pattern layer to form a mark, and the insulating layer has a first opening to expose the inner surface of the substrate, and The first opening is located on the peripheral line area and surrounds the display area and avoids the marking. The first protective layer is formed on the substrate, and is formed on the thin film transistor, the mark, the insulating layer on the peripheral line region and the first opening, wherein the dielectric constant of the first protective layer is greater than the dielectric constant of the insulating layer, and The insulating layer has a dielectric constant of less than 6, greater than one.

The motherboard disclosed in the present invention has a substrate, a thin film transistor, a first signal line, a second signal line, a pixel electrode, a first conductive pattern and a first protective layer. The substrate has a plurality of display units, and a pre-cut area is defined between the display units, and each display unit includes a display area and a peripheral line area, wherein the display area has a plurality of pixel areas. The thin film transistor is disposed on the substrate and located on at least a portion of the pixel region, and the thin film transistor has a gate, a source, a drain, an insulating layer, and The oxide semiconductor layer, wherein the insulating layer is located between the gate and the oxide semiconductor layer, and the source/drain is in contact with the oxide semiconductor layer, and the insulating layer extends to the peripheral wiring region of each display unit. The first signal line is disposed on the substrate and located on at least a portion of the pixel area and connected to the gate. The second signal line is disposed on the substrate and located on at least a portion of the pixel area and connected to the source. The pixel electrode is disposed on the substrate and located on at least a portion of the pixel region and connected to the drain. The first conductive pattern is disposed on a portion of the pre-cut region, and a portion of the first conductive pattern is located in the peripheral line region, wherein the insulating layer on the peripheral line region overlaps with the first conductive pattern to form a mark, and the insulating layer There is a first opening exposing the inner surface of the substrate, and the first opening is located on the peripheral line region and surrounds the display area, and avoids the mark. The first protective layer is formed on the substrate, and is formed on the thin film transistor, the mark, the insulating layer on the peripheral line region and the first opening, wherein the dielectric constant of the first protective layer is greater than the dielectric constant of the insulating layer, And the insulating layer has a dielectric constant of less than 6, greater than one.

In summary, the pixel array substrate and the motherboard thereof disclosed by the present invention have a low dielectric constant (such as an insulating layer) and a material having a high dielectric constant (first protection). Layer) is suitable for isolating the external environment moisture and matching the relevant design of the opening, so it is not easy to process the water vapor during the process and the process of use, thereby improving the yield and life of the pixel array substrate and its mother board.

The above description of the present invention and the following description of the embodiments are intended to illustrate and explain the spirit and principles of the invention The scope of the patent application of the present invention is further explained.

1000‧‧‧ mother board

1100, 3100‧‧‧ substrate

1101, 3101‧‧‧ upper surface

310E‧‧‧ edge

1110‧‧‧Display unit

1111, 3111‧‧‧ display area

1113, 3113‧‧‧ surrounding area

1130‧‧‧Pre-cut area

1300, 3300‧‧‧ film transistor

130G, 330G‧‧‧ gate

130S, 330S‧‧‧ source

130D, 330D‧‧‧汲

130I, 330I‧‧‧Insulation

1400, 1500, 3400, 3500‧‧‧ signal lines

1600, 3600‧‧‧ pixel electrodes

1700, 1710, 3700, 3710‧‧‧ conductive patterns

1800~1830, 3800~3830‧‧‧ openings

1801, 1803, 1807, 3801, 3803, 3807‧‧‧ first part

1805, 1809, 3805, 3809‧‧‧ second part

380E‧‧‧ side wall

1900, 1910, 3900, 3910‧‧ ‧ protective layer

1920, 3920‧‧‧ dielectric layer

2000‧‧‧ Panel Motherboard

3000‧‧‧ pixel array substrate

4000‧‧‧ display panel

2100, 4100‧‧‧ opposite substrate

2200, 4200‧‧‧ box glue

2300, 4300‧‧‧ Display media layer

2400, 4400‧‧‧ optical spacers

AA’, BB’, CC’, DD’‧‧‧ cut line

Aa’, bb’, cc’, dd’‧‧‧ cut line

1 is a plan view of a pixel array substrate mother board according to an embodiment of the present invention.

Fig. 2A is a partial cross-sectional view corresponding to the cutting line AA' in Fig. 1.

Fig. 2B is a partial cross-sectional view corresponding to the cut lines BB' and DD' in Fig. 1.

Fig. 2C is a partial cross-sectional view corresponding to the section line CC' in Fig. 1.

Figure 3 is a plan view of a mother board in accordance with another embodiment of the present invention.

Fig. 4 is a partial cross-sectional view showing a section line CC' of Fig. 1 according to another embodiment of the present invention.

Fig. 5A is a partial cross-sectional view showing a mother board in accordance with a section line AA' in accordance with still another embodiment of the present invention.

Fig. 5B is a partial cross-sectional view showing the mother board in accordance with still another embodiment of the present invention corresponding to the cutting line BB'.

Fig. 5C is a partial cross-sectional view showing the mother board in accordance with another embodiment of the present invention corresponding to the cutting line CC'.

Fig. 6 is a partial cross-sectional view showing a mother board in accordance with another embodiment of the present invention corresponding to a cutting line CC'.

Figure 7 is a partial cross-sectional view showing a panel mother board according to another embodiment of the present invention.

Fig. 8 is a plan view of the pixel array substrate corresponding to the mother board in Fig. 1 being cut.

Fig. 9A is a partial cross-sectional view corresponding to the cutting line aa' in Fig. 8.

Fig. 9B is a partial cross-sectional view corresponding to the cut line bb' in Fig. 8.

Fig. 9C is a partial cross-sectional view corresponding to the cut line cc' in Fig. 8.

The 9D diagram corresponds to a partial cross-sectional view of the section line dd' in Fig. 8.

Figure 10 is a plan view of a pixel array substrate in accordance with another embodiment of the present invention.

Figure 11 is a partial cross-sectional view showing a section line cc' of Figure 8 in accordance with another embodiment of the present invention.

Fig. 12A is a partial cross-sectional view showing a pixel array substrate according to still another embodiment of the present invention corresponding to a cutting line aa'.

Fig. 12B is a partial cross-sectional view showing the pixel array substrate in accordance with still another embodiment of the present invention, corresponding to the cutting line bb'.

Fig. 12C is a partial cross-sectional view showing a pixel array substrate according to still another embodiment of the present invention corresponding to a cutting line cc'.

Fig. 12D is a partial cross-sectional view showing a pixel array substrate according to still another embodiment of the present invention corresponding to a cut line dd'.

Figure 13 is a partial cross-sectional view showing a pixel array substrate in accordance with another embodiment of the present invention corresponding to a cut line cc'.

Figure 14 is a cross-sectional view showing a display panel in accordance with another embodiment of the present invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1 to FIG. 2C , wherein FIG. 1 is a top view of a pixel array substrate according to an embodiment of the present invention, and FIG. 2A is a partial cross-sectional view corresponding to a line AA′ in FIG. 1 . 2B is a partial cross-sectional view corresponding to the cutting lines BB' and DD' in FIG. 1, and FIG. 2C is a partial cross-sectional view corresponding to the cutting line CC' in FIG. As shown in FIG. 1, FIG. 2A and FIG. 2B, the mother board 1000 according to an embodiment of the present invention has a substrate 1100. The substrate 1100 has a plurality of display units 1110, and at least one pre-cut area 1130 is defined between the display units. Each display unit 1110 includes a display area 1111 having a plurality of pixel areas (not labeled) and at least one peripheral line area 1113 adjacent to the display area 1111. The embodiment of the present invention is to surround at least one periphery of the display area 1113. The line area 1113 is an implementation example, but is not limited thereto. It should be noted that after each display unit 1110 is cut, it is a pixel array substrate or a display panel of a display panel.

As shown in FIG. 2A, a thin film transistor 1300 is disposed on the upper surface of the substrate 1100 in at least a portion of the pixel region (not shown) in the display region 1111. The thin film transistor 1300 has a gate 130G, a drain 130D, and a source 130S, an insulating layer 130I and an oxide semiconductor layer 130O. The insulating layer 130I is located between the gate 130G and the oxide semiconductor layer 130O, and the source 130S and the drain 130D are in contact with the oxide semiconductor layer 130O, that is, the source 130S and the drain 130D are combined with the oxide semiconductor layer 130O. The insulating layer 130I also extends to the peripheral line region 1113 of the associated display unit 1110, wherein the insulating layer 130I has a dielectric constant of less than 6, greater than one. In a particular embodiment, the insulating layer 130I has a dielectric constant of less than 5 and greater than one. The material of the insulating layer 130I may be cerium oxide, carbon cerium oxide, cerium oxynitride, cerium carbide, cerium-based polymer, spin-on-glass (SOG) or other suitable materials, and the physical properties or chemical properties of the foregoing materials. Refer to the Material Safety Data Sheet, and the nitrogen atom percentage of bismuth oxynitride is substantially less than 30% greater than 0%, the oxygen atom is greater than the percentage of nitrogen atoms, the cesium atom percentage is substantially less than the sum of nitrogen and oxygen atoms, and the nitrogen and oxygen atoms The sum is less than 67% and more than 62%, wherein the total of nitrogen, oxygen and helium atoms is 100%, and the refractive index of cerium oxynitride is greater than 1.45 and less than 1.75, and the manufacturing method thereof may be chemical vapor deposition, sputtering or other. suitable method. In the present invention, the material of the insulating layer 130I is cerium oxide as an example, but is not limited thereto. In some embodiments, only one gate insulating layer is included in the insulating layer 130I, and in other embodiments, the insulating layer 130I is formed by stacking a plurality of insulating materials, for example, the insulating layer 130I is composed of a gate insulating layer and an etch stop layer. The stacked film layer is constructed. Although in the present embodiment, the gate electrode 130G is located below the oxide semiconductor layer 130O, that is, the bottom gate type thin film transistor is exemplified, it is not limited thereto. In other embodiments, the gate 130G is also located above the oxide semiconductor layer 130O, that is, a top gate type thin film transistor, or It is the gate 130G located at other positions of the oxide semiconductor layer 130O, that is, other types of thin film transistors can also be applied. The oxide semiconductor may be a single layer or a multilayer structure, and the material thereof includes indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide (IGO), tin oxide (ZnO), cadmium oxide yttrium oxide. Bismuth (CdO2.GeO2), nickel cobalt oxide (NiCo2O4), zinc oxide (ZnO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO) or other suitable materials.

In addition, a first signal line 1400, a second signal line 1500, and a pixel electrode 1600 are further disposed on the thin film transistor 1300. The first signal line 1400 is connected to the gate 130G, and the first signal line 1400 can be regarded as a scan line or a gate line, and the second signal line 1500 is connected to the source 130S. Then, the second signal line 1500 can be regarded as a data line, and the second signal line 1500 can be regarded as a data line. The prime electrode 1600 is connected to the drain 130D. The first signal line 1400, the second signal line 1500, and the pixel electrode 1600 are all schematically depicted. In addition, a first conductive pattern 1700 is disposed on the substrate 1100. The first conductive pattern 1700 is disposed in a portion of the pre-cut region 1130, and a portion of the first conductive pattern 1700 is located in the peripheral line region 1113. The insulating layer 130I of 1113 overlaps with the first conductive pattern 1700 to constitute the mark M in FIG. The insulating layer 130I has a first opening 1800, and a portion of the upper surface 1101 (or may be referred to as an inner surface) of the substrate 1100 is exposed through the first opening 1800, and the first opening 1800 is located on the peripheral line region 1113 and surrounds the display region 1111. And avoid the mark M. Although the first conductive pattern 1700 covers the insulating layer 130I in the illustration, the first conductive pattern 1700 may also be covered by the insulating layer 130I, which is not limited in the present invention.

A first protective layer 1900 is formed on the substrate 1100 and formed on the thin film transistor 1300, the mark M, the insulating layer 130I located in the peripheral line region 1113, and the first opening 1800. The dielectric constant of the first protective layer 1900 is greater than the dielectric constant of the insulating layer 130I. The material of the first protective layer 1900 may be tantalum nitride, tantalum oxynitride, tantalum oxide, aluminum oxide, titanium oxide, hafnium oxide (HfO) or other suitable materials, and the physical properties of the foregoing materials are Refer to the material safety data sheet, and the nitrogen atom percentage of bismuth oxynitride should be substantially greater than or equal to 30% and less than 58%, the oxygen atom is less than the percentage of nitrogen atoms and greater than 0%, and the percentage of germanium atoms is substantially smaller than the atomic percentage of nitrogen and oxygen. The sum of the atomic percentage of nitrogen and oxygen is less than or equal to 62% greater than 57%, wherein the sum of nitrogen, oxygen and helium atoms is 100%, and the refractive index of cerium oxynitride is greater than or equal to 1.75 and less than 2.0, and the manufacturing method may be chemistry. Vapor deposition, sputtering or other suitable method. The present invention is exemplified by the material of the first protective layer 1900 being tantalum nitride, but is not limited thereto. Therefore, as shown in FIG. 2B, in a partial cross-sectional view corresponding to the cutting line BB' at the pre-cutting region 1130, the first protective layer 1900 on the substrate 1100 is at the first opening 1800 of the insulating layer 130I and the substrate. The 1100 is in contact, and the portion other than the first opening 1800 does not contact the upper surface of the substrate 1100.

As shown in Fig. 2C, in a partial cross-sectional view corresponding to the section line CC' at the mark M, the substrate 1100 has a first conductive pattern 1700 thereon, and an insulating layer 130I thereon. A first protective layer 1900 is covered over the insulating layer 130I.

In some embodiments, returning to FIG. 1 , the mark M is located at four corners of the pre-cut area 1130 surrounding the display unit 1110 , and the first opening 1800 at each corner has two first portions 1801 . The first portion 1805 overlaps the first portion 1801 and the first portion 1803, and the second portion 1805 is adjacent to the mark. M, but not overlapping the pre-cutting zone 1130, it can be considered that the second portion 1805 is not in communication with the marker M. In this embodiment, the mark M can be used as a registration mark and/or a cut mark, and the projected shape of the mark M is substantially a cross shape, but is not limited thereto. In other embodiments, the projected shape of the indicia M can be L-shaped, T-shaped, or other suitable projected shape.

In another embodiment, please refer to FIG. 3, which is a top view of a motherboard according to another embodiment of the present invention. As shown in FIG. 3, compared with the embodiment of FIG. 1, the mark M of the present embodiment is not located at four corners of the pre-cutting area 1130, but may be located outside the four corners, and the first opening 1800 Having two first portions 1801, 1807 and a second portion 1809, each of the first portions 1801, 1807 overlaps with the pre-cut region 1130, and the second portion 1809 connects the first portion 1801 with the first portion 1807, and adjacent to the mark M, but not overlapping the pre-cut area 1130, it can be seen that the second portion 1809 is not in communication with the mark M. The cross-sectional structures of the hatching lines AA', BB', CC', DD' and EE' shown in Fig. 3 can be seen in Figs. 2a to 2d and Figs. 4 to 7. Assuming that each display unit 1110 has a plurality of sides, each side will have at least one mark M shown in FIG. In this embodiment, the mark M can be used as a registration mark and/or a cut mark, and the mark M The projected shape is substantially a straight line, but is not limited thereto. For example, the projected shape of the mark M may be a curved line or other suitable projected shape. In other embodiments, the mark M shown in FIG. 1 may also be included in FIG. 3, and the mark may be added to the corners and non-corners to re-align the alignment and/or the cutting effect. Similarly, the mark M shown in FIG. 3 can also be included in FIG. 1 , and the mark is added at the corners and non-corners to enhance the effect of alignment and/or cutting.

In another embodiment, reference is made to Fig. 4, which is a partial cross-sectional view of a section line CC' of Fig. 1 in accordance with another embodiment of the present invention. As shown in FIG. 4, in the present embodiment, in the partial cross-sectional structure of the position where the mark M is located, the difference from the embodiment of FIG. 2C is that the mother board 1000 in this embodiment further has the second conductive pattern. 1710. The second conductive pattern 1710 is disposed on a portion of the pre-cut region 1130, and a portion of the second conductive pattern 1710 is located in the peripheral line region 1113. The second conductive pattern 1710 overlaps with the first conductive pattern 1700, and the mark M is formed by overlapping the insulating layer 130I located in the peripheral line region 1113, the first conductive pattern 1700, and the second conductive pattern 1710. In the portion of the mark M, the insulating layer 130I is interposed between the first conductive pattern 1700 and the second conductive pattern 1710.

In still another embodiment, please refer to FIG. 5A to FIG. 5C , wherein FIG. 5A is a partial cross-sectional view of the motherboard corresponding to the cutting line AA′ according to another embodiment of the present invention, and FIG. 5B is a According to still another embodiment of the present invention, a partial cross-sectional view of the motherboard corresponding to the cutting line BB', and FIG. 5C is a partial cross-section of the motherboard corresponding to the cutting line CC' according to another embodiment of the present invention. Schematic diagram. As shown in FIG. 5A, FIG. 5B and FIG. 5C, the mother board 1000 in this embodiment has a second protective layer 1910 and a second embodiment as compared with the embodiments of FIGS. 2A to 2C. The protective layer 1910 is formed on the substrate 1100 and formed on the thin film transistor 1300, the mark M and the insulating layer 130I on the peripheral line region 1113. The second protective layer 1910 is sandwiched between the insulating layer 130I and the first protective layer. Between 1900, the second protective layer 1910 has a second opening 1810 corresponding to the first opening 1800 to expose a portion of the upper surface 1101 of the substrate 1100 (which may be referred to as an inner surface because the rest of the upper surface 1101 of the substrate 1100) The portion is covered by each material layer without being exposed, and the first protective layer 1900 is formed on the thin film transistor 1300, the mark M, the insulating layer 130I on the peripheral line region 1113, the second protective layer 1910, and the first opening. 1800 and the second opening 1810. Further, the dielectric constant of the first protective layer 1900 may be greater than the dielectric constant of the second protective layer 1910. For example, the dielectric constant of the second protective layer 1910 can be selectively less than 6 and greater than 1, and the second protective layer 1910 can be selected from the materials described for the insulating layer 130I or other suitable materials.

In addition, referring also to FIGS. 5A through 5C, the motherboard 1000 in some embodiments may have a dielectric layer 1920, while in other embodiments the dielectric layer 1920 may not be present. The dielectric layer 1920 is formed on the substrate 1100 and formed on the thin film transistor 1300, the mark M, and the insulating layer 130I on the peripheral line region 1113. The dielectric layer 1920 is interposed between the second protective layer 1910 and the first protective layer 1900. The dielectric layer 1920 has a third opening 1820 corresponding to the second opening 1810 to expose a portion of the upper surface of the substrate 1100. 1101, and the first protective layer 1900 is formed on the thin film transistor 1300, the mark M, the insulating layer 130I located in the peripheral line region 1113, the second protective layer 1910, the dielectric layer 1920, the first opening 1800, the second opening 1810, and the first Three openings 1820.

In another embodiment, please refer to FIG. 6, which is a partial cross-sectional view of the motherboard corresponding to the cutting line CC' according to another embodiment of the present invention. As shown in FIG. 6, the dielectric layer 1920 of the present embodiment has a fourth opening 1830 as compared to the embodiment of FIG. 5C. The fourth opening 1830 is located above the mark M, the first protective layer 1900 is formed on the fourth opening 1830, and the fourth opening 1830 is selectively not in communication with the first opening 1800, the second opening 1810, and the third opening 1820. In other embodiments, the fourth opening 1830 can communicate with the first opening 1800, the second opening 1810, and the third opening 1820. Due to the presence of the fourth opening 1830, the height difference between the mark M and the pre-cutting region 1130 is smaller than in the embodiments of FIGS. 2A to 2C, thereby causing the mother board to be cut to produce a pixel array substrate. The yield can be improved, and the moisture barrier capability can be enhanced to improve the reliability of the display panel.

In another embodiment, a panel mother board made of the foregoing mother board is referred to FIG. 7 , which is a partial cross-sectional view of a panel mother board according to another embodiment of the present invention. Referring to FIG. 7 and FIG. 1 or FIG. 14 and FIG. 3, the motherboard mother board 2000 has the motherboard 1000, the opposite substrate 2100, the sealant 2200, and the display medium layer 2300 according to any of the foregoing embodiments. Light spacer 2400. The sealant 2200 is disposed between the substrate 1100 and the opposite substrate 2100 corresponding to each display unit 1110 on the motherboard 1000. Frame glue 2200 is located in the first Between an opening 1800 and the display area 1111 of each display unit 1110, the sealant 2200 surrounds the display area 1111 of each display unit 1110 to form a space in which the display medium layer 2300 is filled. A photo spacer 2400 is disposed between the opposite substrate 2100 and the substrate 1100 and corresponds to at least a portion of the pre-cut region 1130. The thickness of the optical spacer 2400 can be selectively less than or substantially equal to the thickness of the display dielectric layer 2300, and the optical spacer 2400 can further increase the proper rate of cutting the substrate. In other words, in the present embodiment, the pre-cutting region 1130 passes through the mark M and a portion of the first opening 1800 (for example, the two first portions 1801 and 1805 or 1801 and 1807), and the optical spacer 2400 can be stored. And corresponding to the at least one portion of the mark M, and disposed between the opposite substrate and the substrate; or the optical spacer 2400 may be stored in the first opening 1800 corresponding to the portion (for example, two first The positions of the portions 1801 and 1805 or 1801 and 1807) are disposed between the opposite substrate and the substrate; or the optical spacer 2400 is stored in the first portion corresponding to at least a portion of the mark M and the portion The opening 1800 (for example, the two first portions 1801 and 1805 or 1801 and 1807) is disposed between the opposite substrate and the substrate. Furthermore, the cross-sectional views shown in FIG. 5B, 5C and/or FIG. 6 may also optionally include the optical spacer 2400 and its related description described in FIG. 7, and the relative position and the matching relationship may be clearly understood. . In some embodiments, however, if the process of cutting the motherboard is generally less likely to affect the rate of cutting, then there may be no optical spacers 2400 corresponding to the location of the pre-cutting zone 1130. It should be noted that after each display unit 1110 is cut, it is a pixel array substrate or a display panel of a display panel.

Therefore, when the plurality of pixel array substrates obtained by the mother board 1000 are cut, a plan view of a single pixel array substrate and a cross-sectional view of each part are referred to FIGS. 8 to 9D, wherein the eighth figure corresponds to FIG. 1 is a top view of a single pixel array substrate obtained by dividing a mother board, and FIG. 9A is a partial cross-sectional view corresponding to a cutting line aa' in FIG. 8, and FIG. 9B corresponds to FIG. A partial cross-sectional view of the middle cut line bb', the 9C figure corresponds to a partial cross-sectional view of the cut line cc' in Fig. 8, and the 9D figure corresponds to a partial cross section of the cut line dd' in Fig. 8. schematic diagram.

As shown in FIG. 8, FIG. 9A and FIG. 9B, the pixel array substrate 3000 in one embodiment of the present invention has a substrate 3100. The substrate 3100 includes a display area 3111 having a plurality of pixels (not shown) and at least one peripheral line area 3113 adjacent to the display area 3111. The embodiment of the present invention is to surround at least one peripheral line area of the display area 3113. 3113 is an example of implementation, but is not limited thereto. It must be noted that each display unit 1110 is a display panel pixel after being cut from a motherboard (such as the motherboard 1100 of FIG. 1) along a pre-cut area (eg, the pre-cut area 1130 of FIG. 1). The array substrate shows that the edge of the pixel array substrate is the pre-cut area.

As shown in FIG. 9A, a thin film transistor 3300 is provided on the upper surface of the substrate 3100 in at least a portion of the pixel region (not shown) in the display region 3111. The thin film transistor 3300 includes a gate 330G, a drain 330D, a source 330S, an insulating layer 330I, and an oxide semiconductor layer 330O. The insulating layer 330I is located between the gate 330G and the oxide semiconductor layer 330O, and the source 330S and The drain 330D is in contact with the oxide semiconductor layer 330O, that is, the source 330S and the drain 330D partially overlap the oxide semiconductor layer 330O, and the insulating layer 330I also extends to the peripheral wiring region 3113, wherein the dielectric of the insulating layer 330I The constant is less than 6, greater than 1. In a particular embodiment, the insulating layer 330I has a dielectric constant of less than 5 and greater than one. The material of the insulating layer 330I may be selected from the material of the insulating layer 130I in the above embodiment. In some embodiments, only the gate insulating layer is included in the insulating layer 330I, and in other embodiments, the insulating layer 330I is formed by stacking a plurality of insulating materials, for example, the insulating layer 330I is composed of a gate insulating layer and an etch stop layer. The stacked film layer is constructed. Although in the present embodiment, the gate 330G is located below the oxide semiconductor layer 330O, that is, the bottom gate type thin film transistor is exemplified, but is not limited thereto. In other embodiments, the gate 330G is also located above the oxide semiconductor layer 330O, that is, the top gate type thin film transistor, or the gate 330G is located at other positions of the oxide semiconductor layer 330O, that is, other types of thin film transistors are also Applicable. The oxide semiconductor layer 330O may be a single layer or a multilayer structure, and the material thereof is selected from the materials described in the oxide semiconductor layer 130O in the above embodiment.

In addition, a first signal line 3400, a second signal line 3500, and a pixel electrode 3600 are further disposed on the thin film transistor 3300. The first signal line 3400 is connected to the gate 330G, and the first signal line 3400 can be regarded as a scan line or a gate line, and the second signal line 3500 is connected to the source 330S. Then, the second signal line 3500 can be regarded as a data line, and the second signal line 3500 can be regarded as a data line. The element electrode 3600 is connected to the drain 330D. The first signal line 3400, the second signal line 3500, and the pixel electrode 3600 are all schematically depicted. In addition, there is a first conductive pattern 3700 on the substrate 3100, A conductive pattern 3700 is disposed in the peripheral line region 3113 and adjacent to an edge (or side or sidewall) 310E of the substrate 3100, wherein the insulating layer 330I located in the peripheral line region 3113 overlaps with the first conductive pattern 3700 to form an eighth figure. In the mark m. The insulating layer 330I has a first opening 3800, and a portion of the upper surface 3101 (or may be referred to as an inner surface) of the substrate 3100 is exposed through the first opening 3800, and the first opening 3800 is located on the peripheral line region 3113 and surrounds the display region 3111. And avoid the mark m. Although the first conductive pattern 3700 covers the insulating layer 330I in the illustration, the first conductive pattern 3700 may also be covered by the insulating layer 330I, which is not limited in the present invention.

The first protective layer 3900 is formed on the substrate 3100 and formed on the thin film transistor 3300, the mark m, the insulating layer 330I located in the peripheral line region 3113, and the first opening 3800. The dielectric constant of the first protective layer 3900 is greater than the dielectric constant of the insulating layer 330I. Wherein, the material of the first protective layer 3900 may be selected from the materials of the first protective layer 1900 described in the foregoing embodiments. Therefore, as shown in FIG. 9B, in a partial cross-sectional view corresponding to the cutting line bb' of the edge 310E of the substrate 3100, the first protective layer 3900 on the substrate 3100 is at the first opening 3800 of the insulating layer 330I and the substrate. The 3100 is in contact, and the portion other than the first opening 3800 does not contact the upper surface of the substrate 3100.

As shown in Fig. 9C, in a partial cross-sectional view corresponding to the section line cc' at the mark m, the substrate 3100 has a first conductive pattern 3700 thereon, and an insulating layer 330I thereon. Covered on the insulating layer 330I A protective layer 3900.

In some embodiments, returning to FIG. 8, the mark m is located at four corners of the pixel array substrate 3000. The first opening 3800 has at least two first portions 3801, 3803 and a second portion 3805. Each of the first portions is adjacent to the edge 310E of the substrate 3100, and the second portion 3805 is connected to the first portion 3801 and the first portion 3803, respectively, and the second portion 3805 is adjacent to the mark m, but is not adjacent to the edge 310E of the substrate 3100. . At this time, the second portion 3805 is not in communication with the mark m, and the projected shape of the cut mark m may be L-shaped or other suitable shape. When the sidewalls 380E of the first portion and the edge 310E of the substrate are projected on a plane, the two sides (ie, the sidewall 380E of the first portion 3801 and the edge 310E of the substrate and the sidewall 380E of the first portion 3083 and the substrate) The distance d between the edges 310E) is greater than zero.

As shown in Fig. 9D, a partial cross-sectional view corresponding to the section line dd' at the second portion 3805 of the first opening 3800 next to the mark m is shown. In a partial cross-sectional view corresponding to the cutting line bb', the first protective layer 3900 on the substrate 3100 covers the insulating layer 330I and covers the sidewall of the first opening 3800, extending over the upper surface 3101 of the substrate 3100 until the edge 310E At the office. With the first opening 3800, the insulating layer 330I having a lower dielectric constant is covered by the first protective layer 3900 having a higher dielectric constant and is not directly exposed to the air. Although at the mark m, that is, the insulating layer 330I at the cut line cc' is exposed to the air, the second portion 3805 of the first opening 3800 is in the left side of the 9D (the dd' line in Fig. 8) Far from the part marked m) The insulating layer 330I of the edge layer 330I and the right side (the portion of the dd' cut line near the mark m in Fig. 8) is not connected. Therefore, even if the insulating layer 330I near the mark m absorbs the moisture in the air, the insulating layer 330I near the display area does not absorb the moisture, thereby causing the moisture to affect the components of the display area to decrease, prolonging the life of the panel. . Similarly, in the pixel array substrate and the first opening 1800 at the relevant position in the motherboard, the first opening 1800 has a lower dielectric constant of the insulating layer 130I because of the higher dielectric constant. The protective layer 1900 is coated and does not directly expose to the air after cutting to absorb moisture, so that the probability of moisture affecting the components of the display area is reduced, and the life of the panel is prolonged.

In another embodiment, please refer to FIG. 10, which is a top view of a pixel array substrate according to another embodiment of the present invention. As shown in FIG. 10, compared with the embodiment of FIG. 8, the mark m of the present embodiment is not located at four corners of the pixel array substrate 3000, but may be located at positions other than the four corners, and the first opening The 3800 has at least two first portions 3801, 3807 and a second portion 3809, each first portion is adjacent to the edge 310E, and the second portion 3809 is connected to the first portion 3801 and the first portion 3807, respectively, and adjacent thereto. Mark m, but not adjacent to edge 310E, it can be seen that second portion 3809 is not in communication with marker m. Assuming that each display unit 1110 has a plurality of sides, each side has at least one mark m shown in FIG. 10, and the projected shape of the mark m is substantially linear, but is not limited thereto, for example. The projected shape of the mark m can be a curve or other suitable projected shape. In other embodiments, the mark m shown in FIG. 8 may also be included in FIG. Similarly, Figure 8 can also include the image shown in Figure 10. Mark m, mark m at both corners and non-corners. When the sidewalls of the first portion and the edge 310E of the substrate are projected on a plane, the two sides (ie, the sidewall of the first portion 3081 and the edge 310E of the substrate and the sidewall of the first portion 3087 and the edge 310E of the substrate) The distance d' between them is greater than 0, and the cross-sectional structures of the hatching axes aa', bb', cc', dd', and ee' shown in Fig. 10 can be seen in Figs. 9A to 9D and Figs. By the distance d or d' being greater than 0, it can be ensured that the insulating layer 330I is not directly exposed to the air in the cut panel. Between the insulating layer 330I and the air, the first protective layer 3900 necessarily insulates the insulating layer 330I. In the air.

In another embodiment, reference is made to Fig. 11, which is a partial cross-sectional view of a section line cc' according to Fig. 8 of another embodiment of the present invention. As shown in FIG. 11, in the embodiment, the portion of the cross-sectional structure at the position of the mark m is different from the embodiment of the ninth embodiment in that the pixel array substrate 3000 of the present embodiment has a second Conductive pattern 3710. A portion of the second conductive pattern 3710 is located in the peripheral line region 3113. The second conductive pattern 3710 overlaps with the first conductive pattern 3700, and the mark m is formed by overlapping the insulating layer 330I located in the peripheral line region 3113, the first conductive pattern 3700, and the second conductive pattern 3710. And in the portion marked with m, the insulating layer 330I is interposed between the first conductive pattern 3700 and the second conductive pattern 3710.

In still another embodiment, please refer to FIG. 12A to FIG. 12D , wherein FIG. 12A is a partial cross-sectional view of the pixel array substrate according to another embodiment of the present invention corresponding to the cutting line aa′, and FIG. 12B. Drawing according to the invention In another embodiment, the pixel array substrate corresponds to a partial cross-sectional view of the cutting line bb', and FIG. 12C is a partial cross-sectional view of the pixel array substrate according to the embodiment of the present invention corresponding to the cutting line cc'. 12D is a partial cross-sectional view of the pixel array substrate according to another embodiment of the present invention corresponding to the cutting line dd'. As shown in FIGS. 12A to 12D, the mother board 3000 in this embodiment has a second protective layer 3910 and a second protective layer 3910 formed in comparison with the embodiments of FIGS. 9A to 9D. On the substrate 3100, and formed on the thin film transistor 3300, the mark m and the insulating layer 330I located in the peripheral line region 3113, wherein the second protective layer 3910 is interposed between the insulating layer 330I and the first protective layer 3900, The second protective layer 3910 has a second opening 3810 corresponding to the first opening 3800 to expose a portion of the upper surface 3101 of the substrate 3100 (which may be referred to as an inner surface because the remaining portions of the upper surface 3101 of the substrate 3100 are each The material layer is covered without being exposed, and the first protective layer 3900 is formed on the thin film transistor 3300, the mark m, the insulating layer 330I on the peripheral line region 3113, the second protective layer 3910, the first opening 3800 and the second opening On the 3810. In addition, the dielectric constant of the first protective layer 3900 may be greater than the dielectric constant of the second protective layer 3910. For example, the dielectric constant of the second protective layer 3910 can be selectively less than 6 and greater than 1, and the material thereof can be selected from the insulating layer or other suitable materials in the above embodiments.

In addition, referring also to FIGS. 12A through 12D, the pixel array substrate 3000 in some embodiments may further have a dielectric layer 3920, while in other embodiments, the dielectric layer 3920 may not be present. Dielectric layer 3920 formation On the substrate 3100, and formed on the thin film transistor 3300, the mark m and the insulating layer 330I located in the peripheral line region 3113. The dielectric layer 3920 is interposed between the second protective layer 3910 and the first protective layer 3900, and the dielectric layer 3920 has a third opening 3820 corresponding to the second opening 3810 to expose a portion of the upper surface of the substrate 3100. 3101, and the first protective layer 3900 is formed on the thin film transistor 3300, the mark m, the insulating layer 330I located in the peripheral line region 3113, the second protective layer 3910, the dielectric layer 3920, the first opening 3800, the second opening 3810, and the first Three openings 3820.

In another embodiment, reference is made to Fig. 13, which is a partial cross-sectional view of a pixel array substrate according to another embodiment of the present invention corresponding to a cut line cc'. As shown in FIG. 13, the dielectric layer 3920 of the present embodiment has a fourth opening 3830 as compared to the embodiment of FIG. 12C. The fourth opening 3830 is located above the mark m, the first protective layer 3900 is formed on the fourth opening 3830, and the fourth opening 3830 is selectively not in communication with the first opening 3800, the second opening 3810, and the third opening 3820. In other embodiments, the fourth opening 3830 can be in communication with the first opening 3800, the second opening 3810, and the third opening 3820.

In another embodiment, a display panel made of the pixel array substrate described above is referred to FIG. 14 , which is a cross-sectional view of a display panel according to another embodiment of the present invention. Referring to FIG. 14 and FIG. 8 or FIG. 14 and FIG. 10, the display panel 4000 has the pixel array substrate 3000, the opposite substrate 4100, the sealant 4200, and the display medium layer 4300 according to any of the foregoing embodiments. With the optical spacer 4400. The frame glue 4200 is disposed on the pixel array substrate 3000 Between the opposing substrate 4100. The sealant 4200 is located between the first opening 3800 and the display area 3111, and the sealant 4200 surrounds the display area 3111 to form a space in which the display medium layer 4300 is filled. A photo spacer 4400 is disposed between the opposite substrate 4100 and the pixel array substrate 3000, and corresponds to a region between the sidewall of the first opening 3800 and the edge 310E of the substrate 3100, and the thickness of the optical spacer 4400 Optionally, it is less than or substantially equal to the thickness of the display medium layer 4300. In this embodiment, the optical spacer 4400 may be located at a position corresponding to at least a part of the mark m, and disposed between the opposite substrate and the substrate; or the optical spacer 4400 may be stored in the corresponding portion. a portion of the first opening 3800 (for example, two first portions 3801 and 3805 or 3801 and 3807) and disposed between the opposite substrate and the substrate; or the optical spacer 4400 may exist corresponding to At least a portion of the mark m and a portion of the first opening 3800 (eg, the two first portions 3801 and 3805 or 3801 and 3807) are disposed between the opposite substrate and the substrate. Furthermore, the cross-sectional views shown in FIG. 12B, FIG. 12C and/or FIG. 13 may also optionally include the optical spacer 4400 and its related description described in FIG. 14, and the relative position and the matching relationship may be clearly understood. . However, in some embodiments, the procedure for cutting the motherboard is preferably less likely to affect the rate of cutting, and the optical spacers 4400 may be absent corresponding to the locations of the pre-cut regions of the motherboard.

The pixel array substrate and the motherboard thereof disclosed in the foregoing embodiments have an opening directly directly exposing the substrate in a portion of the pre-cut portion of the motherboard, and the first protective layer directly covers the opening and the substrate there. And the opening is also avoided mark. Therefore, when the mother substrate is cut to obtain the pixel array substrate, only the first protective layer and the substrate are directly exposed to the air. In other words, the remaining layers, elements are protected by the first protective layer and are insulated from air. Since the dielectric constant of the first protective layer is high, the moisture is easily blocked by the first protective layer from the first protective layer, so that the materials in the first protective layer are less likely to absorb moisture, thereby causing the oxide therein. Semiconductors are less likely to absorb moisture degradation. Furthermore, the cut panel has a lower dielectric constant insulating layer or other dielectric layer than the first protective layer, and the moisture may be from a lower dielectric constant dielectric layer. The side edge is transferred, but the cut mark is adjacent to the sealant. There is an opening like the above structure (for example, Fig. 7, Fig. 14, etc.) which can effectively block the moisture from the lower dielectric constant dielectric layer. The sides enter the oxide semiconductor. In other words, the layers having a lower dielectric constant in the display region (for example, the insulating layer) are not exposed to the air because they are insulated from the first protective layer by air, and thus the water is absorbed. The probability of deterioration of gas is reduced, so that the life and yield of the panel are improved.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1100‧‧‧Substrate

1101‧‧‧ upper surface

130I‧‧‧Insulation

1800‧‧‧ openings

1900‧‧‧protection layer

Claims (26)

A motherboard includes: a substrate having a plurality of display units, at least one pre-cut area defined between the display units, each of the display units including a display area having a plurality of pixel areas and at least one peripheral line area At least one thin film transistor disposed on the substrate and located on at least a portion of the pixel regions, the thin film transistor having a gate, a source, a drain, an insulating layer and an oxide semiconductor layer The insulating layer is located between the gate and the oxide semiconductor layer, and the source/drain is in contact with the oxide semiconductor layer, and the insulating layer extends to the peripheral line region of each display unit; At least one first signal line disposed on the substrate and located on at least a portion of the pixel regions and connected to the gate; at least one second signal line disposed on the substrate and located in at least a portion of the On the pixel regions, and connecting the source; at least one pixel electrode is disposed on the substrate and located on at least a portion of the pixel regions and connected to the drain; a first conductive pattern is disposed on a part of the pre-cut area, and a portion of the first conductive pattern is located in the peripheral line regions, wherein the insulating layer on the peripheral line region overlaps with the first conductive pattern to form a mark, the insulating layer has a first opening, exposed Out of the base An inner surface of the board, wherein the first opening is located on the peripheral line region and surrounds the display area, and avoids the mark; and at least a first protective layer is formed on the substrate and formed on the thin film transistor, The mark is located on the insulating layer on the peripheral line region and the first opening, wherein a dielectric constant of the first protective layer is greater than a dielectric constant of the insulating layer, and a dielectric constant of the insulating layer is less than 6 ,Greater than 1. The motherboard of claim 1 further comprising a second conductive pattern layer disposed on a portion of the pre-cut region, and a portion of the second conductive pattern layer being located in the peripheral line regions, wherein The second conductive pattern layer overlaps the first conductive pattern layer, and the insulating layer, the first conductive pattern layer and the second conductive pattern layer on the peripheral line region overlap to form the mark. The motherboard as claimed in claim 2, wherein the insulating layer in the mark is interposed between the first conductive pattern layer and the second conductive pattern layer. The motherboard as claimed in claim 2, further comprising a second protective layer formed on the substrate and formed on the thin film transistor, the mark and the insulating layer on the peripheral line region, wherein the a second protective layer is interposed between the insulating layer and the first protective layer, the second protective layer has a second opening corresponding to the first opening to expose an inner surface of the substrate, and the first protection Forming the thin film transistor, the mark, located in the week The insulating layer, the second protective layer, the first opening and the second opening on the side line region. The motherboard according to claim 4, wherein a dielectric constant of the first protective layer is greater than a dielectric constant of the second protective layer, and a dielectric constant of the second protective layer and a dielectric constant of the insulating layer Less than 6, greater than 1. The motherboard of claim 4, further comprising a dielectric layer formed on the substrate and formed on the thin film transistor, the mark and the insulating layer on the peripheral line region, wherein the dielectric layer An electrical layer is interposed between the second protective layer and the first protective layer, the second protective layer has a third opening corresponding to the second opening to expose an inner surface of the substrate, and the first protection The layer forms the thin film transistor, the mark, the insulating layer on the peripheral line region, the second protective layer, the first opening, the second opening and the third opening. The motherboard of claim 6, wherein the dielectric layer has a fourth opening above the mark, the first protective layer is formed on the fourth opening, and the fourth opening does not An opening, the second opening and the third opening are in communication. The mother board according to any one of claims 1 to 7, wherein the insulating layer has a dielectric constant of less than 5 and greater than 1. The motherboard of any one of claims 1 to 7, wherein the mark is located at four corners of the pre-cut area, the first opening has two first portions and a second portion, each of the first Part overlapping the pre-cut area, the second part The portions are respectively connected to the first portion and adjacent to the mark, but do not overlap with the pre-cut area. The motherboard of any one of claims 1 to 7, wherein the mark is not located at four corners of the pre-cut area, the first opening has two first portions and a second portion, each of the first A portion overlaps the pre-cut region, and the second portion communicates with each of the first portions and is adjacent to the mark but does not overlap the pre-cut region. The mother board according to any one of claims 1 to 7, wherein the insulating layer comprises a gate insulating layer or a stacked film layer of the gate insulating layer and an etch stop layer. A display panel motherboard, comprising: a motherboard according to any one of claims 1 to 7; a pair of substrates; a frame glue disposed between the substrate of each display unit and the opposite substrate, Wherein, the sealant surrounds the display area of each display unit to form a space, and the sealant is located between the first opening and the display area of each display unit; and a display medium layer formed in the space Inside. The display panel motherboard of claim 12 further comprising at least one optical spacer disposed between the opposite substrate and the substrate and corresponding to the pre-cut region. A pixel array substrate comprising: a substrate comprising a display area having a plurality of pixel regions and at least one peripheral line region; at least one thin film transistor disposed on the substrate and located on at least a portion of the pixel regions, the thin film transistor having a gate a pole, a source, a drain, an insulating layer and an oxide semiconductor layer, wherein the insulating layer is between the gate and the oxide semiconductor layer, and the source/drain and the oxide semiconductor layer Contacting, and the insulating layer extends to the peripheral line region; at least one first signal line disposed on the substrate and located on at least a portion of the pixel regions and connected to the gate; at least a second signal a wire disposed on the substrate and located on at least a portion of the pixel regions and connected to the source; at least one pixel electrode disposed on the substrate and located on at least a portion of the pixel regions And connecting the drain; a first conductive pattern is disposed on the peripheral line regions and adjacent to an edge of the substrate, wherein the insulating layer on the peripheral line region overlaps with the first conductive pattern layer to form a Marked, the insulating layer has a An opening exposing an inner surface of the substrate, the first opening being located on the peripheral line region and surrounding the display region, and avoiding the mark; and at least a first protective layer formed on the substrate and formed The thin film transistor, the mark, the insulating layer on the peripheral line region And the first opening, wherein a dielectric constant of the first protective layer is greater than a dielectric constant of the insulating layer, and a dielectric constant of the insulating layer is less than 6, greater than 1. The pixel array substrate of claim 14, further comprising a second conductive pattern layer disposed in the peripheral line regions, wherein the second conductive pattern layer overlaps the first conductive pattern layer and is located at the periphery The insulating layer on the line region, the first conductive pattern layer and the second conductive pattern layer overlap to form the mark. The pixel array substrate of claim 15, wherein the insulating layer in the mark is interposed between the first conductive pattern layer and the second conductive pattern layer. The pixel array substrate of claim 15 further comprising a second protective layer formed on the substrate and formed on the thin film transistor, the mark and the insulating layer on the peripheral line region, wherein The second protective layer is disposed between the insulating layer and the first protective layer, and the second protective layer has a second opening corresponding to the first opening to expose an inner surface of the substrate, and the first A protective layer forms the thin film transistor, the mark, the insulating layer on the peripheral line region, the second protective layer, the first opening and the second opening. The pixel array substrate of claim 17, wherein a dielectric constant of the first protective layer is greater than a dielectric constant of the second protective layer, and a dielectric constant of the second protective layer and a dielectric layer of the second protective layer are The electrical constant is less than 6, greater than one. The pixel array substrate of claim 17, further comprising a dielectric layer formed on the substrate and formed on the thin film transistor, the mark and the insulating layer on the peripheral line region, wherein The dielectric layer is interposed between the second protective layer and the first protective layer, and the second protective layer has a third opening corresponding to the second opening to expose an inner surface of the substrate, and the first A protective layer forms the thin film transistor, the mark, the insulating layer on the peripheral line region, the second protective layer, the first opening, the second opening, and the third opening. The pixel array substrate of claim 19, wherein the dielectric layer has a fourth opening above the mark, the first protective layer is formed on the fourth opening, and the fourth opening is not The first opening, the second opening and the third opening are in communication. The pixel array substrate according to any one of claims 14 to 20, wherein the insulating layer has a dielectric constant of less than 5 and greater than 1. The pixel array substrate of any one of claims 14 to 20, wherein the mark is located at four corners of the substrate, the first opening has two first portions and a second portion, each of the first A portion of the substrate is exposed and has a distance greater than zero from the edge of the substrate. The second portion communicates with each of the first portions and is adjacent to the mark but does not overlap the edge of the substrate. The pixel array substrate of any one of claims 14 to 20, wherein the mark is not located at four corners of the pre-cut area, the first opening has two first portions and a second portion, each The first portion exposes the substrate side And having a distance greater than 0 from the edge of the substrate, the second portion respectively connecting the first portions and adjacent to the mark, but not overlapping the edge of the substrate. The pixel array substrate of any one of claims 14 to 20, wherein the insulating layer comprises a gate insulating layer or a stacked film layer of the gate insulating layer and an etch stop layer. A display panel, comprising: a pixel array substrate according to any one of claims 14 to 20; a pair of substrates; a frame glue disposed between the pixel array substrate and the opposite substrate, wherein The sealant surrounds the display area to form a space, and the sealant is located between the first opening and the display area; and a display medium layer is formed in the space. The display panel of claim 25, further comprising at least one optical spacer disposed between the opposite substrate and the pixel array substrate, and corresponding to the first opening and the substrate edge having a distance greater than 0 .