CN101510530B

CN101510530B - Active element array substrate and manufacturing method therefor

Info

Publication number: CN101510530B
Application number: CN2009101342151A
Authority: CN
Inventors: 孙铭伟; 李振岳; 陈昱丞; 彭佳添
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2009-04-03
Filing date: 2009-04-03
Publication date: 2010-09-15
Anticipated expiration: 2029-04-03
Also published as: CN101510530A

Abstract

The invention discloses an active component array base plate and a manufacture method thereof, the method comprises the following steps: a first patterned semiconductor layer, a grid insulation layer, a first patterned conductor layer and a first dielectric layer stacked in sequence are formed on a base plate. A plurality of first contact windows exposing the first patterned semiconductor layer are formed on the first dielectric layer and the grid insulation layer. A second patterned conductor layer and a second patterned semiconductor layer on the second patterned conductor are formed on the first dielectric layer. The second patterned conductor layer comprises a plurality of contact conductors and bottom electrodes and the second patterned semiconductor layer comprises an active layer. A second dielectric layer with a plurality of contact windows is formed on the first dielectric layer and the partial second contact windows expose the active layer. A third patterned conductor layer electrically connected with the active layer by the partial contact window is formed on the second dielectric layer.

Description

Active component array base board and manufacture method thereof

Technical field

The invention relates to a kind of array of display and manufacture method thereof, and particularly relevant for a kind of active component array base board and manufacture method thereof.

Background technology

Along with the progress of science and technology, also constantly development and its demand grow with each passing day the technology of display.It is early stage that (Cathode Ray Tube CRT) has excellent display quality and technology maturation, therefore monopolizes the monitor market all the year round owing to cathode ray tube.Yet, recently because the rise of environmental protection notion, the big and bigger characteristic of generation amount of radiation of energy resource consumption based on cathode ray tube, cathode ray tube adds that its product flattening space is limited, so can't satisfy the market trend of market for light, thin, short, little, U.S. and low consumpting power.Therefore, frivolous flat-panel screens (Flat Panel Display, FPD) replace the thick and heavy negative electrode crt display of tradition gradually, wherein the LCD of advantageous characteristic such as high image quality, space utilization efficient are good, low consumpting power, low radiation is the main flow in market to have especially.

In recent years, in order to promote the operation ease of display interface between user and the flat-panel screens, perhaps based on promoting considering of flat-panel screens display quality, the setting of OPTICAL SENSORS is integrated in the flat-panel screens.Specifically, OPTICAL SENSORS can be used as the input unit of optical touch control panel (optical touch panel), when the user touched optical touch control panel with finger or other article, the OPTICAL SENSORS that is integrated on the display panels can be responded to the variation of light and export corresponding signal to carry out various functions.In another kind was used, it is interior as ambient light (ambientlight) sensor that OPTICAL SENSORS is integrated in flat-panel screens, and it mainly is a built-in OPTICAL SENSORS in flat-panel screens, uses the power of testing environment light.

Common ambient light detection technology is by low temperature polycrystalline silicon (Low TemperaturePoly-Silicon at present; LTPS) technology forms p-i-n (just mixing/do not mix/negative the doping) OPTICAL SENSORS on the glass substrate of display floater.Yet because process technology limit, this p-i-n OPTICAL SENSORS by LTPS technology made is understood because of polysilicon membrane thickness deficiency, and causes quantum effect (Quantum Effect, i.e. photoelectric conversion efficiency) not good.In addition, the light that backlight sent can pass through glass substrate direct irradiation p-i-n OPTICAL SENSORS, and influences the photobehavior of p-i-n OPTICAL SENSORS, makes signal to noise ratio (the Signal toNoise Ratio of photoreceptor signal; SNR) reduce, cause the measurement result distortion.

In other words, light sensing material as active layers in the OPTICAL SENSORS faces following problems at present: even do not apply a voltage on the electrode of light sensing material both sides, as long as the light sensing material is subjected to the irradiation of light, OPTICAL SENSORS can produce the problem of photoelectric current decay, and then influences the reliability performance of OPTICAL SENSORS.Therefore, usually when making has the active component array base board of OPTICAL SENSORS, the Patternized technique of light sensing material is to utilize different photomask technology to make with the Patternized technique of shading electrode layer in abutting connection with it, so that the size of light sensing material is less than the size of contiguous shading electrode layer.Thus, because the Patternized technique of light sensing material and the technology of active component array base board are incompatible, for the technology of active component array base board with OPTICAL SENSORS, must have more one photomask technology and define the pattern of light sensing material, thereby can't effectively reduce the purpose that technology reaches the cost of manufacture of saving, and cause product competitiveness to descend.

Summary of the invention

The present invention is about a kind of manufacture method of having integrated the active component array base board of OPTICAL SENSORS, and the making of its OPTICAL SENSORS can't additionally increase photomask technology.

The present invention is about a kind of active component array base board of integrating OPTICAL SENSORS, and it can use low cost of manufacture making to have sensing effect active component array base board comparatively accurately.

The present invention proposes a kind of manufacture method of active component array base board, and it comprises the following steps.At first, on a substrate, form first patterned semiconductor layer, gate insulation layer, first patterning conductor layer and first dielectric layer, wherein gate insulation layer covers first patterned semiconductor layer, and first patterning conductor layer is disposed on the gate insulation layer, and first dielectric layer is disposed on the gate insulation layer to cover first patterning conductor layer.In first dielectric layer and gate insulation layer, form a plurality of first contact holes that first patterned semiconductor layer is exposed.In forming second patterning conductor layer on first dielectric layer simultaneously and being positioned at second patterned semiconductor layer on second patterning conductor layer, wherein second patterning conductor layer comprises a plurality of contact conductors and a hearth electrode, and second patterned semiconductor layer comprises that one is positioned at the active layers on the hearth electrode.On first dielectric layer, form second dielectric layer.Form a plurality of second contact holes in second dielectric layer, wherein part second contact hole exposes active layers.Form the 3rd patterning conductor layer on second dielectric layer, wherein part the 3rd patterning conductor layer is electrically connected with active layers by part second contact hole.

In one embodiment of this invention, the formation method of the first above-mentioned patterned semiconductor layer for example comprises the following steps.At first, on substrate, form a plurality of island-shaped pattern (island patterns).Then, in island-shaped pattern, form a plurality of first type doped regions and a plurality of second type doped region.Wherein, the first type doped region for example is a P type doped region, and the second type doped region for example is a N type doped region.Further, P type doped region comprises P type heavily doped region (P-type heavily doping regions), and N type doped region then comprises N type heavily doped region (N-type heavily doping regions) and N type light doping section (N-typelightly doping regions).In addition, can also have a contact interface between the part first type doped region and the second type doped region, and part first contact hole for example exposes described contact interface.

In one embodiment of this invention, above-mentioned second patterning conductor layer and the formation method of second patterned semiconductor layer for example comprise the following steps.At first, on first dielectric layer, form one second conductor layer and second semiconductor layer in regular turn.Then, patterning second conductor layer and second semiconductor layer, with formation hearth electrode and active layers on first dielectric layer, and in to first contact hole of small part, forming the contact conductor.At this moment, part the 3rd patterning conductor layer directly is electrically connected with first patterned semiconductor layer by first contact hole and second contact hole.

In one embodiment of this invention, the manufacture method of active component array base board more comprises the following steps.At first, when forming first contact hole, form a plurality of the 3rd contact holes that first patterning conductor layer is exposed in first dielectric layer, wherein part second contact hole is positioned at first contact hole and the 3rd contact hole top.At this moment, part the 3rd patterning conductor layer for example is directly to be electrically connected with first patterning conductor layer by the 3rd contact hole and second contact hole.In addition, the formation method of second patterning conductor layer and second patterned semiconductor layer for example comprises the following steps.At first, on first dielectric layer, form one second conductor layer and one second semiconductor layer in regular turn.Then, patterning second conductor layer and second semiconductor layer with formation hearth electrode and active layers on first dielectric layer, and form the contact conductor in the 3rd contact hole of first contact hole and part.At this moment, part the 3rd patterning conductor layer is electrically connected with first patterned semiconductor layer indirectly by first patterning conductor layer and second patterning conductor layer.

In one embodiment of this invention, the second above-mentioned patterned semiconductor layer more comprises a plurality of plan semiconductor layers that are positioned on the contact conductor, and the size of wherein intending semiconductor layer for example is less than or equal to the size that contacts conductor.Furthermore, the formation method of second patterning conductor layer and second patterned semiconductor layer can be enumerated the following step.At first, on first dielectric layer, form one second conductor layer, one second semiconductor layer and a patterning photoresist layer in regular turn.Afterwards, be mask with the patterning photoresist layer, patterning second conductor layer and second semiconductor layer are to form hearth electrode, active layers, contact conductor and to intend semiconductor layer.Then, active layers and plan semiconductor layer are carried out the side direction etching, so that intend the size of the size of semiconductor layer less than the contact conductor, and make the size of the size of active layers less than hearth electrode.And the 3rd above-mentioned patterning conductor layer is electrically connected with first patterned semiconductor layer by part second contact hole and second patterning conductor layer.

In one embodiment of this invention, above-mentioned part the 3rd patterning conductor layer directly is electrically connected with first patterning conductor layer by the 3rd contact hole and second contact hole.

In one embodiment of this invention, above-mentioned second patterning conductor layer and the formation method of second patterned semiconductor layer comprise the following steps.At first, on first dielectric layer, form second conductor layer, second semiconductor layer and patterning photoresist layer in regular turn, wherein the patterning photoresist layer for example is covered on the subregion of second semiconductor layer, and the patterning photoresist layer has first block and one second block, and the thickness of first block is greater than the thickness of second block, and first block is corresponding to the active layers top.Afterwards, be mask with the patterning photoresist layer, patterning second conductor layer and second semiconductor layer are to form hearth electrode, active layers and contact conductor.

In one embodiment of this invention, on to be set forth in second dielectric layer method that forms second contact hole for example be prior to forming the patterning photoresist layer on second dielectric layer, wherein the patterning photoresist layer is covered on the subregion of second semiconductor layer, and the patterning photoresist layer has one first block and one second block, and the thickness of first block is greater than the thickness of second block, and second block is corresponding to the active layers top.Then, be mask with the patterning photoresist layer again, patterning second dielectric layer is to form second contact hole.

In one embodiment of this invention, on to be set forth in second dielectric layer method that forms second contact hole for example be earlier second dielectric layer to be formed the patterning photoresist layer, wherein the patterning photoresist layer is covered on the subregion of second semiconductor layer, and the patterning photoresist layer has one first block and one second block, and the thickness of first block is greater than the thickness of second block, and second block is corresponding to the active layers top.Then, make patterning second dielectric layer form second contact hole.

In one embodiment of this invention, the 3rd above-mentioned patterning conductor layer is electrically connected with first patterned semiconductor layer by part second contact hole and second patterning conductor layer.

In one embodiment of this invention, above-mentioned part the 3rd patterning conductor layer directly is electrically connected with first patterning conductor layer by the 3rd contact hole and second contact hole.Or above-mentioned part the 3rd patterning conductor layer is electrically connected with first patterning conductor layer indirectly by the second graphical conductor layer in the 3rd contact hole and second contact hole.

In one embodiment of this invention, the manufacture method of above-mentioned active component array base board more is included in when forming first patterned semiconductor layer, forms first light shield layer on substrate.

In one embodiment of this invention, the manufacture method of above-mentioned active component array base board more is included in when forming first patterning conductor layer, forms second light shield layer on gate insulation layer.

In one embodiment of this invention, the manufacture method of above-mentioned active component array base board, more be included in when forming above-mentioned part the 3rd patterning conductor layer and directly being electrically connected with first patterned semiconductor layer by first contact hole and second contact hole, first contact hole on every side by second dielectric layer around.

In one embodiment of this invention, the manufacture method of above-mentioned active component array base board, more be included in when forming above-mentioned part the 3rd patterning conductor layer and directly being electrically connected with first patterning conductor layer by the 3rd contact hole and second contact hole, the 3rd contact hole on every side by second dielectric layer around.

The present invention proposes a kind of manufacture method of active component array base board in addition, and it comprises the following steps.At first, form first patterned semiconductor layer and gate insulation layer on a substrate, wherein gate insulation layer covers first patterned semiconductor layer.Afterwards, in forming first patterning conductor layer on the gate insulation layer simultaneously and being positioned at second patterned semiconductor layer on first patterning conductor layer, wherein first patterning conductor layer comprises a plurality of grids and a hearth electrode, and second patterned semiconductor layer comprises that one is positioned at the active layers on the hearth electrode.Then, on gate insulation layer, form first dielectric layer, to cover first patterning conductor layer.Afterwards, in first dielectric layer and gate insulation layer, form a plurality of first contact holes that first patterned semiconductor layer is exposed.Continue it, form second patterning conductor layer on first dielectric layer, wherein second patterning conductor layer comprises a plurality of contact conductors that are positioned at first contact hole.Afterwards, on first dielectric layer, form second dielectric layer.Then, form a plurality of second contact holes in second dielectric layer, wherein part second contact hole is positioned at the active layers top, and forms the 3rd contact hole in first dielectric layer.Afterwards, form the 3rd patterning conductor layer on second dielectric layer, wherein part the 3rd patterning conductor layer is electrically connected with active layers by part second contact hole and the 3rd contact hole.

In one embodiment of this invention, the formation method of above-mentioned first patterned semiconductor layer comprises the following steps.At first, on substrate, form a plurality of island-shaped pattern (island patterns).Then, in island-shaped pattern, form a plurality of first type doped regions and a plurality of second type doped region.Wherein, the first type doped region is a P type doped region, and the second type doped region is a N type doped region.Further, P type doped region comprises P type heavily doped region (P-type heavily doping regions), and N type doped region comprises N type heavily doped region (N-type heavily doping regions) and N type light doping section (N-type lightly dopingregions).In addition, can also have a contact interface between the part first type doped region and the second type doped region, and part first contact hole for example exposes described contact interface.

In one embodiment of this invention, the formation method of above-mentioned first patterning conductor layer and second patterned semiconductor layer for example is prior to forming one first conductor layer and one second semiconductor layer on the gate insulation layer in regular turn.Follow patterning first conductor layer and second semiconductor layer again, on gate insulation layer, to form hearth electrode and active layers.At this moment, part the 3rd patterning conductor layer for example is directly to be electrically connected with first patterned semiconductor layer by first contact hole and second contact hole.

In one embodiment of this invention, the manufacture method of above-mentioned active component array base board more is included in when forming first contact hole, form a plurality of the 3rd contact holes with exposure of first patterning conductor layer or the exposure of second patterned semiconductor in first dielectric layer, wherein part second contact hole is positioned at first contact hole and the 3rd contact hole top.At this moment, part the 3rd patterning conductor layer for example is directly to be electrically connected with first patterning conductor layer by the 3rd contact hole and second contact hole, and part the 3rd patterning conductor layer for example is by the 3rd contact hole and is positioned at second patterning conductor layer of second contact hole and is electrically connected with first patterning conductor layer.

In one embodiment of this invention, above-mentioned the 3rd patterning conductor layer is electrically connected with first patterned semiconductor layer by part second contact hole and second patterning conductor layer.

In one embodiment of this invention, the formation method of above-mentioned first patterning conductor layer and second patterned semiconductor layer comprises the following steps.At first, on gate insulation layer, form first conductor layer, second semiconductor layer and patterning photoresist layer in regular turn, wherein photoresist layer is covered on the subregion of second semiconductor layer, and photoresist layer has one first district and one second block, and the thickness of first block is greater than the thickness of second block, and first block is corresponding to the active layers top.Then, be mask with the patterning photoresist layer, patterning first conductor layer and second semiconductor layer are to form hearth electrode, active layers, grid and to intend semiconductor layer.

In one embodiment of this invention, above-mentioned second patterned semiconductor layer more comprises a plurality of plan semiconductor layers that are positioned on the grid, and the size of wherein intending semiconductor layer for example is to be less than or equal to the size that contacts conductor.In addition, the formation method of first patterning conductor layer and second patterned semiconductor layer comprises the following steps.At first, on gate insulation layer, form first conductor layer, second semiconductor layer and patterning photoresist layer in regular turn.Then, be mask with the patterning photoresist layer, patterning first conductor layer and second semiconductor layer are to form hearth electrode, active layers, grid and to intend semiconductor layer.Afterwards, active layers and plan semiconductor layer are carried out the side direction etching, so that intend the size of the size of semiconductor layer less than grid, and make the size of the size of active layers less than hearth electrode.

In one embodiment of this invention, the manufacture method of above-mentioned active component array base board, more be included in when forming above-mentioned part the 3rd patterning conductor layer and directly being electrically connected with first patterned semiconductor layer by first contact hole and second contact hole, the 3rd contact hole on every side by second dielectric layer around.

The present invention proposes a kind of active component array base board, and this active component array base board comprises substrate, first patterned semiconductor layer, gate insulation layer, first patterning conductor layer, first dielectric layer, second patterning conductor layer, second patterned semiconductor layer, second dielectric layer and the 3rd patterning conductor layer.Wherein, first patterned semiconductor layer is disposed on the substrate, gate insulation layer is disposed on the substrate to cover first patterned semiconductor layer, first patterning conductor layer is disposed on the gate insulation layer, first dielectric layer is disposed on the gate insulation layer to cover first patterning conductor layer, wherein first dielectric layer and gate insulation layer have a plurality of first contact holes that first patterned semiconductor layer is exposed, second patterning conductor layer is disposed on first dielectric layer, wherein second patterning conductor layer comprises a plurality of contact conductors and a hearth electrode, second patterned semiconductor layer is disposed on second patterning conductor layer, wherein second patterned semiconductor layer comprises that one is positioned at the active layers on the hearth electrode, second dielectric layer is disposed on first dielectric layer, wherein second dielectric layer has a plurality of second contact holes so that active layers is exposed, and the 3rd patterning conductor layer, be disposed on second dielectric layer, wherein part the 3rd patterning conductor layer is electrically connected with active layers by part second contact hole.

In one embodiment of this invention, above-mentioned active component array base board more comprises first light shield layer that is disposed on the substrate.

In one embodiment of this invention, above-mentioned active component array base board more comprises second light shield layer that is disposed on first dielectric layer.

In one embodiment of this invention, above-mentioned first patterned semiconductor layer comprises a plurality of island-shaped pattern, and the part island-shaped pattern has a plurality of first type doped regions, and the part island-shaped pattern has a plurality of second type doped regions.Wherein, the first type doped region is a P type doped region, and the second type doped region is a N type doped region.Furthermore, P type doped region comprises P type heavily doped region (P-type heavily doping regions), and N type doped region comprises N type heavily doped region (N-type heavily doping regions) and N type light doping section (N-type lightly doping regions).In addition, can also have a contact interface between the part first type doped region and the second type doped region, and part first contact hole for example exposes described contact interface.

In one embodiment of this invention, above-mentioned contact conductor is arranged in first contact hole to small part.

In one embodiment of this invention, part the 3rd patterning conductor layer directly is electrically connected with first patterned semiconductor layer by first contact hole and second contact hole.And part the 3rd patterning conductor layer directly is electrically connected with first patterning conductor layer by the 3rd contact hole and second contact hole.

In one embodiment of this invention, above-mentioned contact conductor is arranged in the 3rd contact hole of first contact hole and part.Wherein, part the 3rd patterning conductor layer for example is directly to be electrically connected with first patterning conductor layer by the 3rd contact hole and second contact hole, or part the 3rd patterning conductor layer for example is to be electrically connected with first patterning conductor layer indirectly by second graphical conductor layer in the 3rd contact hole and second contact hole.And part the 3rd patterning conductor layer for example is to be electrically connected with first patterned semiconductor layer indirectly by first patterning conductor layer and second patterning conductor layer.

In one embodiment of this invention, above-mentioned contact conductor is arranged in the 3rd contact hole of first contact hole and part.Wherein, part the 3rd patterning conductor layer for example is directly to be electrically connected with first patterning conductor layer by the 3rd contact hole and second contact hole, or part the 3rd patterning conductor layer for example is to be electrically connected with first patterning conductor layer indirectly by second graphical conductor layer in the 3rd contact hole and second contact hole.And part the 3rd patterning conductor layer is electrically connected with first patterned semiconductor layer by part second contact hole and second patterning conductor layer.

In one embodiment of this invention, above-mentioned second patterned semiconductor layer more comprises a plurality of plan semiconductor layers that are positioned on the contact conductor.Wherein, the size of plan semiconductor layer for example is to be less than or equal to the size that contacts conductor.

In one embodiment of this invention, above-mentioned active component array base board, more be included in when forming above-mentioned part the 3rd patterning conductor layer and directly being electrically connected with first patterned semiconductor layer by first contact hole and second contact hole, the 3rd contact hole on every side by second dielectric layer around.

In one embodiment of this invention, above-mentioned active component array base board, more be included in when forming above-mentioned part the 3rd patterning conductor layer and directly being electrically connected with first patterning conductor layer by the 3rd contact hole and second contact hole, the 3rd contact hole on every side by second dielectric layer around.

The present invention proposes a kind of active component array base board, and this active component array base board comprises substrate, first patterned semiconductor layer, gate insulation layer, first patterning conductor layer, second patterned semiconductor layer, first dielectric layer, second patterning conductor layer, second dielectric layer and the 3rd patterning conductor layer.First patterned semiconductor layer is disposed on the substrate.Gate insulation layer is disposed on the substrate, and wherein gate insulation layer covers first patterned semiconductor layer.First patterning conductor layer comprises a plurality of grids and a hearth electrode.Second patterned semiconductor layer is disposed on first patterning conductor layer, and wherein second patterned semiconductor layer comprises that one is positioned at the active layers on the hearth electrode.First dielectric layer is disposed on the gate insulation layer, and to cover first patterning conductor layer, wherein first dielectric layer and gate insulation layer have a plurality of first contact hole and one the 3rd contact holes that first patterned semiconductor layer is exposed.Second patterning conductor layer is disposed on first dielectric layer, and wherein second patterning conductor layer comprises a plurality of contact conductors that are positioned at first contact hole.Second dielectric layer is disposed on first dielectric layer, and wherein second dielectric layer has a plurality of second contact holes, and part second contact hole is positioned at the active layers top.The 3rd patterning conductor layer is disposed on second dielectric layer, and wherein part the 3rd patterning conductor layer is electrically connected with active layers by part second contact hole and the 3rd contact hole.

In one embodiment of this invention, above-mentioned part the 3rd patterning conductor layer directly is electrically connected with first patterned semiconductor layer by first contact hole and second contact hole.

In one embodiment of this invention, said first dielectric layer has a plurality of the 3rd contact holes that first patterning conductor layer is exposed, and part second contact hole is positioned at the 3rd contact hole top.At this moment, part the 3rd patterning conductor layer can be directly to be electrically connected with first patterning conductor layer by the 3rd contact hole and second contact hole.Certainly, part the 3rd patterning conductor layer also can be by the 3rd contact hole and be positioned at second patterning conductor layer of second contact hole and be electrically connected with first patterning conductor layer.

In one embodiment of this invention, above-mentioned the 3rd patterning conductor layer is electrically connected with active layers by part second contact hole and second patterning conductor layer.

In one embodiment of this invention, above-mentioned second patterned semiconductor layer more comprises a plurality of plan semiconductor layers that are positioned on the grid.Wherein, the size of plan semiconductor layer for example is to be less than or equal to the size that contacts conductor.

In one embodiment of this invention, above-mentioned active component array base board comprises that more one is disposed at first light shield layer on the substrate.

Based on above-mentioned, because the manufacture method of active array substrate of the present invention is that the active layers and the hearth electrode of OPTICAL SENSORS are made in the lump, active layers can be used with photomask technology with second patterning conductor layer or first patterning conductor layer with hearth electrode and make, and process compatibility height with active component array base board, the photomask manufacturing cost can be additionally do not increased, cost of manufacture can be saved.And in part embodiment, additionally do not increasing under the situation of photomask number, the size of hearth electrode can promote the sensing usefulness of OPTICAL SENSORS greater than the size of active layers under identical photomask technology.

Description of drawings

Fig. 1 illustrates a kind of active component array base board according to the first embodiment of the present invention.

Fig. 2 A～Fig. 2 G illustrates the technology of a kind of active component array base board of the first embodiment of the present invention in regular turn.

Fig. 2 A '～Fig. 2 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 2A～Fig. 2 G and pad zone.

Fig. 2 H illustrates the schematic diagram of the another kind of active component array base board of the first embodiment of the present invention.

Fig. 3 illustrates a kind of active component array base board according to the second embodiment of the present invention.

Fig. 4 A～Fig. 4 G illustrates the technology of a kind of active component array base board of the second embodiment of the present invention in regular turn.

Fig. 4 A '～Fig. 4 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 4A～Fig. 4 G and pad zone.

Fig. 4 H illustrates the schematic diagram of the another kind of active component array base board of the second embodiment of the present invention.

Fig. 5 illustrates a kind of active component array base board according to the third embodiment of the present invention.

Fig. 6 A～Fig. 6 G illustrates the technology of a kind of active component array base board of the third embodiment of the present invention in regular turn.

Fig. 6 A '～Fig. 6 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 6A～Fig. 6 G and pad zone.

Fig. 6 H illustrates the schematic diagram of the another kind of active component array base board of the third embodiment of the present invention.

Fig. 7 A～Fig. 7 D is the making schematic flow sheet of a kind of formation second patterning conductor layer and second patterned semiconductor layer.

Fig. 8 illustrates a kind of active component array base board according to the fourth embodiment of the present invention.

Fig. 9 A～Fig. 9 G illustrates the technology of a kind of active component array base board of the third embodiment of the present invention in regular turn.

Fig. 9 A '～Fig. 9 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 9A～Fig. 9 G and pad zone.

Fig. 9 H illustrates the schematic diagram of the another kind of active component array base board of the fourth embodiment of the present invention.

Figure 10 A～Figure 10 D is a kind of making schematic flow sheet that forms second contact hole of different depth.

Figure 11 illustrates a kind of active component array base board according to the fifth embodiment of the present invention.

Figure 12 A～Figure 12 G illustrates the technology of a kind of active component array base board of the fifth embodiment of the present invention in regular turn.

Figure 12 A '～Figure 12 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 12A～Figure 12 G and pad zone.

Figure 12 H illustrates the schematic diagram of the another kind of active component array base board of the fifth embodiment of the present invention.

Figure 13 A～Figure 13 D is the making schematic flow sheet of a kind of formation second patterning conductor layer and second patterned semiconductor layer.

Figure 14 illustrates a kind of active component array base board according to the sixth embodiment of the present invention.

Figure 15 A～Figure 15 G illustrates the technology of a kind of active component array base board of the sixth embodiment of the present invention in regular turn.

Figure 15 A '～Figure 15 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 15A～Figure 15 G and pad zone.

Figure 15 H illustrates the schematic diagram of the another kind of active component array base board of the sixth embodiment of the present invention.

Drawing reference numeral

200,300,400,500,600,700: active component array base board

200A, 700A: pixel region

200B, 700B: sensing area

200C, 700C: pad zone

210,710: substrate

220,720: the first patterned semiconductor layer

220a: the first type doped region

220b: the second type doped region

222,242,722,746: storage electrode

224s: source doping region

224d: drain doped region

224c: channel region

224e: the shallow doped region of source electrode

224f: the shallow doped region of drain

226: the first light shield layers

230,730: gate insulation layer

240,740: the first patterning conductor layer

244,746: grid

246: the second light shield layers

248,748: the first soldering pad layers

249: bridged electrodes

250,760: the first dielectric layers

260,770: the second patterning conductor layer

262,772: the contact conductor

264,742: hearth electrode

270,750: the second patterned semiconductor layer

272,752: active layers

274,754: intend semiconductor layer

280,780: the second dielectric layers

290,790: the three patterning conductor layer

292: pixel electrode

294,794: top electrode

298,798: the second soldering pad layers

410,510,610: the patterning photoresist layer

410A, 410A ', 510A: first block

410B, 510B: second block

H1: first contact hole

H2: second contact hole

H3: the 3rd contact hole

Embodiment

For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.

First embodiment:

Fig. 1 illustrates a kind of active component array base board according to the first embodiment of the present invention, and wherein for making graphic expression comparatively simple and clear, quantity may be represented for a plurality of elements may only illustrate one in Fig. 1.And, for convenience of description, active component array base board can be divided into as the pixel region 200A among Fig. 1, sensing area 200B and pad zone 200C.Have active member in the pixel region 200A, and in the present embodiment, the active member in the pixel region 200A can be in conjunction with a storage capacitors, so that preferable display effect to be provided in order to the control show state.

Please refer to Fig. 1, active component array base board 200 comprises substrate 210, first patterned semiconductor layer 220, gate insulation layer 230, first patterning conductor layer 240, first dielectric layer 250, second patterning conductor layer 260, second patterned semiconductor layer 270, second dielectric layer 280 and the 3rd patterning conductor layer 290.As shown in Figure 1, first patterned semiconductor layer 220 is disposed on the substrate 210, and first patterned semiconductor layer 220 is made of a plurality of island-shaped pattern S, and wherein the material of first patterned semiconductor layer 220 can be polysilicon (polysilicon), or other semi-conducting materials.The alternative buffer dielectric layer that forms between the substrate 210 and first patterned semiconductor layer 220.

In the present embodiment, the part island-shaped pattern S in pixel region 200A for example has a plurality of first type doped region 220a, and as the storage electrode 222 of storage capacitors, wherein the first type doped region 220a for example is a P type doped region.Yi Bufen island-shaped pattern S for example has a plurality of second type doped region 220b in addition, for example the first type doped region 220a is different with the composition of the second type doped region 220b, the second type doped region 220b has as the source doping region 224s of active member and drain doped region 224d, wherein the second type doped region 220b for example is a N type doped region, and first patterned semiconductor layer 220 between source doping region 224s and drain doped region 224d constitutes channel region 224c.In addition, in the island-shaped pattern S of active member, optionally make dopant species identical but shallow doped region 224e of source electrodes that doping content is different and the shallow doped region 224f of drain, for example, source doping region 224s and drain doped region 224d for example are N type heavily doped regions, and shallow doped region 224e of source electrode and the shallow doped region 224f of drain for example are N type light doping sections.Certainly, source doping region 224s and drain doped region 224d can comply with electrical demand, exchange its name each other, and the admixture kind of the first type doped region 220a and the second type doped region 220b is also interchangeable, also together, the present invention is not as limit for shallow doped region 224e of source electrode and the shallow doped region 224f of drain.In addition, influence the sensing sensitivity of OPTICAL SENSORS for fear of unexpected irradiate light OPTICAL SENSORS, can in the sensing area 200B of active component array base board 200, optionally form first light shield layer 226 that is disposed on the substrate 210 with first patterned semiconductor layer 220, wherein the material of first light shield layer 226 can be intrinsic semiconductor (intrinsic semiconductor), P type doped semiconductor or N type doped semiconductor, and wherein semiconductor comprises amorphous silicon, polysilicon or monocrystalline silicon layer.

Please refer to Fig. 1, gate insulation layer 230 is disposed on the substrate 210 covering first patterned semiconductor layer 220, and gate insulation layer 230 is made of dielectric material.First patterning conductor layer 240 is disposed on the gate insulation layer 230, and in the present embodiment, first patterning conductor layer 240 can be divided into the grid 244 that constitutes active member, the storage electrode 242 that constitutes storage capacitors and first soldering pad layer 248 that is positioned at pad zone 200C, wherein storage electrode 242, grid 244 and first soldering pad layer 248 are similarly conductive material, grid 244 is positioned on the gate insulation layer 230 of channel region 224c top, and storage electrode 242 is positioned on the gate insulation layer 230 of storage electrode 222 tops.In addition, influence the running of OPTICAL SENSORS for fear of unexpected light, second light shield layer 246 can also be set on the gate insulation layer among the sensing area 200B 230, and for example, second light shield layer 246 can form simultaneously with storage electrode 242, grid 244 and first soldering pad layer 248.

Please continue with reference to figure 1, first dielectric layer 250 is disposed on the gate insulation layer 230 to cover first patterning conductor layer 240, in pixel region 200A, first dielectric layer 250 has a plurality of first contact hole H1 that first patterned semiconductor layer 220 is exposed with gate insulation layer 230, and in the present embodiment, first dielectric layer 250 can also form a plurality of the 3rd contact hole H3 in pad zone 200C, to expose first soldering pad layer 248 of first patterning conductor layer 240.Second patterning conductor layer 260 is disposed on first dielectric layer 250, wherein second patterning conductor layer 260 comprises that a plurality of contact conductors 262 and are arranged in the hearth electrode 264 of sensing area 200B, and contact conductor 262 is positioned to the first contact hole H1 of small part and is couple to pairing part first patterned semiconductor layer 220 to pass first dielectric layer 250 with gate insulation layer 230, shown in the leftmost first contact hole H1 among Fig. 1, in the present embodiment, contact conductor 262 for example is directly to be connected with source doping region 224s.

Refer again to Fig. 1, second patterned semiconductor layer 270 is disposed on second patterning conductor layer 260, and wherein second patterned semiconductor layer 270 comprises that one is positioned at the active layers 272 on the hearth electrode 264, in order to produce corresponding photoelectric current according to extraneous light.Active layers 272 for example is the dielectric layer of amorphous silicon layer, polysilicon layer, monocrystalline silicon layer or Silicon-rich.Second dielectric layer 280 is disposed on first dielectric layer 250, wherein second dielectric layer 280 has a plurality of second contact hole H2 so that active layers 272 is exposed, and the 3rd patterning conductor layer 290 is disposed on second dielectric layer 280, wherein part the 3rd patterning conductor layer 290 is electrically connected with active layers 272 by the part second contact hole H2, the material of the 3rd patterning conductor layer 290 can be used has high penetration and low resistivity materials, for example indium tin oxide (ITO) or indium-zinc oxide (IZO).In detail, part the 3rd patterning conductor layer 290 passes that second dielectric layer 280 contacts with active layers 272 and as the top electrode 294 of OPTICAL SENSORS.As shown in Figure 1, the formed OPTICAL SENSORS of sensing area 200B of present embodiment comprises the hearth electrode 264 that is positioned on first dielectric layer 250, is positioned at the active layers 272 on the hearth electrode 264, and passes second dielectric layer 280 and the top electrode 294 that contacts with active layers 272.

What deserves to be mentioned is that top electrode 294 or hearth electrode 264 can be electrically connected signal read circuit, in order to read the luminous intensity that active layers 272 is sensed.In the present embodiment, hearth electrode 264 for example is to be formed by identical conductor layer patterning with contact conductor 262 as source electrode, and top electrode 294 for example is to be formed by the 3rd conductor layer patterning with pixel electrode 292 equally.In addition, active layers 272 for example is the dielectric layer of amorphous silicon layer, polysilicon layer, monocrystalline silicon layer or Silicon-rich, and silicic dielectric layer adopts relevant chemical vapor deposition process to form on making, utilize technological parameter control, be gas ratio for example, reach excessive silicone content, make silicone content surpass proper chemical ratios (chemical equivalent), and form silicic dielectric layer.The actual material that is suitable for for example is the silicon oxide layer of hydrogenation Silicon-rich (Hydrogen-Silicon rich oxide, H-SRO), the silicon nitride layer of hydrogenation Silicon-rich (Hydrogen-Silicon rich nitride, H-SRN), the oxide layer of Silicon-rich (Silicon rich oxide, SRO) and the nitration case of Silicon-rich (Silicon rich nitride, SRN).Yet active layers 272 of the present invention is not limited to above-mentioned material, also can select for use other Silicon-rich compounds to substitute.

In addition, in the present embodiment, optionally the substrate 210 in hearth electrode 264 belows is provided with first light shield layer 226, or second light shield layer 246 is set on the gate insulation layer 230 of hearth electrode 264 belows, the influence of covering unexpected light by first light shield layer 226 or second light shield layer 246 is in order to improve the sensing sensitivity of OPTICAL SENSORS.In the present embodiment, first light shield layer 226 for example is to be formed by the first identical semiconductor layer patternization with the first type doped region 220a of active member and the storage electrode 222 of storage capacitors, just so-called first patterned semiconductor layer 220, and second light shield layer 246 for example is to be formed by the first conductor layer patterning with the grid 244 of active member and the storage electrode 222 of storage capacitors equally.Second light shield layer 246 is aimed at (align with) in first light shield layer 226, and wherein the area of first light shield layer 226 is more than or equal to the area of second light shield layer 246, and the area of second light shield layer 246 is more than or equal to the area of hearth electrode 264.

Please continue with reference to figure 1, the part second contact hole H2 is corresponding to the first contact hole H1, so that the pixel electrode in the 3rd patterning conductor layer 290 292 can directly be electrically connected with active member and storage electrode 222 by the first contact hole H1 and the second contact hole H2, in other words, pixel electrode 292 passes second dielectric layer 280, first dielectric layer 250 and gate insulation layer 230 and downwards electric property coupling to first patterned semiconductor layer 220, in the present embodiment, pixel electrode 292 for example is the drain doped region 224d that directly is couple to first patterned semiconductor layer 220, and pixel electrode 292 also directly passes second dielectric layer 280, first dielectric layer 250 and gate insulation layer 230 and be couple to storage electrode 222.As shown in Figure 1, storage electrode 222 is electrically connected to drain doped region 224d via pixel electrode 292, in other words, the storage electrode 222 that is positioned at gate insulation layer 230 belows and pixel electrode 292 be equipotential in fact, therefore in the present embodiment, storage electrode 222, gate insulation layer 230, storage electrode 242, first dielectric layer 250, second dielectric layer 280 and pixel electrode 292 can constitute the storage capacitors (multi-layered storage capacitor) of a sandwich construction jointly, and the visual Demand Design of actual panel is simple layer or multilayer storage capacitors.

In addition, in the pad zone 200C of present embodiment, the part second contact hole H2 corresponding to the 3rd contact hole H3 to expose first soldering pad layer 248 of first patterning conductor layer 240, second soldering pad layer 298 directly is electrically connected with first soldering pad layer 248 of first patterning conductor layer 240 by the 3rd contact hole H3 and the second contact hole H2, in other words, second soldering pad layer 298 pass second dielectric layer 280 and first dielectric layer 250 and downwards electric property coupling to first soldering pad layer 248.In the present embodiment, weld pad mainly is made of jointly first

patterning conductor layer

240 and 290 of the 3rd patterning conductor layer.

For further specifying technology contents of the present invention, Fig. 2 A～Fig. 2 G that hereinafter more arranges in pairs or groups illustrates the manufacture method of the active component array base board 200 of present embodiment.

Please refer to Fig. 2 A～Fig. 2 G, it illustrates the technology of a kind of active component array base board of the first embodiment of the present invention in regular turn, wherein illustrates pixel region 200A, sensing area 200B and the top view of pad zone 200C when each step of active component array base board 200 among Fig. 2 A～Fig. 2 G respectively.Fig. 2 A '～Fig. 2 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 2A～Fig. 2 G and pad zone.

At first, shown in Fig. 2 A and Fig. 2 A ', provide substrate 210, and on substrate 210, form first patterned semiconductor layer 220.Substrate 210 for example is glass substrate 210 or plastic substrate 210, divides a pixel region 200A, a sensing area 200B and a pad zone 200C on it at least, and relevant configuration is as indicated above.First patterned semiconductor layer 220 for example is polysilicon layer (first semiconductor layer), can form through quasi-molecule laser annealing technology by the amorphous silicon material layer, and polysilicon layer forms a plurality of island-shaped pattern S that are positioned at pixel region 200A behind patterning, part island-shaped pattern S constitutes the semiconductor block 224 as active member, and part island-shaped pattern S constitutes the storage electrode 222 of storage capacitors.And form a gate insulation layer 230 on substrate 210, make it cover semiconductor block 224 and storage electrode 222, wherein gate insulation layer 230 is made of dielectric material.In addition, in order to make the sensing usefulness of OPTICAL SENSORS more excellent, can also on the substrate among the sensing area 200B 210, utilize first patterned semiconductor layer 220 to form first light shield layer 226.

Then, shown in Fig. 2 B and Fig. 2 B ', storage electrode 222 to described storage capacitors carries out the doping of first type and constitutes the first type doped region 220a, and wherein the doping of first type for example is P type (P+) ion doping, makes storage electrode 222 have P type admixture (dopants).More specifically, formation one exposes the patterned mask (not illustrating) of storage electrode 222 on substrate 210, and the polysilicon layer that described patterned mask exposed is carried out first type to mix, for example be P type (P+) ion doping, can make storage electrode 222 have good electrical conductivity by the P+ ion doping.

Then, shown in Fig. 2 C and Fig. 2 C ', on gate insulation layer 230, form one first conductor layer (not illustrating), and first conductor layer (not illustrating) is carried out patterning, and form first patterning conductor layer that is mainly constituted by grid 244, storage electrode 242 and first soldering pad layer 248.Afterwards, second type that the zones of different of semiconductor region piece 224 is carried out different dopant concentrations mixes, and for example is that N type (N+) ion doping and N type (N-) shallow ion mix.Specifically, after second type doping of the zones of different of semiconductor block 224 via variable concentrations, two ends by semiconductor block 224 can be divided into N type heavily doped region in regular turn toward central authorities, N type light doping section and intrinsic region, wherein the N type heavily doped region at semiconductor block 224 two ends forms source doping region 224s and drain doped region 224d respectively, intrinsic region between N type heavily doped region forms channel region 224c, and the N type light doping section between source doping region 224s and channel region 224c forms the shallow doped region 224e of source electrode, and the N type light doping section between drain doped region 224d and channel region 224c forms the shallow doped region 224f of drain.In addition, in order further to promote the sensing usefulness of OPTICAL SENSORS, optionally utilize first patterning conductor layer 240 to form second light shield layer 246 on the gate insulation layer 230 above first light shield layer 226 in sensing area 200B, and in the present embodiment, second light shield layer 246 and first light shield layer 226 overlap, the area of second light shield layer 246 can be smaller or equal to the area of first light shield layer 226, and the area of second light shield layer 246 is more than or equal to the area of hearth electrode 264 (Fig. 2 E～Fig. 2 E ').

Then, shown in Fig. 2 D and Fig. 2 D ', on gate insulation layer 230, form one first dielectric layer 250, to cover first patterning conductor layer 240.And, in first dielectric layer 250 and gate insulation layer 230, form a plurality of first contact hole H1, exposing source doping region 224s, the drain doped region 224d in first patterned semiconductor layer 220 respectively, and storage electrode 222.What deserves to be mentioned is, in the present embodiment, when forming the first contact hole H1, more in first dielectric layer 250, form a plurality of the 3rd contact hole H3 that first soldering pad layer 248 of first patterning conductor layer 240 is exposed.More specifically, first dielectric layer 250 for example is to utilize ion chemistry vapor deposition method or other suitable film deposition techniques to form, and its material for example is dielectric materials such as silica, silicon nitride, silicon oxynitride or its combination.

Then, shown in Fig. 2 E and Fig. 2 E ', on first dielectric layer 250, form one second conductor layer (not illustrating) and second semiconductor layer (not illustrating) in regular turn.Then, patterning second conductor layer (not illustrating) and second semiconductor layer (not illustrating), on first dielectric layer 250 of sensing area 200B, to form hearth electrode 264 and active layers 272, and in pixel region 200A form contact conductor 262 to the first contact hole H1 of small part, wherein contact conductor 262 and pass the first contact hole H1 and directly contact with source doping region 224s.More specifically, the material of second patterning conductor layer 260 for example is an aluminium (Al), molybdenum (Mo), titanium (Ti), neodymium (Nd), above-mentioned nitride such as molybdenum nitride (MoN), titanium nitride (TiN), it is laminated, above-mentioned alloy or other electric conducting materials, and the material of second patterned semiconductor layer 270 can be according to the luminous sensitivity of OPTICAL SENSORS, demands such as reliability and adjust material, as amorphous silicon layer, polysilicon layer, the dielectric layer of monocrystalline silicon layer or Silicon-rich etc., and silicic dielectric layer for example is to adopt ion chemistry vapor deposition process or other suitable film deposition techniques to form on making, utilize technological parameter control, be gas ratio for example, reach excessive silicone content in the film, make silicone content surpass proper chemical ratios (chemical equivalent), and form silicic dielectric layer.The actual material that is suitable for can be enumerated the silicon oxide layer of hydrogenation Silicon-rich, the silicon nitride layer of hydrogenation Silicon-rich, the oxide layer of Silicon-rich and the nitration case of Silicon-rich.It should be noted that, be different from known, in the OPTICAL SENSORS of the present invention as contacting conductor 262 for forming simultaneously in light sensing material active layers 272 and the active member, can reduce photomask technology one, and the complexity of reduction technology, so second patterned semiconductor layer 270 is all arranged on second patterned conductor 260.

Then, shown in Fig. 2 F and Fig. 2 F ', on first dielectric layer 250, form second dielectric layer 280 and for example can select no based material layer or organic material layers such as similar silica, silicon nitride for use, but wherein the organic material layer double as is a flatness layer to cover contact conductor 262, the second dielectric layers 280.And, in second dielectric layer 280, form a plurality of second contact hole H2, wherein the part second contact hole H2 exposes the active layers 272 among the sensing area 200B, and in the present embodiment, the part second contact hole H2 that is arranged in pixel region 200A is corresponding to the first contact hole H1, and exposes the drain doped region 224d of active member and the storage electrode 222 of storage capacitors respectively.Simultaneously, the part second contact hole H2 that is arranged in pad zone 200C is corresponding to the 3rd contact hole H3, and exposes first soldering pad layer 248 of weld pad.

Afterwards, shown in Fig. 2 G and Fig. 2 G ', on second dielectric layer 280, form the 3rd conductor layer, and the 3rd conductor layer carried out patterning, to form the 3rd patterning conductor layer 290 that is made of pixel electrode 292, top electrode 294 and second soldering pad layer 298, wherein part the 3rd patterning conductor layer 290 is electrically connected with active layers 272 by the part second contact hole H2.The material of the 3rd conductor layer for example is indium tin oxide (ITO), indium-zinc oxide (IZO) or other electrically conducting transparent materials.Pixel electrode 292 directly is electrically connected with the drain doped region 224d of first patterned semiconductor layer 220 by the first contact hole H1 and the second contact hole H2, and pixel electrode 292 also directly is electrically connected with storage electrode 222 by the first contact hole H1 and the second contact hole H2 that is positioned at storage electrode 222 tops, and top electrode 294 stacks on active layers 272 by the second contact hole H2 that is arranged in sensing area 200B, and contacts with active layers 272.So, just can form OPTICAL SENSORS, in order to the light variation of sensitive context by hearth electrode 264, active layers 272 and top electrode 294.Wherein, because the top electrode 294 of OPTICAL SENSORS is a transparency conducting layer, therefore extraneous light can be directly by top electrode 294 irradiation active layers 272.On making, help significantly to increase the photosensitive area of OPTICAL SENSORS, and promote its light sensing usefulness.In addition, because the material of hearth electrode 264 is generally lighttight metal, therefore can effectively stop backlight direct irradiation active layers 272, the sensitization usefulness that has influence on OPTICAL SENSORS to avoid producing noise.

In addition, the storage capacitors that is constituted between storage electrode 222, gate insulation layer 230 and the storage electrode 242, can and storage electrode 242, first dielectric layer 250, second dielectric layer 280 and pixel electrode 292 between the mutual superposition of storage capacitors that constituted and promote the voltage retention of pixel electrode 292.

Fig. 2 H illustrates the another kind of active component array base board schematic diagram of the first embodiment of the present invention, please refer to Fig. 2 H, the part first type doped region 220a in the active component array base board contacts with the second type doped region 220b or is connected, and has a contact interface between the first type doped region 220a and the second type doped region 220b.The part first contact hole H1 exposes contact interface.In other words, in the same first contact hole H1, expose the first type doped region 220a and the second type doped region 220b simultaneously, make each pixel electrode 292 only need one first contact hole H1 by being positioned at storage electrode 222 tops and one second contact hole H2 and directly be electrically connected with storage electrode 222.All the other elements of the another kind of active component array base board of Fig. 2 H and technology are identical with the active component array base board 200 of Fig. 1, do not give unnecessary details at this.

The foregoing description is that the photomask technology that adopts seven road photomask technologies to make the active component array base board 200 with OPTICAL SENSORS is that example describes, therefore the present invention can be with the light sensing material sorting in original active component array base board 200 technologies, can't additionally increase photomask technology, reach the effect of saving cost and improving the technology yield.Yet in not departing from the scope of the present invention, the visual actual state of dopant profile of aforesaid photomask number of processes and active member is changed.

Second embodiment:

Fig. 3 illustrates a kind of active component array base board according to the second embodiment of the present invention.Please refer to Fig. 3, the active component array base board 300 of present embodiment and the active component array base board 200 of first embodiment are similar, only compared to first embodiment, in the active component array base board 300 of present embodiment, the pixel electrode 292 that is positioned at pixel region 200A for example is to be electrically connected with first patterned semiconductor layer 220 indirectly by first patterning conductor layer 240 and second patterning conductor layer 260.

Specifically, compared to first embodiment, first patterning conductor layer 240 of active component array base board 300 more comprises the bridged electrodes 249 that is positioned at pixel region 200A.Simultaneously, the contact conductor 262 of active component array base board 300 is inserted the first contact hole H1 and is contacted with source doping region 224s, drain doped region 224d and storage electrode 222 respectively, and the contact conductor 262 of present embodiment is more inserted the 3rd contact hole H3 that exposes bridged electrodes 249.So, as part the 3rd patterning conductor layer 290 of pixel electrode 292 is to pass the second contact hole H2 and the 3rd contact hole H3 and directly be electrically connected with the bridged electrodes 249 of first patterning conductor layer 240, and bridged electrodes 249 is electrically coupled to drain doped region 224d and storage electrode 222 respectively via contact conductor 262 again.

Therefore in the present embodiment, data voltage among the drain doped region 224d of active member, it is the pixel electrode 292 that is passed to via the bang path of the bridged electrodes 249 of the contact conductor 262 of second patterning conductor layer 260 and first patterning conductor layer 240 in order to show, and in the present embodiment, storage electrode 222, gate insulation layer 230, storage electrode 242, first dielectric layer 250, contact conductor 262, bridged electrodes 249, second dielectric layer 280 and pixel electrode 292 can constitute the storage capacitors of a sandwich construction jointly, and it is simple layer or multilayer storage capacitors that actual panel designs visual Demand Design.

For further specifying technology contents of the present invention, hereinafter more collocation diagram illustrates the manufacture method of the active component array base board 300 of second embodiment of the invention.

Please refer to Fig. 4 A～Fig. 4 G, it illustrates the technology of a kind of active component array base board of the second embodiment of the present invention in regular turn, and Fig. 4 A '～Fig. 4 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 4A～Fig. 4 G and pad zone.For the purpose of simplifying the description, present embodiment no longer similarly partly is illustrated the making flow process shown in described these and Fig. 2 A～2G and Fig. 2 A '～2G '.

Shown in Fig. 4 C and Fig. 4 C ', to compare with the active component array base board 200 of first embodiment, present embodiment more in the patterning step of first conductor layer, forms above-mentioned bridged electrodes 249 simultaneously.Then, shown in Fig. 4 D and Fig. 4 D ', compared to first embodiment, present embodiment more forms the 3rd contact hole H3 that exposes bridged electrodes 249 in bridged electrodes 249 tops in the Patternized technique of first dielectric layer 250.Afterwards, shown in Fig. 4 E and Fig. 4 E ', compared to first embodiment, present embodiment forms in the technology of second patterning conductor layer 260 and second patterned semiconductor layer 270 at the same time, more in the first contact hole H1, insert contact conductor 262 and contacting with storage electrode 222 with source doping region 224s, drain doped region 224d respectively, contact conductor 262 and pass the 3rd contact hole H3 that exposes bridged electrodes 249 and contact with bridged electrodes 249.In addition, in this step, and form contact conductor 262 simultaneously in order to be electrically connected bridged electrodes 249, storage electrode 222 and drain doped region 224d.

Afterwards, shown in Fig. 4 F and Fig. 4 F ', compared to first embodiment, present embodiment is in the Patternized technique of second dielectric layer 280, more in second dielectric layer 280, offer the second contact hole H2, to expose part bridged electrodes 249 corresponding to part the 3rd contact hole H3.Then, shown in Fig. 4 G and Fig. 4 G ', present embodiment is in the step that forms the 3rd patterning conductor layer 290, as part the 3rd patterning conductor layer 290 of pixel electrode 292 is by the 3rd contact hole H3 and the second contact hole H2 and directly be electrically connected with the bridged electrodes 249 of first patterning conductor layer 240, and part the 3rd patterning conductor layer 290 of pixel electrode 292 is via the contact conductor 262 of the bridged electrodes 249 of first patterning conductor layer 240 and second patterning conductor layer 260 and be electrically connected with drain doped region 224d and storage electrode 222 indirectly.

Fig. 4 H illustrates the another kind of active component array base board schematic diagram of the second embodiment of the present invention, please refer to Fig. 4 H, the part first type doped region 220a in the active component array base board contacts with the second type doped region 220b, and has a contact interface between the first type doped region 220a and the second type doped region 220b.The part first contact hole H1 exposes contact interface.In other words, expose the first type doped region 220a and the second type doped region 220b in the same first contact hole H1 simultaneously, making only needs directly be connected with the second type doped region 220b with the first type doped region 220a by being positioned at one first contact hole H1 with the contact conductor 262 of pixel electrode 292 electrical connections.All the other elements of the another kind of active component array base board of Fig. 4 H and technology are identical with the active component array base board 300 of Fig. 3, do not give unnecessary details at this.

Accept above-mentioned second embodiment, be to utilize seven road photomask technologies to make active component array base board 300 with OPTICAL SENSORS, therefore the active component array base board 300 of present embodiment can reach equally to shorten and make timeliness, reduces the effect of manufacturing cost.

The 3rd embodiment:

Fig. 5 illustrates a kind of active component array base board according to the third embodiment of the present invention.Please refer to Fig. 5, the active component array base board 400 of present embodiment is similar with the active component array base board 200,300 of previous embodiment, only compared to previous embodiment 200,300, in the active component array base board 400 of present embodiment, be positioned at pixel region 200A and be electrically connected with first patterned semiconductor layer 220 by described these second contact hole H2 of part and described second patterning conductor layer 260 as the 3rd patterning conductor layer 290 of pixel electrode 292.And, second patterned semiconductor layer 270 of present embodiment more comprises a plurality of plan semiconductor layers 274 that are positioned on the contact conductor 262, the size of wherein partly intending semiconductor layer 274 for example is the size that equals to contact conductor 262 in fact, and the size of partly intending semiconductor layer 274 for example is in fact less than the size that contacts conductor 262, in other words, part is intended the covered contact conductor 262 of semiconductor layer 274, do not cover contact conductor 262 and partly intend semiconductor layer 274, as shown in Figure 5, with contact conductor 262 that the 3rd patterned conductor is connected in, the size of plan semiconductor layer 274 that is positioned at its top is less than the size of described place's contact conductor 262.

Specifically, compared to previous embodiment, contact conductor 262 tops of present embodiment have the semiconductor layer 274 of plan.Simultaneously, the size of the plan semiconductor layer 274 by dwindling part contact conductor 262 tops can allow the second contact hole H2 in second dielectric layer 280 directly avoid intending semiconductor layer 274 and exposes the contact conductor 262 of part.So, as shown in Figure 5, as part the 3rd patterning conductor layer 290 of pixel electrode 292 can pass the second contact hole H2 that exposes contact conductor 262 and directly with contact conductor 262 and contact, thereby pixel electrode 292 is connected with first patterned semiconductor layer 220 by the second contact hole H2 and contact conductor 262, and first patterned semiconductor layer 220 that wherein is electrically connected with pixel electrode 292 for example is the drain doped region 224d of active member and the storage electrode 222 of storage capacitors.

Therefore in the present embodiment, data voltage among the drain doped region 224d of active member, be to be passed on the pixel electrode 292 that shows usefulness by the contact conductor 262 of second patterning conductor layer 260 and the bang path of the second contact hole H2, in the present embodiment, storage electrode 222, gate insulation layer 230, storage electrode 242, first dielectric layer 250, second dielectric layer 280 and pixel electrode 292 can constitute the storage capacitors of a sandwich construction jointly, and it is simple layer or multilayer storage capacitors that actual panel designs visual Demand Design.

For further specifying technology contents of the present invention, hereinafter more collocation diagram illustrates the manufacture method of the active component array base board 400 of third embodiment of the invention.

Please refer to Fig. 6 A～Fig. 6 G, it illustrates the technology of a kind of active component array base board of the third embodiment of the present invention in regular turn, and Fig. 6 A '～Fig. 6 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 6A～Fig. 6 G and pad zone.For the purpose of simplifying the description, present embodiment no longer similarly partly is illustrated the making flow process shown in described these and Fig. 2 A～Fig. 2 G and Fig. 2 A '～Fig. 2 G '.

Shown in Fig. 6 E and Fig. 6 E ', compared to first embodiment, present embodiment forms in the technology of second patterning conductor layer 260 and second patterned semiconductor layer 270 at the same time, more in the first contact hole H1, insert contact conductor 262 and contact with storage electrode 222 with source doping region 224s, drain doped region 224d respectively, form plan semiconductor layer 274 respectively and be positioned at second patterned semiconductor layer 270 that contacts 262 layers of top of conductor.Simultaneously, in this step, utilize the size of the size of the feasible contact conductor 262 that is connected with drain doped region 224d greater than the plan semiconductor layer 274 that is positioned at its top with photomask technology, for example be half mode photomask technology or a grey mode photomask technology with photomask technology wherein, detailed processing step will be in hereinafter arranging in pairs or groups after Fig. 7 A～Fig. 7 D is specified in.

Afterwards, shown in Fig. 6 F and Fig. 6 F ', compared to first embodiment, the part second contact hole H2 in second dielectric layer 280 of present embodiment is the top that is formed at the contact conductor 262 of inserting the first contact hole H1 accordingly, and owing to subregion of this contact conductor 262 is not covered by the plan semiconductor layer 274 of top, so this second contact hole H2 exposes the contact conductor 262 that connects drain doped region 224d and storage electrode 222.Then, shown in Fig. 6 G and Fig. 6 G ', present embodiment is in the step that forms the 3rd patterning conductor layer 290, as part the 3rd patterning conductor layer 290 of pixel electrode 292 is to pass the second contact hole H2 and directly is connected with contact conductor 262, and pixel electrode 292 passes through this and contacts conductor 262 and be electrically connected with drain doped region 224d and with storage electrode 222 respectively.

The method of above-mentioned formation contact conductor 262 and plan semiconductor layer 274 for example can use half mode photomask technology to make.Fig. 7 A～Fig. 7 D is the making schematic flow sheet of a kind of formation second patterning conductor layer and second patterned semiconductor layer.Shown in Fig. 7 A, on first dielectric layer 250, form second conductor layer 260 ', second semiconductor layer 270 ' and patterning photoresist layer 410 in regular turn, wherein patterning photoresist layer 410 for example is covered on the subregion of second semiconductor layer, and patterning photoresist layer 410 has the first block 410A and one second block 410B, and the thickness of the first block 410A is greater than the thickness of the second block 410B.In detail, the patterning photoresist layer 410 that is positioned at contact conductor 262 tops that are connected with source doping region 224s is for having the first block 410A of big thickness, and the second block 410B that the patterning photoresist layer 410 that is positioned at contact conductor 262 tops that are connected with drain doped region 224d and storage electrode 222 can be divided into the first block 410A and be positioned at the first block 410A both sides, and the thickness of the first block 410A is greater than the thickness of the second block 410B.Afterwards, shown in Fig. 7 B, be that mask carries out an etching technics to second conductor layer 260 ' and second semiconductor layer 270 ', to form hearth electrode 264, active layers 272 and contact conductor 262 and to intend semiconductor layer 274 with patterning photoresist layer 410.

Then, shown in Fig. 7 C, reduce the thickness of patterning photoresist layer 410, removed fully up to the second block 410B, and the method for minimizing patterning photoresist layer 410 thickness for example is to adopt the mode of ashing.And, after the second block 410B is removed fully, be that mask carries out an etching technics to the part plan semiconductor layer 274 that is exposed with the remaining first block 410A '.Afterwards, shown in Fig. 7 D, remove process layer to remove the remaining first block 410A ' carrying out a photoresist, promptly form the structure shown in Fig. 6 E: part contacts the plan semi-conductive size of the size of conductor 262 greater than its top.

Fig. 6 H illustrates the another kind of active component array base board schematic diagram of the third embodiment of the present invention, please refer to Fig. 6 H, the part first type doped region 220a in the active component array base board contacts with the second type doped region 220b, and has a contact interface between the first type doped region 220a and the second type doped region 220b.The part first contact hole H1 exposes contact interface.In other words, expose the first type doped region 220a and the second type doped region 220b in the same first contact hole H1 simultaneously, making only needs directly be connected with the second type doped region 220b with the first type doped region 220a by being positioned at one first contact hole H1 with the contact conductor 262 of pixel electrode 292 electrical connections.

Accept above-mentioned the 3rd embodiment, can utilize seven road photomask technologies to make active component array base board 400 equally, so the active component array base board 400 of present embodiment can shorten the making timeliness, the reduction manufacturing cost with OPTICAL SENSORS.

The 4th embodiment:

Fig. 8 illustrates a kind of active component array base board according to the fourth embodiment of the present invention.Please refer to Fig. 8, the active component array base board 400 of the active component array base board of present embodiment and the 3rd embodiment is similar, being positioned at pixel region 200A is to be electrically connected with first patterned semiconductor layer 220 by the part second contact hole H2 and second patterning conductor layer 260 as the 3rd patterning conductor layer 290 of pixel electrode 292, only compared to the 3rd embodiment, in the active component array base board 500 of present embodiment, pixel electrode 292 is except the second contact hole H2 that passes through second dielectric layer 280, also pass through the plan semiconductor layer 274 at described place and couple the contact conductor 262 of second patterning conductor layer 260 downwards, and be electrically connected with drain doped region 224d and storage electrode 222.And the size of the plan semiconductor layer 274 of present embodiment for example is the size that equals to contact conductor 262 in fact, and as shown in Figure 8, in other words, the edge of intending semiconductor layer 274 trims in fact in the edge of contact conductor 262.

Specifically, compared to the 3rd embodiment, the plan semiconductor layer 274 of present embodiment is directly to stack on contact conductor 262, and by suitable Patternized technique, describe in detail in the back, can allow the second contact hole H2 in second dielectric layer 280 directly pass through the contact conductor 262 of intending semiconductor layer 274 and exposing part.So, as shown in Figure 8, as part the 3rd patterning conductor layer 290 of pixel electrode 292 can via the second contact hole H2 pass second dielectric layer 280 and intend semiconductor layer 274 and directly with contact conductor 262 and contact, thereby pixel electrode 292 is connected with first patterned semiconductor layer 220 by the second contact hole H2 and contact conductor 262, and first patterned semiconductor layer 220 that wherein is electrically connected with pixel electrode 292 for example is the drain doped region 224d of active member and the storage electrode 222 of storage capacitors.

Therefore in the present embodiment, data voltage among the drain doped region 224d of active member, be the contact conductor 262 by second patterning conductor layer 260 and pass through second patterned semiconductor layer 270, the bang path of the second contact hole H2 and being passed on the pixel electrode 292 that shows usefulness, in the present embodiment, storage electrode 222, gate insulation layer 230, storage electrode 242, first dielectric layer 250, second dielectric layer 280 and pixel electrode 292 can constitute the storage capacitors of a sandwich construction jointly, and it is simple layer or multilayer storage capacitors that actual panel designs visual Demand Design.

For further specifying technology contents of the present invention, hereinafter more collocation diagram illustrates the manufacture method of the active component array base board 500 of fourth embodiment of the invention.

Please refer to Fig. 9 A～Fig. 9 G, it illustrates the technology of a kind of active component array base board of the third embodiment of the present invention in regular turn, and Fig. 9 A '～Fig. 9 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 9A～Fig. 9 G and pad zone.For the purpose of simplifying the description, present embodiment no longer similarly partly is illustrated the making flow process shown in described these and Fig. 6 A～Fig. 6 G and Fig. 6 A '～Fig. 6 G '.

Shown in Fig. 9 E and Fig. 9 E ', compared to the 3rd embodiment, present embodiment forms in the technology of second patterning conductor layer 260 and second patterned semiconductor layer 270 at the same time, be to utilize feasible and the size that contacts conductor 262 to equal to intend the size of semiconductor layer 274 in fact with photomask technology, and contact conductor 262 is inserted source doping region 224s, drain doped region 224d and storage electrode 222 respectively, and drain doped region 224d contacts conductor 262 with storage electrode 222 via one and is electrically connected.

Specifically, shown in Fig. 9 F and Fig. 9 F ', compared to the 3rd embodiment, present embodiment patterning second dielectric layer 280 with the step that forms the second contact hole H2 in, utilizing makes the plan semiconductor layer 274 below the part second contact hole H2 remove in the lump with photomask technology, to expose the contact conductor 262 that is connected with drain doped region 224d, and reservation is arranged in the active layers 272 that sensing area 200B is exposed by the second contact hole H2 simultaneously, for example be half mode photomask technology or a grey mode photomask technology with photomask technology wherein, detailed processing step will be in hereinafter arranging in pairs or groups after Figure 10 A～Figure 10 D is specified in.

Then, shown in Fig. 9 G and Fig. 9 G ', present embodiment is in the step that forms the 3rd patterning conductor layer 290, as part the 3rd patterning conductor layer 290 of pixel electrode 292 is to pass the second contact hole H2 of second dielectric layer 280 and intend semiconductor layer 274 and directly is connected with contact conductor 262, and pixel electrode 292 passes through this and contacts conductor 262 and be electrically connected with drain doped region 224d and with storage electrode 222 respectively.

On be set forth in second dielectric layer 280 method that forms the second contact hole H2 and for example can use half mode photomask technology to make.Figure 10 A～Figure 10 D is a kind of making schematic flow sheet that forms second contact hole of different depth.Shown in Figure 10 A, prior to forming patterning photoresist layer 510 on second dielectric layer 280, wherein patterning photoresist layer 510 is covered on the subregion of second dielectric layer 280, and patterning photoresist layer 510 has one first block 510A and one second block 510B, and the thickness of the first block 510A is greater than the thickness of the second block 510B, and the second block 510B is corresponding to active layers 272 tops.Afterwards, shown in Figure 10 B, be mask with patterning photoresist layer 510 again, patterning second dielectric layer 280 is carried out one remove step, expose the second contact hole H2 that intends semiconductor layer 274 and the 3rd contact hole H3 respectively to form.What deserves to be mentioned is that owing to have second a less block 510B of thickness above active layers 272, therefore after removing step and finishing, active layers 272 tops can keep certain thickness second dielectric layer 280.

Then, shown in Figure 10 C, with patterning photoresist layer 510 is that mask carries out an etching technics to the plan semiconductor layer 274 that is come out by second dielectric layer 280, so that the second contact hole H2 at described place passes through the contact conductor 262 of intending semiconductor layer 274 and exposing the below.Then, after removing remaining patterning photoresist layer 510, shown in Figure 10 D, reduce the thickness of second dielectric layer 280, second dielectric layer 280 up to active layers 272 tops is removed fully and exposes active layers 272, the method that wherein reduces second dielectric layer, 280 thickness for example is to adopt the mode of ashing, promptly forms the structure shown in Fig. 9 F '.

Certainly, in another embodiment, when second dielectric layer, 280 employed materials belong to photosensitive organic resin material, second dielectric layer 280 also can be directly controlled the degree of depth of the second contact hole H2 by shining exposure energy on the second contact hole H2 in the modulation lithography process, and the present invention is not limited thereto.

In addition, Fig. 9 H illustrates the another kind of active component array base board schematic diagram of the fourth embodiment of the present invention, please refer to Fig. 9 H, the part first type doped region 220a in the active component array base board contacts with the second type doped region 220b, and has a contact interface between the first type doped region 220a and the second type doped region 220b.The part first contact hole H1 exposes contact interface.In other words, expose the first type doped region 220a and the second type doped region 220b in the same first contact hole H1 simultaneously, making only needs directly be connected with the second type doped region 220b with the first type doped region 220a by being positioned at one first contact hole H1 with the contact conductor 262 of pixel electrode 292 electrical connections.

The 5th embodiment:

Figure 11 illustrates a kind of active component array base board according to the fifth embodiment of the present invention.Please refer to Figure 11, the active component array base board 600 of present embodiment and the active component array base board 400 of the 3rd embodiment are similar, being positioned at pixel region 200A is to be electrically connected with first patterned semiconductor layer 220 by the part second contact hole H2 and second patterning conductor layer 260 as the 3rd patterning conductor layer 290 of pixel electrode 292, only compared to the 3rd embodiment, in the active component array base board 600 of present embodiment, the size that the part of present embodiment is intended semiconductor layer 274 for example is in fact all less than the size that partly contacts conductor 262, as shown in figure 11.

Specifically, compared to the 3rd embodiment, second patterning conductor layer 260 of present embodiment and the size difference of second patterned semiconductor layer 270, and by making with photomask technology.So, not only can reduce the photomask number, and because the size of hearth electrode 264 that is arranged in sensing area 200B is greater than the size of active layers 272, therefore hearth electrode 264 can more effectively cover the light from backlight, avoid active layers 272 to produce photoelectric current, reduce the phenomenon that OPTICAL SENSORS produces noise because of unexpected light disturbs.

Therefore in the present embodiment, hearth electrode 264 sizes in the OPTICAL SENSORS are greater than active layers 272 sizes, in order to the sensing usefulness of further lifting OPTICAL SENSORS.Data voltage among the drain doped region 224d of active member, be that contact conductor 262 by second patterning conductor layer 260 and the bang path that passes through second patterned semiconductor layer 270, the second contact hole H2 are passed on the pixel electrode 292 that shows usefulness, in the present embodiment, storage electrode 222, gate insulation layer 230, storage electrode 242, first dielectric layer 250, second dielectric layer 280 and pixel electrode 292 can constitute the storage capacitors of a sandwich construction jointly, and it is simple layer or multilayer storage capacitors that actual panel designs visual Demand Design.

For further specifying technology contents of the present invention, hereinafter more collocation diagram illustrates the manufacture method of the active component array base board 600 of fifth embodiment of the invention.

Please refer to Figure 12 A～12G, it illustrates the technology of a kind of active component array base board of the fifth embodiment of the present invention in regular turn, and Figure 12 A '～Figure 12 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 12A～Figure 12 G and pad zone.For the purpose of simplifying the description, present embodiment no longer similarly partly is illustrated the making flow process shown in described these and Fig. 6 A～Fig. 6 G and Fig. 6 A '～Fig. 6 G '.

Shown in Figure 12 E and Figure 12 E ', compared to the 3rd embodiment, present embodiment forms in the technology of second patterning conductor layer 260 and second patterned semiconductor layer 270 at the same time, be to utilize with photomask technology to make the size of partly intending semiconductor layer 274 contact the size of conductor 262 in fact less than part, and contact conductor 262 and the 3rd embodiment are similar, be to insert source doping region 224s, drain doped region 224d and storage electrode 222 respectively, and drain doped region 224d contact conductor 262 with storage electrode 222 via one and is electrically connected.In this step, utilize and to make the size of the plan semiconductor layer 274 that is arranged in pixel region 200A with photomask technology less than the size that contacts 262 layers of conductors, and make the size of the active layers 272 be arranged in sensing area 200B less than the size of hearth electrode 264, wherein tropism's etching technics such as for example be to use with photomask technology, detailed processing step will be in hereinafter arranging in pairs or groups after Figure 13 A～Figure 13 D is specified in.

Afterwards, shown in Figure 12 F and Figure 12 F ', the covering scope of the second contact hole H2 is less than active layers 272.Then, shown in Figure 12 G and Figure 12 G ', present embodiment is in the step that forms the 3rd patterning conductor layer 290, as part the 3rd patterning conductor layer 290 of pixel electrode 292 is to pass the second contact hole H2 and directly is connected with contact conductor 262, and pixel electrode 292 passes through this and contacts conductor 262 and be electrically connected with drain doped region 224d and with storage electrode 222 respectively.And in sensing area 200B, the size of hearth electrode 264 is greater than the size of active layers 272.

Form above-mentioned size less than the plan semiconductor layer 274 of contact conductor 262 sizes and form above-mentioned size and tropism's etching such as for example can use to make less than the method for the active layers 272 of hearth electrode 264 sizes.Figure 13 A～Figure 13 D is the making schematic flow sheet of a kind of formation second patterning conductor layer and second patterned semiconductor layer.As shown in FIG. 13A, form one second conductor layer 260 ', one second semiconductor layer 270 ' and a patterning photoresist layer 610 on first dielectric layer 250 in regular turn, wherein patterning photoresist layer 610 for example is covered on the zone of predetermined formation hearth electrode 264 and contact conductor 262.Afterwards, shown in Figure 13 B, with patterning photoresist layer 610 is that mask comes patterning second conductor layer 260 ' and second semiconductor layer 270 ', wherein the method for patterning second conductor layer 260 ' and second semiconductor layer 270 ' for example is to carry out an etching technics, to form hearth electrode 264, active layers 272 and contact conductor 262 and to intend semiconductor layer 274.

Then, shown in Figure 13 C, active layers 272 and plan semiconductor layer 274 are carried out the side direction etching, so that intend the size of the size of semiconductor layer 274 less than contact conductor 262, and make the size of the size of active layers 272 less than hearth electrode 264, in other words, the size that makes second graphical semiconductor layer 270 is less than second graphical conductor layer 260, and the side direction etching technics can be enumerated wet etching technology, utilize an etching liquid that has a higher selection ratio for second semiconductor material to carry out the side direction etching, certainly the side direction etching technics is not limited in wet etching technology, the situation that also can utilize the reacting gas of higher concentration in the technology of dry etching and not apply bias voltage is issued to the effect of side direction etching second semiconductor layer 270 ', and the present invention does not limit the kind of side direction etching.

Afterwards, shown in Figure 13 D, remove process layer to remove remaining patterning photoresist layer 610 carrying out a photoresist, promptly form the structure shown in Figure 12 E: the size of contact conductor 262 is greater than the semi-conductive size of plan of its top, and the size of hearth electrode 264 is greater than the size of active layers 272.

In addition, Figure 12 H illustrates the another kind of active component array base board schematic diagram of the fifth embodiment of the present invention, please refer to Figure 12 H, the part first type doped region 220a in the active component array base board contacts with the second type doped region 220b, and has a contact interface between the first type doped region 220a and the second type doped region 220b.The part first contact hole H1 exposes contact interface.In other words, expose the first type doped region 220a and the second type doped region 220b in the same first contact hole H1 simultaneously, making only needs directly be connected with the second type doped region 220b with the first type doped region 220a by being positioned at one first contact hole H1 with the contact conductor 262 of pixel electrode 292 electrical connections.

Accept above-mentioned the 5th embodiment, can utilize seven road photomask technologies to make active component array base board 600 equally, so the active component array base board 600 of present embodiment can shorten the making timeliness, the reduction manufacturing cost with OPTICAL SENSORS.Simultaneously, because the size of hearth electrode 264 that is arranged in sensing area 200B is greater than the size of active layers 272, therefore hearth electrode 264 can more effectively cover the light from backlight, avoids active layers 272 to produce photoelectric current because of unexpected light disturbs, and reduces the phenomenon that OPTICAL SENSORS produces noise.

The 6th embodiment:

Figure 14 illustrates a kind of active component array base board according to the sixth embodiment of the present invention, the active component array base board 700 of present embodiment and the active component array base board 700 of the 3rd embodiment are similar, and the material of similar member and technology are considered and can be repeated no more with reference to previous embodiment.In the present embodiment, active component array base board 700 can be divided into as the pixel region 700A among Figure 14, sensing area 700B and pad zone 700C, and active component array base board 700 comprises substrate 710, first patterned semiconductor layer 720, gate insulation layer 730, first patterning conductor layer 740, second patterned semiconductor layer 750, first dielectric layer 760, second patterning conductor layer 770, second dielectric layer 780 and the 3rd patterning conductor layer 790.And compared to previous embodiment, second patterned semiconductor layer 750 is to be configured on first patterning conductor layer 740, and hearth electrode 742 in the OPTICAL SENSORS and active layers 752 are made with first patterning conductor layer 740 and second patterned semiconductor layer 750 respectively, and first patterning conductor layer 740 and second patterned semiconductor layer 750 form simultaneously.Moreover, in the active component array base board 700 of present embodiment, intend semiconductor layer 754 and more for example be formed on the grid 746.

In detail, please refer to Figure 14, first patterning conductor layer 740 of active component array base board 700 comprises a plurality of grids 746 and a hearth electrode 742, second patterned semiconductor layer 750 is disposed on first patterning conductor layer 740, and wherein second patterned semiconductor layer 750 comprises that one is positioned at the active layers 752 on the hearth electrode 742.First dielectric layer 760 is disposed on the gate insulation layer 730, and to cover first patterning conductor layer 740, wherein first dielectric layer 760 has a plurality of first contact hole H1 and one the 3rd contact hole H3 that first patterned semiconductor layer 720 is exposed with gate insulation layer 730.Second patterning conductor layer 770 is disposed on first dielectric layer 760, and wherein second patterning conductor layer 770 comprises a plurality of contact conductors 772 that are positioned at the first contact hole H1.Second dielectric layer 780 is disposed on first dielectric layer 760, and wherein second dielectric layer 780 has a plurality of second contact hole H2, and the part second contact hole H2 is positioned at active layers 752 tops.The 3rd patterning conductor layer 790 is disposed on second dielectric layer 780, and in sensing area 700B, part the 3rd patterning conductor layer 790 is electrically connected with active layers 752 by part second contact hole H2 and the 3rd contact hole H3.

As shown in figure 14, first patterned semiconductor layer 720 is disposed on the substrate 710, and influences the running of OPTICAL SENSORS for fear of unexpected light, and first light shield layer 726 can optionally be set on the substrate among the sensing area 700B 710.Gate insulation layer 730 is disposed on the substrate 710, and gate insulation layer 730 is disposed on the substrate 710 covering first patterned semiconductor layer 720, and gate insulation layer 730 is made of dielectric material.

What deserves to be mentioned is, in the present embodiment, please refer to Figure 14, first patterning conductor layer 740 is disposed on the gate insulation layer 730, and in the present embodiment, first patterning conductor layer 740 can be divided into a plurality of grids 746 that constitute active member, constitute the storage electrode 746 of storage capacitors, first soldering pad layer 748 that is positioned at the hearth electrode 742 of sensing area 700B and is positioned at pad zone 700C, wherein grid 746, storage electrode 722, the hearth electrode 742 and first soldering pad layer 748 are identical conductive material, grid 746 is positioned on the gate insulation layer 730 of channel region 724c top, and storage electrode 744 is positioned on the gate insulation layer 730 of storage electrode 722 tops.

As shown in figure 14, second patterned semiconductor layer 750 is disposed on first patterning conductor layer 740, and wherein second patterned semiconductor layer 750 comprises that one is positioned at the active layers 752 on the hearth electrode 742.What deserves to be mentioned is that in the present embodiment, second patterned semiconductor layer 750 more comprises a plurality of plan semiconductor layers 754 that are positioned on the grid 746, wherein, the size of intending semiconductor layer 754 can be less than or equal to the size that contacts conductor 772, but is not limited thereto.As shown in figure 14, first dielectric layer 760 is disposed on the gate insulation layer 730, to cover first patterning conductor layer 740, wherein first dielectric layer 760 has a plurality of first contact hole H1 and one the 3rd contact hole H3 that first patterned semiconductor layer 720 is exposed with gate insulation layer 730, wherein the 3rd contact hole H3 exposes active layers 752, and in the present embodiment, first dielectric layer 760 more for example forms a plurality of the 3rd contact hole H3 that first patterning conductor layer 740 is exposed, and exposes first soldering pad layer 748 as the 3rd contact hole H3 among the pad zone 700C.

Refer again to Figure 14, second patterning conductor layer 770 is disposed on first dielectric layer 760, wherein second patterning conductor layer 770 comprises a plurality of contact conductors 772, and contact conductor 772 is arranged in the first contact hole H1 to small part, be couple to pairing part first patterned semiconductor layer 720 to pass first dielectric layer 760 with gate insulation layer 730, in the present embodiment, contact conductor 772 for example is directly to be connected with source doping region 724s, source doping region 724s and storage electrode 722 respectively.And in the present embodiment, contact conductor 772 more passes the 3rd contact hole H3 and is connected with first soldering pad layer 748 of first patterned semiconductor layer 720.

Please continue with reference to Figure 14, second dielectric layer 780 is disposed on first dielectric layer 760, and wherein second dielectric layer 780 has a plurality of second contact hole H2, and the part second contact hole H2 is positioned at active layers 752 tops.The 3rd patterning conductor layer 790 is disposed on second dielectric layer 780, wherein part the 3rd patterning conductor layer 790 is electrically connected with active layers 752 by part second contact hole H2 and the 3rd contact hole H3, therefore comprise the hearth electrode 742 that is positioned on the gate insulation layer 730, be positioned at the active layers 752 on the hearth electrode 742 in the formed OPTICAL SENSORS of the sensing area 700B of present embodiment, and pass second dielectric layer 780, second dielectric layer 780 and the top electrode 294 that contacts with active layers 752.

In addition, the part second contact hole H2 is corresponding to the first contact hole H1, so that directly be electrically connected by the first contact hole H1 and the second contact hole H2 with active member and storage electrode 722 as part the 3rd patterning conductor layer 790 of pixel electrode 792, in other words, pixel electrode 792 pass second dielectric layer 780 and with fill in the first contact hole H1 in contact conductor 772 contact, and by this contact conductor 772 be conductively coupled to first patterned semiconductor layer 720 downwards, in the present embodiment, pixel electrode 792 for example is drain doped region 724d and the storage electrode 722 that is electrically connected to first patterned semiconductor layer 720.As shown in figure 14, storage electrode 722 is electrically connected to drain doped region 224d via contact conductor 772, in other words, the storage electrode 722 that is positioned at gate insulation layer 730 belows and pixel electrode 792 be equipotential in fact, therefore in the present embodiment, storage electrode 722, gate insulation layer 730, storage electrode 744, plan semiconductor layer 754, first dielectric layer 760, second dielectric layer 780 and pixel electrode 792 can constitute the storage capacitors of a sandwich construction jointly, and it is simple layer or multilayer storage capacitors that actual panel designs visual Demand Design.

In addition, in the pad zone 700C of present embodiment, the part second contact hole H2 corresponding to the 3rd contact hole H3 to expose first soldering pad layer 748 of first patterning conductor layer 740, part the 3rd patterning conductor layer 790 as second soldering pad layer 798 is electrically connected with first soldering pad layer 748 of first patterning conductor layer 740 by the 3rd contact hole H3 and the second contact hole H2, in more detail, as part the 3rd patterning conductor layer 790 of second soldering pad layer 798 be pass by the second contact hole H2 with fill in the 3rd contact hole H3 in contact conductor 772 and be electrically connected with first soldering pad layer 748 of first patterning conductor layer 740.In the present embodiment, weld pad mainly is made of jointly first soldering pad layer 748 of first patterning conductor layer 740, the contact conductor 772 of second patterned

conductor layer

770 and 798 of second soldering pad layers of the 3rd patterning conductor layer 790.

For further specifying technology contents of the present invention, hereinafter more collocation diagram illustrates the manufacture method of the active component array base board 700 of sixth embodiment of the invention.

Please refer to Figure 15 A～Figure 15 G, it illustrates the technology of a kind of active component array base board of the sixth embodiment of the present invention in regular turn, and Figure 15 A '～Figure 15 G ' is respectively the process section of the CC ' hatching of the BB ' hatching of AA ' hatching, sensing area of the pixel region of corresponding diagram 15A～Figure 15 G and pad zone.For the purpose of simplifying the description, present embodiment no longer similarly partly is illustrated the making flow process shown in described these and Fig. 6 A～Fig. 6 G and Fig. 6 A '～Fig. 6 G '.Wherein the technology of Figure 15 A～15B and 15A '～Figure 15 B ' and Fig. 6 A～Fig. 6 B and Fig. 6 A '～Fig. 6 B ' are similar, no longer narrate in this.

Shown in Figure 15 C and Figure 15 C ', compared to the 3rd embodiment, present embodiment is after gate insulation layer 730 forms, and the method that forms first patterning conductor layer 740 simultaneously and be positioned at second patterned semiconductor layer 750 on first patterning conductor layer 740 for example is prior to forming one first conductor layer and one second semiconductor layer on the gate insulation layer 730 in regular turn.Follow again while patterning first conductor layer and second semiconductor layer, on gate insulation layer 730, to form the hearth electrode 742 and active layers 752 among the sensing area 700B, and in first patterned semiconductor layer, 720 tops of pixel region 700A form respectively grid 746 with and on plan semiconductor layer 754, with storage electrode 744 with and on plan semiconductor layer 754, and on the gate insulation layer 730 of pad zone 700C, form first soldering pad layer 748 and intend semiconductor layer 754.Certainly, the method that forms first patterning conductor layer 740 and second patterned semiconductor layer 750 simultaneously can also be utilized with half mode photomask technology and make, and its manufacture method can be carried out with reference to the step of earlier figures 7A～Fig. 7 D, does not give unnecessary details at this.

Afterwards, shown in Figure 15 D and Figure 15 D ', compared to the 3rd embodiment, present embodiment forms in the first contact hole H1 in first dielectric layer 760, more in first dielectric layer 760, form a plurality of the 3rd contact hole H3 that first patterning conductor layer 740 is exposed, to expose first soldering pad layer 748 in first patterning conductor layer 740.Wherein, the method that forms the first contact hole H1 and the 3rd contact hole H3 in first dielectric layer 760 simultaneously can be carried out with reference to the step of earlier figures 10A～10D, does not give unnecessary details at this.

Then, shown in Figure 15 E and Figure 15 E ', on first dielectric layer 760, form second patterning conductor layer 770, wherein second patterning conductor layer 770 comprises a plurality of contact conductors 772 that are positioned at the first contact hole H1 and directly contacts with source doping region 724s, drain doped region 724d and by the storage electrode 724 of first patterned semiconductor layer respectively, in the present embodiment, second patterning conductor layer 770 more comprises the contact conductor 772 of inserting the 3rd contact hole H3 and being connected with first soldering pad layer 748 of first patterning conductor layer 740.

Afterwards, shown in Figure 15 F and Figure 15 F ', on first dielectric layer 760, form second dielectric layer 780 to cover contact conductor 772.Then, in second dielectric layer 780, form a plurality of second contact hole H2, wherein the part second contact hole H2 is positioned at active layers 752 tops, and in first dielectric layer 760, for example utilize an etching technics to remove first dielectric layer 760 that is exposed by the second contact hole H2, expose active layers 752 in first dielectric layer 760, to form the 3rd contact hole H3.And, the part second contact hole H2 is opened on the first contact hole H1 accordingly, and the part second contact hole H2 is opened in accordingly and is positioned at the 3rd contact hole H3 top, fills in the contact conductor 772 among the first contact hole H1 and fills in contact conductor 772 among the 3rd contact hole H3 and expose respectively.

Then, shown in Figure 15 G and Figure 15 G ', form the 3rd patterning conductor layer 790 on second dielectric layer 780, wherein in sensing area 700B, part the 3rd patterning conductor layer 790 is electrically connected with active layers 752 by part second contact hole H2 and the 3rd contact hole H3 as top electrode 794.At this moment, part the 3rd patterning conductor layer 790 is as pixel electrode 792 and for example by the first contact hole H1 and fill in the contact conductor 772 among the second contact hole H2 and be electrically connected with drain doped region 724d and storage electrode 742 in first patterned semiconductor layer 720.And part the 3rd patterning conductor layer 790 for example is to be electrically connected with first soldering pad layer 748 of first patterning conductor layer 740 by the second contact hole H2 and the contact conductor 772 that fills among the 3rd contact hole H3 as second soldering pad layer 798.

In addition, Figure 15 H illustrates the another kind of active component array base board schematic diagram of the sixth embodiment of the present invention, please refer to Figure 15 H, the part first type doped region 720a in the active component array base board contacts with the second type doped region 720b, and has a contact interface between the first type doped region 720a and the second type doped region 720b.The part first contact hole H1 exposes described contact interface.In other words, expose the first type doped region 720a and the second type doped region 720b in the same first contact hole H1 simultaneously, making only needs directly also be connected with the second type doped region 720b with the first type doped region 720a simultaneously by being positioned at one first contact hole H1 with the contact conductor 772 of pixel electrode 792 electrical connections.

Accept above-mentioned the 6th embodiment, can utilize seven road photomask technologies to make active component array base board 700 equally, so the active component array base board 700 of present embodiment can shorten the making timeliness, the reduction manufacturing cost with OPTICAL SENSORS.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any technical staff with the technical field of the invention; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking the claim scope.

Claims

1. the manufacture method of an active component array base board is characterized in that, described method comprises:

On a substrate, form a buffer dielectric layer, one first patterned semiconductor layer, a gate insulation layer, one first patterning conductor layer and one first dielectric layer, wherein said gate insulation layer covers described first patterned semiconductor layer, and described first patterning conductor layer is disposed on the described gate insulation layer, and described first dielectric layer is disposed on the described gate insulation layer to cover described first patterning conductor layer;

In described first dielectric layer and described gate insulation layer, form a plurality of first contact holes that described first patterned semiconductor layer is exposed;

Be positioned at second patterned semiconductor layer on described second patterning conductor layer in forming one second patterning conductor layer and on described first dielectric layer simultaneously, wherein said second patterning conductor layer comprises a plurality of contact conductors and a hearth electrode, and described second patterned semiconductor layer comprises that one is positioned at the active layers on the described hearth electrode;

On described first dielectric layer, form one second dielectric layer;

Form a plurality of second contact holes in described second dielectric layer, wherein described these second contact holes of part expose described active layers; And

Form one the 3rd patterning conductor layer on described second dielectric layer, wherein described the 3rd patterning conductor layer of part is electrically connected with described active layers by described these second contact holes of part.

2. the manufacture method of active component array base board as claimed in claim 1 is characterized in that, the formation method of described first patterned semiconductor layer comprises:

On described substrate, form a plurality of island-shaped pattern; And

In described these island-shaped pattern, form a plurality of first type doped regions and a plurality of second type doped region, wherein have a contact interface between described these the first type doped regions of part and described these second type doped regions, and described these first contact holes of part expose described contact interface.

3. the manufacture method of active component array base board as claimed in claim 1 is characterized in that, the formation method of described second patterning conductor layer and described second patterned semiconductor layer comprises:

On described first dielectric layer, form one second conductor layer and one second semiconductor layer in regular turn; And

Described second conductor layer of patterning and described second semiconductor layer, on described first dielectric layer, to form described hearth electrode and described active layers, and in form described these contact conductors to first contact hole of small part, wherein described the 3rd patterning conductor layer of part directly is electrically connected with described first patterned semiconductor layer by described these first contact holes and described these second contact holes.

4. the manufacture method of active component array base board as claimed in claim 1 is characterized in that, described method more comprises:

When forming described these first contact holes, form a plurality of the 3rd contact holes that described first patterning conductor layer is exposed in described first dielectric layer, wherein described these second contact holes of part are positioned at described these first contact holes and described these the 3rd contact hole tops.

5. the manufacture method of active component array base board as claimed in claim 4 is characterized in that, the formation method of described second patterning conductor layer and described second patterned semiconductor layer comprises:

Described second conductor layer of patterning and described second semiconductor layer, on described first dielectric layer, to form described hearth electrode and described active layers, and described these of formation contact conductors in the 3rd contact hole of described these first contact holes and part, wherein described the 3rd patterning conductor layer of part directly is electrically connected with described first patterning conductor layer by described these the 3rd contact holes and described these second contact holes, and wherein described the 3rd patterning conductor layer of part is electrically connected with described first patterned semiconductor layer indirectly by described first patterning conductor layer and described second patterning conductor layer.

6. the manufacture method of active component array base board as claimed in claim 1 is characterized in that, the formation method of described second patterning conductor layer and described second patterned semiconductor layer comprises:

On described first dielectric layer, form one second conductor layer, one second semiconductor layer and a patterning photoresist layer in regular turn, wherein said patterning photoresist layer is covered on the subregion of described second semiconductor layer, and described patterning photoresist layer has one first block and one second block, and the thickness of described first block is greater than the thickness of described second block, and first block is corresponding to the active layers top; And

With described patterning photoresist layer is mask, and described second conductor layer of patterning and described second semiconductor layer are to form described hearth electrode, described active layers and described these contact conductors.

7. the manufacture method of active component array base board as claimed in claim 1, it is characterized in that, described second patterned semiconductor layer more comprises a plurality of plan semiconductor layers that are positioned on described these contact conductors, and the formation method of wherein said second patterning conductor layer and described second patterned semiconductor layer comprises:

On described first dielectric layer, form one second conductor layer, one second semiconductor layer and a patterning photoresist layer in regular turn;

With described patterning photoresist layer is mask, and described second conductor layer of patterning and described second semiconductor layer are intended semiconductor layer to form described hearth electrode, described active layers, described these contact conductors and described these; And

Described active layers and described plan semiconductor layer are carried out the side direction etching,, and make the size of the size of described active layers less than described these hearth electrodes so that described these are intended the size of the size of semiconductor layer less than described these contact conductors.

8. the manufacture method of active component array base board as claimed in claim 1 is characterized in that, the method that forms described these second contact holes in described second dielectric layer comprises:

On described second dielectric layer, form a patterning photoresist layer, wherein said patterning photoresist layer is covered on the subregion of described second semiconductor layer, and described patterning photoresist layer has one first block and one second block, and the thickness of described first block is greater than the thickness of described second block, and described second block is corresponding to described active layers top; And

With described patterning photoresist layer is mask, and described second dielectric layer of patterning is to form described these second contact holes.

9. the manufacture method of active component array base board as claimed in claim 1 is characterized in that, the method that forms described these second contact holes in described second dielectric layer comprises:

Described second dielectric layer forms a patterning photoresist layer, wherein said patterning photoresist layer is covered on the subregion of described second semiconductor layer, and described patterning photoresist layer has one first block and one second block, and the thickness of described first block is greater than the thickness of described second block, and described second block is corresponding to described active layers top; And

Described second dielectric layer of patterning is to form described these second contact holes.

10. the manufacture method of an active component array base board is characterized in that, described method comprises:

Form one first patterned semiconductor layer and a gate insulation layer on a substrate, wherein said gate insulation layer covers described first patterned semiconductor layer;

Be positioned at second patterned semiconductor layer on described first patterning conductor layer in forming one first patterning conductor layer and on the described gate insulation layer simultaneously, wherein said first patterning conductor layer comprises a plurality of grids and a hearth electrode, and described second patterned semiconductor layer comprises that one is positioned at the active layers on the described hearth electrode;

On described gate insulation layer, form one first dielectric layer, to cover described first patterning conductor layer;

Form one second patterning conductor layer on described first dielectric layer, wherein said second patterning conductor layer comprises a plurality of contact conductors that are positioned at described these first contact holes;

On described first dielectric layer, form one second dielectric layer;

Form a plurality of second contact holes in described second dielectric layer, wherein described these second contact holes of part are positioned at described active layers top;

In described first dielectric layer, form one the 3rd contact hole; And

Form one the 3rd patterning conductor layer on described second dielectric layer, wherein described the 3rd patterning conductor layer of part is electrically connected with described active layers by described these second contact holes of part and described the 3rd contact hole.

11. the manufacture method of active component array base board as claimed in claim 10 is characterized in that, the formation method of described first patterned semiconductor layer comprises:

On described substrate, form a plurality of island-shaped pattern; And

In described these island-shaped pattern, form a plurality of first type doped regions and a plurality of second type doped region.

12. the manufacture method of active component array base board as claimed in claim 11 is characterized in that, the formation method of described first patterning conductor layer and described second patterned semiconductor layer comprises:

On described gate insulation layer, form one first conductor layer and one second semiconductor layer in regular turn; And

Described first conductor layer of patterning and described second semiconductor layer, to form described hearth electrode and described active layers on described gate insulation layer, wherein described the 3rd patterning conductor layer of part directly is electrically connected with described first patterned semiconductor layer by described these first contact holes and described these second contact holes.

13. the manufacture method of active component array base board as claimed in claim 11 is characterized in that, described method more comprises:

14. the manufacture method of active component array base board as claimed in claim 11 is characterized in that, the formation method of described first patterning conductor layer and described second patterned semiconductor layer comprises:

On described gate insulation layer, form one first conductor layer, one second semiconductor layer and a patterning photoresist layer in regular turn, wherein said photoresist layer is covered on the subregion of described second semiconductor layer, and described photoresist layer has one first district and one second block, and the thickness of described first block is greater than the thickness of described second block, and first block is corresponding to the active layers top; And

With described patterning photoresist layer is mask, and described first conductor layer of patterning and described second semiconductor layer are to form described hearth electrode, described active layers, described these grids and to intend semiconductor layer.

15. the manufacture method of active component array base board as claimed in claim 11, it is characterized in that, described second patterned semiconductor layer more comprises a plurality of plan semiconductor layers that are positioned on described these grids, and the formation method of wherein said first patterning conductor layer and described second patterned semiconductor layer comprises:

On described gate insulation layer, form one first conductor layer, one second semiconductor layer and a patterning photoresist layer in regular turn;

With described patterning photoresist layer is mask, and described first conductor layer of patterning and described second semiconductor layer are intended semiconductor layer to form described hearth electrode, described active layers, described these grids and described these; And

Described active layers and described plan semiconductor layer are carried out the side direction etching,, and make the size of the size of described active layers less than described these hearth electrodes so that described these are intended the size of the size of semiconductor layer less than described these grids.

16. an active component array base board is characterized in that, described active component array base board comprises:

One substrate;

One first patterned semiconductor layer is disposed on the described substrate;

One gate insulation layer is disposed on the described substrate to cover described first patterned semiconductor layer;

One first patterning conductor layer is disposed on the described gate insulation layer;

One first dielectric layer is disposed on the described gate insulation layer to cover described first patterning conductor layer, and wherein said first dielectric layer and described gate insulation layer have a plurality of first contact holes that described first patterned semiconductor layer is exposed;

One second patterning conductor layer is disposed on described first dielectric layer, and wherein said second patterning conductor layer comprises a plurality of contact conductors and a hearth electrode;

One second patterned semiconductor layer is disposed on described second patterning conductor layer, and wherein said second patterned semiconductor layer comprises that one is positioned at the active layers on the described hearth electrode;

One second dielectric layer is disposed on described first dielectric layer, and wherein said second dielectric layer has a plurality of second contact holes so that described active layers is exposed; And

One the 3rd patterning conductor layer is disposed on described second dielectric layer, and wherein described the 3rd patterning conductor layer of part is electrically connected with described active layers by described these second contact holes of part.

17. active component array base board as claimed in claim 16, it is characterized in that, described first patterned semiconductor layer comprises a plurality of island-shaped pattern, and described these island-shaped pattern of part have a plurality of first type doped regions, and described these island-shaped pattern of part have a plurality of second type doped regions.

18. active component array base board as claimed in claim 16 is characterized in that, described second patterned semiconductor layer more comprises a plurality of plan semiconductor layers that are positioned on described these contact conductors.

19. an active component array base board is characterized in that, described active component array base board comprises:

One substrate;

One first patterned semiconductor layer is disposed on the described substrate;

One gate insulation layer is disposed on the described substrate, and wherein said gate insulation layer covers described first patterned semiconductor layer;

One first patterning conductor layer, wherein said first patterning conductor layer comprises a plurality of grids and a hearth electrode;

One second patterned semiconductor layer is disposed on described first patterning conductor layer, and wherein said second patterned semiconductor layer comprises that one is positioned at the active layers on the described hearth electrode;

One first dielectric layer is disposed on the described gate insulation layer, and to cover described first patterning conductor layer, wherein said first dielectric layer and described gate insulation layer have a plurality of first contact hole and one the 3rd contact holes that described first patterned semiconductor layer is exposed;

One second patterning conductor layer is disposed on described first dielectric layer, and wherein said second patterning conductor layer comprises a plurality of contact conductors that are positioned at described these first contact holes;

One second dielectric layer is disposed on described first dielectric layer, and wherein said second dielectric layer has a plurality of second contact holes, and described these second contact holes of part are positioned at described active layers top; And

One the 3rd patterning conductor layer is disposed on described second dielectric layer, and wherein described the 3rd patterning conductor layer of part is electrically connected with described active layers by described these second contact holes of part and described the 3rd contact hole.

20. active component array base board as claimed in claim 19, it is characterized in that, described first patterned semiconductor layer comprises a plurality of island-shaped pattern, and described these island-shaped pattern of part have a plurality of first type doped regions, and described these island-shaped pattern of part have a plurality of second type doped regions, wherein have a contact interface between described these the first type doped regions of part and described these second type doped regions, and described these first contact holes of part expose described contact interface.