CN101276790A - Method for preparing thin-film transistor array substrate and liquid crystal display panel - Google Patents
Method for preparing thin-film transistor array substrate and liquid crystal display panel Download PDFInfo
- Publication number
- CN101276790A CN101276790A CNA2008101086095A CN200810108609A CN101276790A CN 101276790 A CN101276790 A CN 101276790A CN A2008101086095 A CNA2008101086095 A CN A2008101086095A CN 200810108609 A CN200810108609 A CN 200810108609A CN 101276790 A CN101276790 A CN 101276790A
- Authority
- CN
- China
- Prior art keywords
- layer
- film transistor
- thin
- dielectric layer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a method for manufacturing thin film transistor array substrate and liquid crystal display panel, the method for manufacturing thin film transistor array substrate integrates the manufacturing of an optical sensor, a photosensitive dielectric layer is formed between a transparent conductive layer and a metal electrode to sense the external light. As the optical sensor uses the transparent conductive layer as an electrode, the external light can directly irradiate the photosensitive dielectric layer through the transparent conductive layer, dramatically increasing the sensitization area of the optical sensor and promoting the light sensing performance. In addition, another side of the photosensitive dielectric layer is metal electrode, therefore efficiently preventing the backlight from directly irradiating the photosensitive dielectric layer and avoiding the noise.
Description
Technical field
The invention relates to a kind of manufacture method of thin-film transistor array base-plate, and particularly relevant for a kind of manufacture method of having integrated the thin-film transistor array base-plate of optical sensor.
Background technology
Along with the universalness of liquid crystal and plasma display panel, flat-panel screens has become so-called " multimedia platform (Multimedia Board) " except viewing and admiring image.Ambient light (Ambient Light) sensing function that is integrated in the flat-panel screens is a kind of new motion of present Display Technique, and it mainly is a built-in optical sensor in flat-panel screens, uses the power of testing environment light.
Common ambient light detection technology is by low temperature polycrystalline silicon (Low TemperaturePoly-Silicon at present; LTPS) technology forms p-i-n (just mixing/do not mix/negative the doping) optical sensor on the glass substrate of display floater.Yet because process technology limit, this p-i-n optical sensor by LTPS technology made is understood because of polysilicon membrane thickness deficiency, and causes quantum effect (Quantum Effect, i.e. photoelectric conversion efficiency) not good.In addition, the light that backlight sent can pass through glass substrate direct irradiation p-i-n optical sensor, and influences the photobehavior of p-i-n optical sensor, makes signal to noise ratio (the Signal toNoise Ratio of photoreceptor signal; SNR) reduce, cause the measurement distortion.
Summary of the invention
The present invention is about a kind of manufacture method of having integrated the thin-film transistor array base-plate of optical sensor, and its optical sensor has bigger photosensitive area and light sensing usefulness.
The present invention is in addition about a kind of manufacture method of having integrated the thin-film transistor array base-plate of optical sensor, and it can effectively completely cut off the irradiation of backlight to optical sensor, makes optical sensor have and measures effect comparatively accurately.
For specifically describing content of the present invention, a kind of manufacture method of thin-film transistor array base-plate is proposed at this.At first, provide a substrate, it has a viewing area and a sensing area.And, form a patterned semiconductor layer on substrate, wherein patterned semiconductor layer comprises semiconductor block and one first storage electrode that is positioned at the viewing area.Then, the semiconductor region piece and first storage electrode are carried out ion doping, wherein be formed with one source pole doped region, a drain doping region and the channel region between source doping region and drain doping region in each semiconductor block.Then, form a gate insulation layer on substrate, make it cover the semiconductor block and first storage electrode.Then, form one first patterned metal layer on gate insulation layer, wherein first patterned metal layer comprises corresponding to a plurality of grids of channel region and corresponding to a plurality of second storage electrodes of first storage electrode.Then, form an interlayer dielectric layer on gate insulation layer, to cover first patterned metal layer.Afterwards, form a plurality of first interlayer holes in interlayer dielectric layer and gate insulation layer, wherein first interlayer hole exposes pairing source doping region, drain doping region and first storage electrode respectively.Then, form one second patterned metal layer on interlayer dielectric layer, wherein second patterned metal layer comprises a plurality of contacting metal connectors, a plurality of connection metal wire and one first sensing electrode.Each grid and pairing semiconductor block constitute one and show thin-film transistor, and each contacting metal connector is couple to the source doping region or the drain doping region of pairing demonstration thin-film transistor by pairing first interlayer hole.In addition, each first storage electrode, this gate insulation layer and pairing second storage electrode constitute a storage capacitors, and each connection metal wire is couple to pairing demonstration thin-film transistor by the contacting metal connector in pairing first interlayer hole with pairing storage capacitors.Then, form an actinodielectric layer on first sensing electrode, and form a protective layer on interlayer dielectric layer, to cover second patterned metal layer and actinodielectric layer.Then, form a plurality of second interlayer holes and a perforate in protective layer, wherein second interlayer hole exposes pairing connection metal wire respectively, and perforate exposes actinodielectric layer.Afterwards, form a patterned transparent conductive layer on protective layer, wherein patterned transparent conductive layer comprises a plurality of pixel electrodes and one second sensing electrode.Each pixel electrode is couple to pairing contacting metal connector by pairing second interlayer hole, and second sensing electrode is stacked on the actinodielectric layer by opening.
In one of the present invention embodiment, above-mentionedly semiconductor region piece and first storage electrode are carried out ion doping comprise respectively first storage electrode is carried out that first conductivity type mixes and the semiconductor region piece carried out second conductivity type mix, wherein this first conductivity type mixes to mix with this second conductivity type and is respectively P type ion doping and N type ion doping.
In one of the present invention embodiment, the above-mentioned step that the semiconductor region piece is carried out second ion doping is after the step that forms first patterned metal layer, with by grid as cover curtain, source doping region and drain doping region that it exposed are carried out ion doping.
In one of the present invention embodiment, the manufacture method of above-mentioned thin-film transistor array base-plate more is included in carries out ion doping to each semiconductor block and forms after source doping region, drain doping region and the channel region, each semiconductor block is carried out shallow ion to mix, with the shallow doped region of formation one source pole between source doping region and channel region, and between drain doping region and channel region, form the shallow doped region of a drain electrode.
In one of the present invention embodiment, above-mentioned substrate has more a peripheral circuit region, and during the demonstration thin-film transistor in forming the viewing area, forms a plurality of peripheral thin-film transistors more simultaneously in peripheral circuit region.
At this a kind of manufacture method of thin-film transistor array base-plate is proposed in addition.At first, one substrate is provided, it has a viewing area and a sensing area, and at least one demonstration thin-film transistor and at least one storage capacitors have been formed with in the viewing area, each shows that thin-film transistor is coupled to pairing storage capacitors, be formed with an interlayer dielectric layer on the substrate, cover demonstration thin-film transistor and storage capacitors.Then, form a plurality of first interlayer holes in interlayer dielectric layer, to expose each an one source pole doped region that shows thin-film transistor and a storage electrode of a drain doping region and each storage capacitors.Then, form one second patterned metal layer on interlayer dielectric layer, wherein second patterned metal layer comprises a plurality of contacting metal connectors, a plurality of connection metal wire and one first sensing electrode.Each contacting metal connector is couple to the source doping region or the drain doping region of pairing demonstration thin-film transistor by pairing first interlayer hole.In addition, each connection metal wire is couple to pairing demonstration thin-film transistor by pairing first interlayer hole with pairing storage capacitors.Then, form an actinodielectric layer on first sensing electrode, and form a protective layer on interlayer dielectric layer, to cover second patterned metal layer and actinodielectric layer.Afterwards, form a plurality of second interlayer holes and a perforate in protective layer, wherein second interlayer hole exposes pairing contacting metal connector respectively, and perforate exposes actinodielectric layer.Then; form a patterned transparent conductive layer on protective layer; wherein patterned transparent conductive layer comprises a plurality of pixel electrodes and one second sensing electrode; each pixel electrode is couple to pairing contacting metal connector by pairing second interlayer hole, and second sensing electrode contacts with actinodielectric layer by opening.
In the manufacture method of above-mentioned another kind of thin-film transistor array base-plate, substrate more can have a peripheral circuit region, have a plurality of peripheral thin-film transistors in it, and the interlayer dielectric layer of follow-up formation more covers peripheral thin-film transistor.
In one of the present invention embodiment, the formed actinodielectric layer of above-mentioned various manufacture methods comprises a silicic dielectric layer.
In one of the present invention embodiment, the method of the actinodielectric layer of above-mentioned formation comprises that carrying out chemical vapor deposition method forms silicic dielectric layer, then carry out quasi-molecule laser annealing technology, to form a silicon nanocrystal grain (Silicon Nanocrystal) dielectric layer on first sensing electrode.
The present invention is integrated in the making of optical sensor in the technology of thin-film transistor array base-plate, forms actinodielectric layer between transparency conducting layer and metal electrode, with the extraneous light of sensing.Wherein, because a side of actinodielectric layer is a transparency conducting layer, therefore extraneous light can directly shine photosensitive dielectric layer by transparency conducting layer, significantly increases the photosensitive area of optical sensor, and promotes its light sensing usefulness.In addition, the opposite side of actinodielectric layer is a metal electrode, therefore can effectively stop the actinodielectric layer of backlight direct irradiation, avoids possible noise effect.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is a kind of layout of having integrated the display panels of optical sensor according to one of the present invention embodiment;
Fig. 2 is the possible cross-sectional view of the display panels of Fig. 1;
Fig. 3 is a kind of thin-film transistor array base-plate according to one of the present invention embodiment;
Fig. 4 A～4J illustrates the technology of a kind of thin-film transistor array base-plate of one of the present invention embodiment in regular turn;
Fig. 5 for the formed a kind of optical sensor of the present invention when practical operation, its luminous intensity is with respect to the characteristic curve of photoelectric current;
Fig. 6 is a kind of display panels according to one embodiment of the invention, implements the system architecture to the sensing of ambient light.
[primary clustering symbol description]
100: display panels
110: the viewing area
120: periphery circuit region
130: sensing area
210: upper substrate
220: infrabasal plate
230: colored light-filtering units
240: dot structure
250: liquid crystal layer
260: optical sensor
270: frame glue
280,290: polaroid
300: thin-film transistor array base-plate
302: the viewing area
304: periphery circuit region
306: sensing area
310: show thin-film transistor
312: grid
314: semiconductor layer
314a: source doping region
314b: drain doping region
314c: channel region
314d: the shallow doped region of source electrode
314e: shallow doped region drains
316: the contacting metal connector
320: storage capacitors
322,324: storage electrode
326: connect metal wire
330: gate insulation layer
340: interlayer dielectric layer
350: protective layer
360: pixel electrode
370: peripheral thin-film transistor
372: grid
374: semiconductor layer
376: the contacting metal connector
380: optical sensor
382,386: sensing electrode
384: actinodielectric layer
402: the viewing area
404: periphery circuit region
406: sensing area
410: substrate
420: polysilicon layer
422: the semiconductor block
422a: source doping region
422b: drain doping region
422d: the shallow doped region of source electrode
422e: shallow doped region drains
422c: channel region
424,444: storage electrode
426: the semiconductor block
426a: source doping region
426b: drain doping region
426c: channel region
430: gate insulation layer
440: metal level
442,446: grid
450: interlayer dielectric layer
452: interlayer hole
454: silicon nitride layer
456: silicon oxide layer
460: metal level
462,466: the contacting metal connector
464: connect metal wire
468,494: sensing electrode
470: actinodielectric layer
480: protective layer
482: interlayer hole
484: perforate
490: transparency conducting layer
492: pixel electrode
510: show thin-film transistor
520: storage capacitors
530: peripheral thin-film transistor
540: optical sensor
610: display panels
612: the viewing area
614: optical sensor
620: sensing signal
630: controller
640: control signal
650: backlight
660: control signal
710: patterning cover curtain
720: patterning cover curtain
Embodiment
Please refer to Fig. 1, it illustrates a kind of layout of having integrated the display panels of optical sensor according to one of the present invention embodiment.As shown in Figure 1, display panels 100 periphery circuit region 120 and the sensing area 130 that have a viewing area 110 at least and be positioned at 110 peripheries, viewing area.Have a plurality of pixel cells in the viewing area 110, to show a picture frame picture.The possible driven unit of configuration in the periphery circuit region 120 is as scanner driver (Scan Driver) or data driver (Data Driver) etc.130 of sensing areas are used the power of testing environment light, and are regulated the brightness of display backlight source (Back-light) according to this in order to the configuration optical sensor, reach the effect of power saving.Simultaneously, by the power of testing environment light, also the brightness and contrast of regulator solution LCD panel automatically can not only slow down high brightness and the reflective eye fatigue of bringing, and can also reduce the energy consumption of display panels.
The zone that present embodiment is chosen in beyond the viewing area 110 is provided with sensing area 130, in order to the configuration optical sensor.Yet in other embodiments of the invention, the outer peripheral areas that is in close proximity to the viewing area in frame glue also may exist one to intend pixel region (dummy pixel region).At this moment, can select that also optical sensor is disposed at this and intend in the pixel region, and it can't have influence on the pixel display effect in other normal viewing area.
Fig. 2 further illustrates the cross-sectional view of the display panels of Fig. 1.As shown in Figure 2, display panels 100 has upper substrate 210 and infrabasal plate 220, wherein for example is formed with a plurality of colored light-filtering units 230 on the upper substrate 210, and for example is formed with a plurality of dot structures 240 on the infrabasal plate 220.In addition, liquid crystal layer 250 is sealed between upper substrate 210 and the infrabasal plate 220 by frame glue 270, and polaroid 280 and 290 is attached at the outer surface of upper substrate 210 and infrabasal plate 220 respectively.As Fig. 1 person of illustrating, present embodiment is integrated in the making of optical sensor 260 in the technology of infrabasal plate 220, and optical sensor 260 is disposed at viewing area 110 (with reference to Fig. 1) sensing region in addition.
The infrabasal plate 220 that the foregoing description is mentioned and on the assembly that may exist can be called as a thin-film transistor array base-plate, particularly, one low-temperature polysilicon film transistor array base palte wherein can form the required semiconductor layer of thin-film transistor by the low temperature polycrystalline silicon technology on substrate.To be example hereinafter, illustrate that the present invention is integrated in optical sensor the correlation technique content of the technology of thin-film transistor array base-plate with the low-temperature polysilicon film transistor array base palte.
Fig. 3 illustrates a kind of thin-film transistor array base-plate according to one of the present invention embodiment, and wherein for making graphic expression comparatively simple and clear, quantity may be represented for a plurality of assemblies may only illustrate one in Fig. 3.
Please refer to Fig. 3, thin-film transistor array base-plate 300 is divided at least viewing area 302, periphery circuit region 304 and sensing area 306.The demonstration thin-film transistor 310 that has arrayed in the viewing area 302, and under possible situation, the demonstration thin-film transistor 310 in the viewing area 302 can be in conjunction with a storage capacitors 320, so that preferable display effect to be provided.Show that thin-film transistor 310 mainly comprises assemblies such as grid 312, semiconductor layer 314, wherein the material of semiconductor layer 314 can be polysilicon (polysilicon), or other semi-conducting material, and more be formed with source doping region 314a, channel region 314c, drain doping region 314b in the semiconductor layer 314, and optionally make shallow doped region 314d of source electrode and the shallow doped region 314e of drain electrode.Wherein, source doping region 314a and drain doping region 314b can comply with electrical demand, exchange its name each other, and shallow doped region 314d of source electrode and the shallow doped region 314e of drain electrode are also together.Gate insulation layer 330 covers semiconductor layers 314, and gate insulation layer 330 is made of dielectric material, and grid 312 is positioned on the gate insulation layer 330 above the channel region 314c.In addition, the storage electrode 322 and the semiconductor layer 314 of storage capacitors 320 are similarly the polysilicon material, and the gate insulation layer 330 same storage electrodes 322 that cover.324 of the storage electrodes of storage capacitors 320 are positioned on the gate insulation layer 330 of storage electrode 322 tops, and wherein storage electrode 324 is all metal material mutually with grid 312.
Refer again to Fig. 3, interlayer dielectric layer 340 is positioned on the gate insulation layer 330, and the grid 312 of cover film transistor 310 and the storage electrode 324 of storage capacitors 320.Contacting metal connector (contact metalplug) 316 passes interlayer dielectric layer 340 and is couple to pairing source doping region 314a and drain doping region 314b with gate insulation layer 330.Connect metal wire 326 and pass interlayer dielectric layer 340 and gate insulation layer 330 via contacting metal connector 316, and with storage capacitors 320 electric property couplings to thin-film transistor 310.As shown in Figure 3, storage electrode 322 is electrically connected to drain doping region 314b via connecting metal wire 326.In addition, also dispose protective layer 350 on the interlayer dielectric layer 340, it covers contacting metal connector 316.Protective layer 350 tops also have pixel electrode 360, and it passes protective layer 350 downward electric property couplings to showing thin-film transistor 310.
Refer again to Fig. 3, for example have assemblies such as P type thin-film transistor, N type thin-film transistor or CMOS transistor in the periphery circuit region 304.A characteristic of the poly-silicon thin film transistor array substrate 300 that present embodiment disclosed is to be that viewing area 302 can be integrated in the identical technology with the assembly of periphery circuit region 304 to make.For example, the peripheral thin-film transistor 370 in the periphery circuit region 304 can be made simultaneously with the demonstration thin-film transistor 310 in the viewing area 302, and forms grid 372, semiconductor layer 374, contacting metal connector 376 etc.Furthermore, semiconductor layer 374 for example is to be formed by identical polysilicon material layer patterning with semiconductor layer 314, grid 372 for example is to be formed by identical metal layer patternization with grid 312, and contacting metal connector 376 then adopts identical processing step and metal material to make with contacting metal connector 316 and connection metal wire 326.
Refer again to Fig. 3; present embodiment forms optical sensor 380 in sensing area 306; it comprises the sensing electrode 382 that is positioned on the interlayer dielectric layer 340, is positioned at the actinodielectric layer 384 on the sensing electrode 382, and pass protective layer 350 and with actinodielectric layer 384 sensing electrode that contacts 386.Sensing electrode 382 can electrically connect signal read circuit, for example is arranged on peripheral circuit region 304, in order to read actinodielectric layer 384 luminous intensity that is sensed.In the present embodiment, sensing electrode 382 for example is to be formed by identical metal layer patternization with the grid 312 that shows thin-film transistor 310, and sensing electrode 386 for example is to be formed by identical transparency conducting layer patterning with pixel electrode 360.In addition, actinodielectric layer 384 for example is a silicic dielectric layer, and it is made to go up and adopts chemical vapor deposition method to form, utilize the process gas proportional control, reach excessive silicone content, make silicone content surpass proper chemical ratios (chemical equivalent), and form silicic dielectric layer.In addition, the quasi-molecule laser annealing technology of also can further optionally arranging in pairs or groups forms the silicon nanocrystal grain in silicic dielectric layer, particle diameter uses forming silicon nanocrystal grain (SiliconNanocrystal) dielectric layer between 0.5 to 200 nanometer (nm), to obtain preferable electrical and light sensing effect.The actual material that is suitable for for example can be silicon rich silicon oxide (silicon rich oxide; SiO
X), silicon-rich silicon nitride (silicon rich nitride; SiNy) or Silicon-rich silicon oxynitride (silicon rich oxynitride; SiOxNy) etc., wherein x is between 0.01 to 2, and y is between 0.01 to 1.33.The present invention is not limited to above-mentioned material, also can select for use other Silicon-rich compound to substitute.
For further specifying technology contents of the present invention, hereinafter more collocation diagram illustrates the manufacture method of thin-film transistor array base-plate of the present invention.
Please refer to Fig. 4 A～4J, it illustrates the technology of a kind of thin-film transistor array base-plate of one of the present invention embodiment in regular turn.
At first, shown in Fig. 4 A, provide substrate 410, and on substrate 410, form the semiconductor layer of patterning.Substrate 410 for example is glass substrate or plastic base, divides a viewing area 402, a periphery circuit region 404 and a sensing area 406 on it at least, and relevant configuration is as indicated above.The semiconductor layer of patterning for example is a polysilicon layer 420, can form through quasi-molecule laser annealing technology by the amorphous silicon material layer, and polysilicon layer 420 forms the semiconductor block 422 and storage electrode 424 that is positioned at viewing area 402 behind patterning, and the semiconductor block 426 that is positioned at periphery circuit region 404.
Then, shown in Fig. 4 B, forming a patterning cover curtain 710 on substrate 410, and the polysilicon layer 420 that this patterning cover curtain 710 is exposed is carried out first conductivity type mix, for example is P type (P+) ion doping.More specifically, patterning cover curtain 710 exposes storage electrode 424 and local semiconductor block 426, can make storage electrode 424 have conductivity by the P+ ion doping, and in semiconductor block 426, form source doping region 426a, drain doping region 426b and channel region 426c.
Then, shown in Fig. 4 C, form a gate insulation layer 430 on substrate 410, make it cover semiconductor block 426 and storage electrode 424, gate insulation layer 430 is made of dielectric material.And, shown in Fig. 4 D, on gate insulation layer 430, form a metal level 440, and metal level 440 carried out patterning, and form grid 442, storage electrode 444 with gate pole 446.At this moment, still remain with patterning cover curtain 720 on the metal level 440 after being patterned.Therefore, can carry out second conductivity type with metal level 440 as the cover curtain by remaining patterning cover curtain 720 mixes, for example be N type (N+) ion doping, and in the semiconductor block 422 that grid 442 is exposed, form source doping region 422a and drain doping region 422b.At this moment,, optionally use metallic shield (shielding mask) (not icon), cover zone in addition, viewing area 402 if only need the semiconductor block 426 of viewing area 402 is mixed.
Then, shown in Fig. 4 E, remaining patterning cover curtain 720 is waited to etching, and further remove metal level 440 partly by patterning cover curtain 720.At this moment, grid 442 after etched can further expose the semiconductor block 422 that partly is not doped, again the semiconductor block 422 that is exposed being carried out N type (N-) shallow ion afterwards mixes, and at the shallow doped region 422d of source electrode and the shallow doped region 422e that drains that form in the semiconductor block 422 shown in Fig. 4 E, and define channel region 422c, with the shallow doped region 422d of formation source electrode between source doping region 422a and channel region 422c, and between drain doping region 422b and channel region 422c, form the shallow doped region 422e of drain electrode.
Then, shown in Fig. 4 F, remove remaining patterning cover curtain 720, on gate insulation layer 430, form an interlayer dielectric layer 450, to cover metal level 440.And, form a plurality of interlayer holes 452 in interlayer dielectric layer 440 and gate insulation layer 430, exposing pairing source doping region 422a and 426a, drain doping region 422b and 426b respectively, and storage electrode 424.What deserves to be mentioned is that the composition of interlayer dielectric layer 450 herein can be individual layer or sandwich construction according to actual demand.More specifically, the material of interlayer dielectric layer 450 can be adjusted according to actinodielectric layer material of follow-up formation.With the interlayer dielectric layer 450 that present embodiment was illustrated is example, and it is by the silicon nitride layer on upper strata (silicon nitride; Si
3N
4) 454 with silicon oxide layer (the silicon oxide of lower floor; SiO
2) 456 compositions, the material of the actinodielectric layer of follow-up formation this moment just can adopt silicon rich silicon oxide (SiOx), selects the material that preferable etching selectivity is arranged with silicon nitride material for use.Moreover if interlayer dielectric layer 450 is the silicon oxide layer of individual layer, then the actinodielectric layer of follow-up formation just can adopt with silica material and the silicon-rich silicon nitride (SiNy) of preferable etching selectivity be arranged as material.
Then, shown in Fig. 4 G, on interlayer dielectric layer 450, form a metal level 460, and insert interlayer hole 452, and form contacting metal connector 462 and 466, and metal level 460 is carried out patterning, for example carry out little shadow and etch process, form connection metal wire 464 and sensing electrode 468.The material of metal level 460 also can be used other conductive material except metal, perhaps use laminated.Grid 442 constitutes one with pairing semiconductor block 422 and shows thin-film transistor 510, and contacting metal connector 462 is couple to the source doping region 422a or the drain doping region 422b of pairing demonstration thin-film transistor 510 by pairing interlayer hole 452.Storage electrode 424, gate insulation layer 430 and storage electrode 444 constitute a storage capacitors 520, and connect metal wire 464 by pairing first interlayer hole 452 and the contacting metal connector 462 in it, to pairing demonstration thin-film transistor 510, storage electrode 424 is electrically connected to drain doping region 422b via connecting metal wire 464 as shown in the figure with pairing storage capacitors 520 electric property couplings.In addition, the grid 446 that is positioned at periphery circuit region 404 constitutes a peripheral thin-film transistor 530 with pairing semiconductor block 426, and contacting metal connector 466 is couple to the source doping region 426a or the drain doping region 426b of pairing peripheral thin-film transistor 530 by pairing interlayer hole 452.
Then, shown in Fig. 4 H, form an actinodielectric layer 470 on sensing electrode 468.It for example is to starch reinforced chemical vapor deposition method by electricity to form silicic dielectric layer that formation makes the method for actinodielectric layer 470, for example is silicon rich silicon oxide layer, silicon-rich silicon nitride layer or Silicon-rich silicon oxynitride layer, or other silica-rich material layer.In addition, also alternative is further carried out quasi-molecule laser annealing technology or heating anneal technology to formed material layer, has the silicon nanocrystal grain dielectric layer of preferable electrical and light sensing characteristic with formation.
Then, shown in Fig. 4 I, form a protective layer 480 on interlayer dielectric layer 450, to cover metal level 460 and actinodielectric layer 470, protective layer 480 for example can be selected organic material layer for use, but double as is a flatness layer.And, forming a plurality of interlayer holes 482 and a perforate 484 in protective layer 480, its media layer window 482 exposes pairing connection metal wire 464 or contacting metal connector 462 or 466 respectively, and perforate 484 exposes actinodielectric layer 470.
Afterwards, shown in Fig. 4 J, form a transparency conducting layer 490 on protective layer 480, and transparency conducting layer 490 is carried out patterning, to form a pixel electrode 492 and a sensing electrode 494.The material of transparency conducting layer 490 for example is indium tin oxide (ITO), indium-zinc oxide (IZO) or other electrically conducting transparent material.Wherein pixel electrode 492 is couple to pairing metal connecting line 464 or contacting metal connector 462 by pairing interlayer hole 482, and sensing electrode 494 is stacked on the actinodielectric layer 470 by opening 484, and contacts with actinodielectric layer 470.So, just can form optical sensor 540, in order to the light variation of sensitive context by sensing electrode 494, actinodielectric layer 470 and sensing electrode 468.Wherein, because the sensing electrode 494 of optical sensor 540 is a transparency conducting layer, therefore extraneous light can be directly by the photosensitive dielectric layer 470 of sensing electrode 494 irradiations.On making, help significantly to increase the photosensitive area of optical sensor 540, and promote its light sensing usefulness.In addition, because sensing electrode 494 is a metal electrode, therefore can effectively stop the actinodielectric layer 470 of backlight direct irradiation, to avoid possible noise effect.
The foregoing description is that the light shield technology that adopts the light shield technology collocation of seven road CMOS (complementary doping film transistor) to make actinodielectric layer together is that example describes, show that wherein thin-film transistor can be N type doping film transistor (NMOS), peripheral thin-film transistor then can be P type doping film transistor (PMOS).Yet in not departing from the scope of the present invention, the visual actual state of dopant profile of the light shield technology of aforementioned seven road CMOS and demonstration thin-film transistor and peripheral thin-film transistor is changed.For example, the light shield technology of CMOS can all be used PMOS or all use the light shield technology of NMOS to replace.
For example, one of the present invention alternate embodiment also can be chosen in before the P type ion doping that carries out shown in Fig. 4 B, earlier the semiconductor layer that shows thin-film transistor is carried out N type ion doping, relatively need additionally to increase by one light shield technology and define the zone of N type ion doping this moment, and become the manufacture method that the light shield technology of actinodielectric layer is made in eight road CMOS light shield technology collocation altogether together.
In addition, another alternate embodiment of the present invention also can change the N type shallow ion doping of the self-aligned type shown in Fig. 4 E into the N type ion doping enforcement afterwards in aforementioned eight road CMOS light shield technologies.At this moment, relatively will need to increase again one light shield technology and define N type shallow ion doped regions, and become the manufacture method that the light shield technology of actinodielectric layer is made in nine road CMOS light shield technology collocation altogether together.
Moreover, though the demonstration thin-film transistor of previous embodiment is to be example with N type doping film transistor, and peripheral thin-film transistor is to be example with P type doping film transistor, but in fact, both dopant profile can be intercoursed and be P type ion doping and N type ion doping.In addition, the bottom electrode of aforementioned storage capacitors also can change into and adopt N type ion doping to make.
Fig. 5 illustrates a kind of optical sensor that the present invention forms when practical operation, and its luminous intensity is with respect to the characteristic curve of photoelectric current.In the embodiment that this gives an example, optical sensor after tested, the material of its top electrode are indium tin oxide, and bottom electrode is the metal level of titanium/aluminium/titanium, applying between top electrode and the bottom electrode under 3 volts the condition of bias voltage, can find that its photoelectric current and luminous intensity roughly are desirable linear relationship.In other words, optical sensor of the present invention really can be by practical application.
Fig. 6 illustrates a kind of display panels according to one of the present invention embodiment, implements the system architecture to the sensing of ambient light.As shown in Figure 6, display panels 610 has viewing area 612, and optical sensor 614 is disposed at outside the viewing area 612.During running, optical sensor 614 reception environment light, and corresponding output sensing signal 620 is to controller 630.Controller 630 receives after the sensing signal 620, can select corresponding output control signal 640 to backlight 650, to regulate the brightness of backlight, reaches the effect of power saving.In addition, controller 630 also can select corresponding output control signal 660 to display panels 610, with the power of foundation ambient light, the brightness and contrast of regulator solution LCD panel 610 demonstrations can certainly export control signal 640 and control signal 660 simultaneously automatically.So, help to slow down high brightness and the reflective eye fatigue that causes, also can reduce the energy consumption of display panels 610.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (16)
1. the manufacture method of a thin-film transistor array base-plate is characterized in that, comprising:
One substrate is provided, and this substrate has a viewing area and a sensing area at least;
Form a patterned semiconductor layer on this substrate, wherein this patterned semiconductor layer comprises semiconductor block and one first storage electrode that is positioned at this viewing area;
This semiconductor block and this first storage electrode are carried out an ion doping technology, wherein be formed with one source pole doped region, a drain doping region and the channel region between this source doping region and this drain doping region in this semiconductor block;
Form a gate insulation layer on this substrate, and cover this semiconductor block and this first storage electrode;
Form one first patterned metal layer on this gate insulation layer, wherein this first patterned metal layer comprises corresponding to a grid of this channel region and corresponding to one second storage electrode of this first storage electrode;
Form an interlayer dielectric layer on this gate insulation layer, and cover this first patterned metal layer;
Form a plurality of first interlayer holes in this interlayer dielectric layer and this gate insulation layer, wherein those first interlayer holes expose pairing this source doping region, this drain doping region and this first storage electrode respectively;
Form one second patterned metal layer on this interlayer dielectric layer, and insert in those first interlayer holes, wherein this second patterned metal layer comprises at least one connection metal wire and one first sensing electrode, and this first storage electrode is electrically connected to this drain doping region via this connection metal wire;
Form an actinodielectric layer on this first sensing electrode;
Form a protective layer on this interlayer dielectric layer, to cover this second patterned metal layer and this actinodielectric layer;
Form a plurality of second interlayer holes and a perforate in this protective layer, wherein those second interlayer holes expose pairing this connection metal wire respectively, and this perforate exposes this actinodielectric layer; And
Form a patterned transparent conductive layer on this protective layer; and insert in those second interlayer holes and this perforate; wherein this patterned transparent conductive layer comprises a pixel electrode and one second sensing electrode; this pixel electrode is couple to pairing this connection metal wire by pairing this second interlayer hole, and this second sensing electrode is stacked on this actinodielectric layer by this opening.
2. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, this semiconductor block and this first storage electrode are carried out ion doping comprise respectively those first storage electrodes are carried out that first conductivity type mixes and those semiconductor blocks carried out second conductivity type mix, wherein this first conductivity type mixes to mix with this second conductivity type and is respectively P type ion doping and N type ion doping.
3. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, the step that those semiconductor blocks are carried out ion doping is after the step that forms first patterned metal layer, with by this grid as cover curtain, this source doping region and this drain doping region that it exposed are carried out ion doping.
4. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, more be included in and each semiconductor block is carried out ion doping and form after this source doping region, this drain doping region and this channel region, dwindle this grid and with this grid as cover curtain, each semiconductor block is carried out shallow ion to mix, with the shallow doped region of formation one source pole between this source doping region and this channel region, and between this drain doping region and this channel region, form the shallow doped region of a drain electrode.
5. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, this substrate has more a peripheral circuit region, and in forming this viewing area those form a plurality of peripheral thin-film transistors in this peripheral circuit region when showing thin-film transistors more simultaneously.
6. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is characterized in that, this actinodielectric layer comprises a silicic dielectric layer.
7. the manufacture method of thin-film transistor array base-plate as claimed in claim 1 is characterized in that, the material of this silicic dielectric layer comprises silicon rich silicon oxide, silicon-rich silicon nitride, Silicon-rich silicon oxynitride and combination thereof.
8. the manufacture method of thin-film transistor array base-plate as claimed in claim 6 is characterized in that, the method that forms this silicic dielectric layer comprises carries out chemical vapor deposition method.
9. the manufacture method of thin-film transistor array base-plate as claimed in claim 6 is characterized in that, more comprises carrying out an excimer laser annealing process, forms a silicon nanocrystal grain dielectric layer with this silicic dielectric layer.
10. the manufacture method of a thin-film transistor array base-plate is characterized in that, comprising:
One substrate is provided, this substrate has a viewing area and a sensing area, and at least one demonstration thin-film transistor and at least one storage capacitors have been formed with in this viewing area, should show wherein that thin-film transistor was to should storage capacitors, and be formed with an interlayer dielectric layer on this substrate, show thin-film transistor and those storage capacitors to cover those;
Form a patterned metal layer on this interlayer dielectric layer, wherein this patterned metal layer comprises at least one connection metal wire and one first sensing electrode, and this storage capacitors is electrically connected to this demonstration thin-film transistor via this connection metal wire;
Form an actinodielectric layer on this first sensing electrode;
Form a protective layer on this interlayer dielectric layer, to cover this patterned metal layer and this actinodielectric layer;
Form an at least one interlayer hole and a perforate in this protective layer, wherein this interlayer hole exposes pairing this connection metal wire respectively, and this perforate exposes this actinodielectric layer; And
Form a patterned transparent conductive layer on this protective layer; and insert in this interlayer hole and this perforate; wherein this patterned transparent conductive layer comprises a pixel electrode and one second sensing electrode; this pixel electrode is couple to pairing this connection metal wire by pairing this interlayer hole, and this second sensing electrode is stacked on the actinodielectric layer by this opening.
11. the manufacture method of thin-film transistor array base-plate as claimed in claim 10, it is characterized in that, this substrate has more a peripheral circuit region, and has at least one peripheral thin-film transistor in this peripheral circuit region, and this interlayer dielectric layer of follow-up formation more covers those peripheral thin-film transistors.
12. the manufacture method of thin-film transistor array base-plate as claimed in claim 10 is characterized in that, this actinodielectric layer comprises a silicic dielectric layer.
13. the manufacture method of thin-film transistor array base-plate as claimed in claim 12 is characterized in that, the material of this silicic dielectric layer comprises silicon rich silicon oxide, silicon-rich silicon nitride, Silicon-rich silicon oxynitride and combination thereof.
14. the manufacture method of thin-film transistor array base-plate as claimed in claim 12 is characterized in that, the method that forms this silicic dielectric layer comprises carries out chemical vapor deposition method.
15. the manufacture method of thin-film transistor array base-plate as claimed in claim 12 is characterized in that, more comprises carrying out an excimer laser annealing process, forms a silicon nanocrystal grain dielectric layer with this silicic dielectric layer.
16. the manufacture method of a display panels is characterized in that, comprising:
One first substrate is provided, this first substrate has a viewing area and a sensing area, and at least one demonstration thin-film transistor and at least one storage capacitors have been formed with in this viewing area, should show wherein that thin-film transistor was to should storage capacitors, and be formed with an interlayer dielectric layer on this first substrate, show thin-film transistor and those storage capacitors to cover those;
Form a patterned metal layer on this interlayer dielectric layer, wherein this patterned metal layer comprises at least one connection metal wire and one first sensing electrode, and this storage capacitors is electrically connected to this demonstration thin-film transistor via this connection metal wire;
Form an actinodielectric layer on this first sensing electrode;
Form a protective layer on this interlayer dielectric layer, to cover this patterned metal layer and this actinodielectric layer;
Form an at least one interlayer hole and a perforate in this protective layer, wherein this interlayer hole exposes pairing this connection metal wire respectively, and this perforate exposes this actinodielectric layer;
Form a patterned transparent conductive layer on this protective layer, and insert in this interlayer hole and this perforate, wherein this patterned transparent conductive layer comprises a pixel electrode and one second sensing electrode, this pixel electrode is couple to pairing this connection metal wire by pairing this interlayer hole, and this second sensing electrode is stacked on the actinodielectric layer by this opening; And
One second substrate is assembled with this first substrate, and between this first base version and this second substrate, injected a liquid crystal layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101086095A CN101276790A (en) | 2008-05-21 | 2008-05-21 | Method for preparing thin-film transistor array substrate and liquid crystal display panel |
| CN200910006533XA CN101494202B (en) | 2008-05-21 | 2009-02-17 | Preparation method for thin-film transistor array substrate and liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101086095A CN101276790A (en) | 2008-05-21 | 2008-05-21 | Method for preparing thin-film transistor array substrate and liquid crystal display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101276790A true CN101276790A (en) | 2008-10-01 |
Family
ID=39996015
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008101086095A Pending CN101276790A (en) | 2008-05-21 | 2008-05-21 | Method for preparing thin-film transistor array substrate and liquid crystal display panel |
| CN200910006533XA Active CN101494202B (en) | 2008-05-21 | 2009-02-17 | Preparation method for thin-film transistor array substrate and liquid crystal display panel |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910006533XA Active CN101494202B (en) | 2008-05-21 | 2009-02-17 | Preparation method for thin-film transistor array substrate and liquid crystal display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN101276790A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102224453A (en) * | 2008-11-21 | 2011-10-19 | 夏普株式会社 | Liquid crystal display device and electronic device |
| CN103246098A (en) * | 2013-04-26 | 2013-08-14 | 北京京东方光电科技有限公司 | Display device and charging method thereof |
| CN101521243B (en) * | 2009-04-02 | 2014-10-15 | 友达光电股份有限公司 | Optical sensor and manufacture method thereof and display panel with same |
| CN107126219A (en) * | 2016-02-26 | 2017-09-05 | 三星显示有限公司 | Photosensitive thin film device and the biological information sensing device further containing photosensitive thin film device |
| CN107621857A (en) * | 2017-09-30 | 2018-01-23 | 联想(北京)有限公司 | A kind of display screen, electronic equipment and light-intensity test method |
| CN108735769A (en) * | 2018-08-25 | 2018-11-02 | Oppo广东移动通信有限公司 | Display screen component and electronic device |
| WO2019041594A1 (en) * | 2017-09-01 | 2019-03-07 | Boe Technology Group Co., Ltd. | Display substrate, display apparatus, method of controlling a display apparatus, and method of fabricating display substrate |
| CN109698378A (en) * | 2018-12-21 | 2019-04-30 | 华中科技大学 | A kind of light regulation lithium ion battery and preparation method thereof |
| CN109786399A (en) * | 2017-11-13 | 2019-05-21 | 群创光电股份有限公司 | Detection device |
| CN109801569A (en) * | 2019-03-28 | 2019-05-24 | 京东方科技集团股份有限公司 | A kind of array substrate, its production method and display device |
| WO2019161671A1 (en) * | 2018-02-24 | 2019-08-29 | 惠科股份有限公司 | Display substrate and manufacturing method therefor, and display panel |
| WO2020042755A1 (en) * | 2018-08-25 | 2020-03-05 | Oppo广东移动通信有限公司 | Display screen assembly and electronic apparatus |
| WO2020107723A1 (en) * | 2018-11-30 | 2020-06-04 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| US10890807B2 (en) | 2018-02-24 | 2021-01-12 | HKC Corporation Limited | Display substrate, manufacturing method of the display substrate, and display panel |
| CN113641024A (en) * | 2021-08-09 | 2021-11-12 | 武汉华星光电技术有限公司 | Display panel and preparation method thereof |
| CN113968185A (en) * | 2021-11-29 | 2022-01-25 | 北京京东方技术开发有限公司 | Rearview mirror, anti-dazzle method of rearview mirror and vehicle |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101789450B (en) * | 2010-01-26 | 2012-02-01 | 友达光电股份有限公司 | Thin film transistor and method for manufacturing silicon-rich channel layer |
| CN102508376B (en) * | 2011-12-15 | 2014-07-16 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and manufacturing method thereof |
| US8546209B1 (en) * | 2012-06-15 | 2013-10-01 | International Business Machines Corporation | Replacement metal gate processing with reduced interlevel dielectric layer etch rate |
| CN104465702B (en) * | 2014-11-03 | 2019-12-10 | 深圳市华星光电技术有限公司 | Manufacturing method of AMOLED (active matrix/organic light emitting diode) backboard |
| CN104701326A (en) * | 2015-03-19 | 2015-06-10 | 京东方科技集团股份有限公司 | Array substrate and manufacture method thereof and display device |
| TWI672621B (en) * | 2018-07-24 | 2019-09-21 | 友達光電股份有限公司 | Display device and sensing element substrate |
| CN112928134B (en) * | 2021-02-03 | 2022-09-09 | 武汉华星光电技术有限公司 | Array substrate and display panel |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100382817B1 (en) * | 1999-01-20 | 2003-05-09 | 엘지.필립스 엘시디 주식회사 | A pattern for detecting the living things and thin film transistor optical sensor with the same |
| CN100517075C (en) * | 2006-03-09 | 2009-07-22 | 北京京东方光电科技有限公司 | Manufacturing method for array substrate of thin film transistor LCD |
| KR20080001769A (en) * | 2006-06-30 | 2008-01-04 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display device and fabricating method of the same |
-
2008
- 2008-05-21 CN CNA2008101086095A patent/CN101276790A/en active Pending
-
2009
- 2009-02-17 CN CN200910006533XA patent/CN101494202B/en active Active
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102224453A (en) * | 2008-11-21 | 2011-10-19 | 夏普株式会社 | Liquid crystal display device and electronic device |
| CN102224453B (en) * | 2008-11-21 | 2014-03-12 | 夏普株式会社 | Liquid crystal display device and electronic device |
| CN101521243B (en) * | 2009-04-02 | 2014-10-15 | 友达光电股份有限公司 | Optical sensor and manufacture method thereof and display panel with same |
| WO2014173147A1 (en) * | 2013-04-26 | 2014-10-30 | 京东方科技集团股份有限公司 | Display device and charging method therefor |
| CN103246098A (en) * | 2013-04-26 | 2013-08-14 | 北京京东方光电科技有限公司 | Display device and charging method thereof |
| CN103246098B (en) * | 2013-04-26 | 2015-06-10 | 北京京东方光电科技有限公司 | Display device and charging method thereof |
| CN107126219A (en) * | 2016-02-26 | 2017-09-05 | 三星显示有限公司 | Photosensitive thin film device and the biological information sensing device further containing photosensitive thin film device |
| CN107126219B (en) * | 2016-02-26 | 2022-06-03 | 三星显示有限公司 | Photosensitive thin film device and biometric information sensing apparatus including the same |
| US11093084B2 (en) | 2017-09-01 | 2021-08-17 | Boe Technology Group Co., Ltd. | Display substrate, display apparatus, method of controlling a display apparatus, and method of fabricating display substrate |
| WO2019041594A1 (en) * | 2017-09-01 | 2019-03-07 | Boe Technology Group Co., Ltd. | Display substrate, display apparatus, method of controlling a display apparatus, and method of fabricating display substrate |
| CN107621857A (en) * | 2017-09-30 | 2018-01-23 | 联想(北京)有限公司 | A kind of display screen, electronic equipment and light-intensity test method |
| CN109786399A (en) * | 2017-11-13 | 2019-05-21 | 群创光电股份有限公司 | Detection device |
| WO2019161671A1 (en) * | 2018-02-24 | 2019-08-29 | 惠科股份有限公司 | Display substrate and manufacturing method therefor, and display panel |
| US10890807B2 (en) | 2018-02-24 | 2021-01-12 | HKC Corporation Limited | Display substrate, manufacturing method of the display substrate, and display panel |
| WO2020042755A1 (en) * | 2018-08-25 | 2020-03-05 | Oppo广东移动通信有限公司 | Display screen assembly and electronic apparatus |
| CN108735769A (en) * | 2018-08-25 | 2018-11-02 | Oppo广东移动通信有限公司 | Display screen component and electronic device |
| WO2020107723A1 (en) * | 2018-11-30 | 2020-06-04 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN109698378A (en) * | 2018-12-21 | 2019-04-30 | 华中科技大学 | A kind of light regulation lithium ion battery and preparation method thereof |
| CN109801569A (en) * | 2019-03-28 | 2019-05-24 | 京东方科技集团股份有限公司 | A kind of array substrate, its production method and display device |
| US11538871B2 (en) | 2019-03-28 | 2022-12-27 | Beijing Boe Technology Development Co., Ltd. | Array substrate and fabricating method thereof, and display apparatus |
| CN113641024A (en) * | 2021-08-09 | 2021-11-12 | 武汉华星光电技术有限公司 | Display panel and preparation method thereof |
| CN113641024B (en) * | 2021-08-09 | 2024-01-05 | 武汉华星光电技术有限公司 | Display panel and preparation method thereof |
| CN113968185A (en) * | 2021-11-29 | 2022-01-25 | 北京京东方技术开发有限公司 | Rearview mirror, anti-dazzle method of rearview mirror and vehicle |
| CN113968185B (en) * | 2021-11-29 | 2024-05-28 | 北京京东方技术开发有限公司 | Rear-view mirror, anti-dazzle method for rear-view mirror and vehicle |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101494202B (en) | 2010-12-08 |
| CN101494202A (en) | 2009-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101494202B (en) | Preparation method for thin-film transistor array substrate and liquid crystal display panel | |
| CN100426489C (en) | Semiconductor device and method of manufacturing thereof | |
| US6847422B2 (en) | Liquid crystal display device and method of manufacturing the same | |
| US6399933B2 (en) | Active matrix display device and method of manufacturing the same | |
| CN101285975B (en) | Light sensing unit and pixel structure possessing the light sensing unit and liquid crystal display panel | |
| CN102354695B (en) | Display and manufacturing method thereof | |
| US8415182B2 (en) | Manufacturing method of thin film transistor array substrate and liquid crystal display panel | |
| CN101118915B (en) | Optical sensing element and manufacturing method | |
| JP2002216960A (en) | Pixel element structure of oled display and its manufacturing method | |
| CN101964353B (en) | Organic electro-luminescence display unit and manufacturing thereof | |
| CN101635276A (en) | Touch control panel of organic luminous diode and manufacture method thereof | |
| CN105470197A (en) | Production method of low temperature poly silicon array substrate | |
| CN102314034A (en) | Active element, pixel structure, driving circuit and display panel | |
| US8063464B2 (en) | Photo detector and method for forming thereof | |
| CN100444405C (en) | Double grid film electric crystal and pixel structure and its producing method | |
| CN101981676B (en) | Semiconductor device, semiconductor device manufacturing method, liquid crystal display device and electronic apparatus | |
| CN100521253C (en) | Photosensing element, method of manufacturing the same and display panel using the photosensing element | |
| US20070051954A1 (en) | TFT array substrate of TFT LCD having large storage capcitor and method for manufacturing same | |
| CN102591054A (en) | Liquid crystal display panel | |
| CN101510530B (en) | Active element array substrate and manufacturing method therefor | |
| CN100555642C (en) | Optical pickocff and preparation method thereof | |
| CN106298955A (en) | Low-temperature polysilicon film transistor and preparation method thereof, liquid crystal panel and display | |
| CN100520547C (en) | Manufacturing method for pixel structure of LCD | |
| CN100521254C (en) | Photosensing element and its manufacture method | |
| CN101097370B (en) | Liquid crystal display and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |