CN104752208A - Manufacturing method and structure of LDMOS device - Google Patents
Manufacturing method and structure of LDMOS device Download PDFInfo
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- CN104752208A CN104752208A CN201310739299.8A CN201310739299A CN104752208A CN 104752208 A CN104752208 A CN 104752208A CN 201310739299 A CN201310739299 A CN 201310739299A CN 104752208 A CN104752208 A CN 104752208A
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- dielectric layer
- gate dielectric
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- ldmos device
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 238000002955 isolation Methods 0.000 claims abstract description 45
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 230000000717 retained effect Effects 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method and a structure of an LDMOS device. Photoresist is used to block a sacrificial layer disposed at the two sides of the edges of isolation grooves. The part, disposed at the two sides of the edges of the isolation grooves, of the sacrificial layer can be retained when the exposed part of the sacrificial layer is removed. Then, a gate dielectric layer is formed to cover the part, disposed at the two sides of the edges of the isolation grooves, of the sacrificial layer. The thickness of a dielectric layer disposed at the two sides of the edges of the isolation grooves is increased, and the reliability of the device is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of manufacture method and structure of LDMOS device.
Background technology
In integrated circuit, different devices, circuit gather together and realize specific function by usual needs, and different devices has different fundamental operation characteristics, different voltage is needed to drive, but different operating voltages needs the thickness of different gate oxides to carry, the gate oxide producing different-thickness is therefore usually needed to carry out the integration of realizing circuit.
Containing high-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor, Laterally Diffused Metal Oxide Semiconductor) CMOS technology be exactly the integration of the gate oxide manufacturing two or three different-thickness in integrated circuits, realizing circuit.Due to the usual thinner thickness of gate oxide, also comparatively responsive, therefore gate oxide is also one of link the weakest in ic manufacturing process.Its manufacturing process is comparatively complicated, and process window is narrower, requires high with the compatible degree of front and back technique.If occur, little deviation is just easy to cause yield loss, and therefore, industry generally believes that gate oxide is one of technique easily gone wrong most aborning.
Common high-voltage LDMOS gate oxide is thicker, but, in the process of its growth, be easy to form the defects such as shallow ridges (DIVOT) in the edge of active area and isolation channel (STI), cause at active area and isolation channel) the gate oxide thickness of edge thinner.Device easily forms larger electrical potential difference in the edge of active area and isolation channel, and the reliability of thinner gate oxide is inadequate, and cause device reactance voltage breakdown capability to decline, serious even directly causes whole chip failure.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method and structure of LDMOS device, the thickness of the gate dielectric layer of isolation channel edge can be improved, improve the reliability of device.
To achieve these goals, the present invention proposes a kind of manufacture method of LDMOS device, comprise step:
There is provided semiconductor base, described semiconductor base is formed with isolation channel and well region, and is provided with higher-pressure region;
Form sacrifice layer on the surface of described semiconductor base, described sacrifice layer is kept apart by described isolation channel;
The isolation channel of described higher-pressure region forms photoresist layer, and described photoresist layer coverage is greater than the edge of isolation channel, shelters from the partial sacrificial layer being positioned at described isolation channel both sides;
With described photoresist layer for mask, remove the sacrifice layer exposed;
Remove described photoresist layer;
The semiconductor base of described higher-pressure region forms gate dielectric layer, and described gate dielectric layer covers the partial sacrificial layer being positioned at described isolation channel both sides;
Described gate dielectric layer forms grid.
Further, in the manufacture method of described LDMOS device, the scope of described sacrificial layer thickness is
Further, in the manufacture method of described LDMOS device, the material of described sacrifice layer is silica.
Further, in the manufacture method of described LDMOS device, described semiconductor base is also provided with device region.
Further, in the manufacture method of described LDMOS device, described gate dielectric layer comprises first grid dielectric layer and second gate dielectric layer.
Further, in the manufacture method of described LDMOS device, the semiconductor base of described higher-pressure region is formed in gate dielectric layer, the step forming described gate dielectric layer comprises:
The semiconductor base of described higher-pressure region is formed first grid dielectric layer, and described first grid dielectric layer covers the partial sacrificial layer being positioned at described isolation channel both sides;
The semiconductor base of described higher-pressure region and device region forms second gate dielectric layer, and described second gate dielectric layer covers first grid dielectric layer.
Further, in the manufacture method of described LDMOS device, the material of described first grid dielectric layer and second gate dielectric layer is silica.
Further, in the manufacture method of described LDMOS device, the thickness of described first grid dielectric layer is greater than the thickness of described second gate dielectric layer.
Further, in the manufacture method of described LDMOS device, form grid on the surface of described second gate dielectric layer.
Further, in the manufacture method of described LDMOS device, the material of described grid is polysilicon.
Further, the invention allows for a kind of LDMOS device structure, adopt as above any one method is formed, described structure comprises: the semiconductor base being provided with higher-pressure region, be formed at the isolation channel in described semiconductor base, be positioned at the sacrifice layer of described isolation channel both sides of edges, described sacrifice layer exposes semiconductor base, be formed at the gate dielectric layer of described semiconductor substrate surface, described gate dielectric layer covers described sacrifice layer and is formed at the grid on described gate dielectric layer surface.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: use photoresistance to shelter from the sacrifice layer being positioned at isolation channel both sides of edges, the sacrifice layer being positioned at isolation channel both sides of edges can be retained when removing the sacrifice layer exposed, then form gate dielectric layer and cover the sacrifice layer being positioned at isolation channel both sides of edges, add the thickness being positioned at isolation channel both sides of edges dielectric layer, improve the reliability of device.
Accompanying drawing explanation
Fig. 1 is the flow chart of the manufacture method of LDMOS device in one embodiment of the invention;
Fig. 2 to Fig. 6 is the generalized section in the manufacture method process of LDMOS device in one embodiment of the invention.
Embodiment
Below in conjunction with schematic diagram, the manufacture method of LDMOS device of the present invention and structure are described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 1, in the present embodiment, propose a kind of manufacture method of LDMOS device, comprise step:
S100: semiconductor base 100 is provided, described semiconductor base 100 is formed with isolation channel 110 and well region (scheming not shown), and is provided with higher-pressure region 1 and device region 2, wherein, implementing isolation channel 110 is arranged in described higher-pressure region 1 and device region 2 for multiple spacing, as shown in Figure 2;
S200: form sacrifice layer 200 on the surface of described semiconductor base 100, described sacrifice layer 200 is kept apart by described isolation channel 110, as shown in Figure 2;
In step s 200, the material of described sacrifice layer 200 is silica, and adopt chemical vapour deposition (CVD) mode to be formed, the scope of its thickness is
, be such as
.
S300: form photoresist layer 300 on the isolation channel 110 of described higher-pressure region 1, described photoresist layer 300 shelters from the partial sacrificial layer 200 being positioned at described isolation channel 110 both sides, as shown in Figure 3;
In step S300, described photoresist layer 300 have employed exposure-processed, and it blocks a part of sacrifice layer 200, exposes the sacrifice layer 200 of remainder.
S400: with described photoresist layer 300 for mask, removes the sacrifice layer 200 exposed, as shown in Figure 4;
In step S400, wet etching is adopted to remove the sacrifice layer 200 exposed, owing to there is blocking of described photoresist layer 300, when adopting wet etching, the partial sacrificial layer 200 being positioned at described isolation channel 110 both sides can be retained, increase the thickness being positioned at the dielectric layer of described isolation channel 110 both sides.
S500: remove described photoresist layer 300, as shown in Figure 4;
S600: form gate dielectric layer on the semiconductor base 100 of described higher-pressure region 1, described gate dielectric layer covers the partial sacrificial layer 200 being positioned at described isolation channel 110 both sides, as illustrated in Figures 5 and 6;
In step S600, described gate dielectric layer comprises first grid dielectric layer 410 and second gate dielectric layer 420, and the forming step of described gate dielectric layer comprises:
The semiconductor base 100 of described higher-pressure region 1 forms first grid dielectric layer 410, and described first grid dielectric layer 410 covers the partial sacrificial layer 200 being positioned at described isolation channel 110 both sides;
Wherein, in this step, can all form first grid dielectric layer 410 on the surface of described higher-pressure region 1 and device region 2, then use etching to remove the first grid dielectric layer 410 being positioned at surface, described device region 2, only retain the first grid dielectric layer 410 being positioned at surface, described higher-pressure region 1, as shown in Figure 5.
The semiconductor base 100 of described higher-pressure region 1 and device region 2 forms second gate dielectric layer 420, and described second gate dielectric layer 420 covers first grid dielectric layer 410, as shown in Figure 6.
In the present embodiment, the material of described first grid dielectric layer 410 and second gate dielectric layer 420 is silica, as gate oxide, wherein, the thickness of described first grid dielectric layer 410 is greater than the thickness of described second gate dielectric layer 420, because described first grid dielectric layer 410 is positioned at higher-pressure region 1, its thickness thicklyer should could form high tension apparatus.Meanwhile, the sacrifice layer 200 due to the reservation in described higher-pressure region 1 also can serve as the effect of gate oxide, improves the thickness of the gate oxide at isolation channel 110 edge, thus can improve the reliability of the device of formation.
S700: form grid (scheming not shown) on the surface of described second gate dielectric layer 420, form LDMOS device, wherein, described grid is polysilicon.
In the present embodiment, also proposed a kind of LDMOS device structure, adopt as method is above formed, described structure comprises: the semiconductor base 100 being provided with higher-pressure region 1, be formed at the isolation channel 110 in described semiconductor base 100, be positioned at the sacrifice layer 200 of described isolation channel 110 both sides of edges, described sacrifice layer 200 exposes semiconductor base 100, be formed at the gate dielectric layer on described semiconductor base 100 surface, described gate dielectric layer covers described sacrifice layer 200 and is formed at the grid on described gate dielectric layer surface.
To sum up, in the manufacture method of the LDMOS device provided in the embodiment of the present invention and structure, photoresistance is used to shelter from the sacrifice layer being positioned at isolation channel both sides of edges, the sacrifice layer being positioned at isolation channel both sides of edges can be retained when removing the sacrifice layer exposed, then form gate dielectric layer and cover the sacrifice layer being positioned at isolation channel both sides of edges, add the thickness being positioned at isolation channel both sides of edges dielectric layer, improve the reliability of device.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (11)
1. a manufacture method for LDMOS device, comprises step:
There is provided semiconductor base, described semiconductor base is formed with isolation channel and well region, and is provided with higher-pressure region;
Form sacrifice layer on the surface of described semiconductor base, described sacrifice layer is kept apart by described isolation channel;
The isolation channel of described higher-pressure region forms photoresist layer, and described photoresist layer shelters from the partial sacrificial layer being positioned at described isolation channel both sides;
With described photoresist layer for mask, remove the sacrifice layer exposed;
Remove described photoresist layer;
The semiconductor base of described higher-pressure region forms gate dielectric layer, and described gate dielectric layer covers the partial sacrificial layer being positioned at described isolation channel both sides;
Described gate dielectric layer forms grid.
2. the manufacture method of LDMOS device as claimed in claim 1, it is characterized in that, the scope of described sacrificial layer thickness is
3. the manufacture method of LDMOS device as claimed in claim 1, it is characterized in that, the material of described sacrifice layer is silica.
4. the manufacture method of LDMOS device as claimed in claim 1, it is characterized in that, described semiconductor base is also provided with device region.
5. the manufacture method of LDMOS device as claimed in claim 4, it is characterized in that, described gate dielectric layer comprises first grid dielectric layer and second gate dielectric layer.
6. the manufacture method of LDMOS device as claimed in claim 5, it is characterized in that, the semiconductor base of described higher-pressure region is formed in gate dielectric layer, and the step forming described gate dielectric layer comprises:
The semiconductor base of described higher-pressure region is formed first grid dielectric layer, and described first grid dielectric layer covers the partial sacrificial layer being positioned at described isolation channel both sides;
The semiconductor base of described higher-pressure region and device region forms second gate dielectric layer, and described second gate dielectric layer covers first grid dielectric layer.
7. the manufacture method of LDMOS device as claimed in claim 6, it is characterized in that, the material of described first grid dielectric layer and second gate dielectric layer is silica.
8. the manufacture method of LDMOS device as claimed in claim 7, it is characterized in that, the thickness of described first grid dielectric layer is greater than the thickness of described second gate dielectric layer.
9. the manufacture method of LDMOS device as claimed in claim 8, is characterized in that, forms grid on the surface of described second gate dielectric layer.
10. the manufacture method of LDMOS device as claimed in claim 9, it is characterized in that, the material of described grid is polysilicon.
11. 1 kinds of LDMOS device structures, adopt as any one method in claim 1 to 10 is formed, described structure comprises: the semiconductor base being provided with higher-pressure region, be formed at the isolation channel in described semiconductor base, be positioned at the sacrifice layer of described isolation channel both sides of edges, described sacrifice layer exposes semiconductor base, is formed at the gate dielectric layer of described semiconductor substrate surface, and described gate dielectric layer covers described sacrifice layer and is formed at the grid on described gate dielectric layer surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310739299.8A CN104752208A (en) | 2013-12-27 | 2013-12-27 | Manufacturing method and structure of LDMOS device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310739299.8A CN104752208A (en) | 2013-12-27 | 2013-12-27 | Manufacturing method and structure of LDMOS device |
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| CN104752208A true CN104752208A (en) | 2015-07-01 |
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| CN201310739299.8A Pending CN104752208A (en) | 2013-12-27 | 2013-12-27 | Manufacturing method and structure of LDMOS device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090072308A1 (en) * | 2007-09-18 | 2009-03-19 | Chin-Lung Chen | Laterally diffused metal-oxide-semiconductor device and method of making the same |
| US20100006937A1 (en) * | 2008-07-09 | 2010-01-14 | Yong Jun Lee | Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) Device and Method of Manufacturing LDMOS Device |
| CN102097476A (en) * | 2009-12-03 | 2011-06-15 | 台湾积体电路制造股份有限公司 | Integrated circuit structure and formation method thereof |
| CN102315251A (en) * | 2010-07-06 | 2012-01-11 | 瑞萨电子株式会社 | The manufacturing approach of semiconductor device and semiconductor device |
-
2013
- 2013-12-27 CN CN201310739299.8A patent/CN104752208A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090072308A1 (en) * | 2007-09-18 | 2009-03-19 | Chin-Lung Chen | Laterally diffused metal-oxide-semiconductor device and method of making the same |
| US20100006937A1 (en) * | 2008-07-09 | 2010-01-14 | Yong Jun Lee | Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) Device and Method of Manufacturing LDMOS Device |
| CN102097476A (en) * | 2009-12-03 | 2011-06-15 | 台湾积体电路制造股份有限公司 | Integrated circuit structure and formation method thereof |
| CN102315251A (en) * | 2010-07-06 | 2012-01-11 | 瑞萨电子株式会社 | The manufacturing approach of semiconductor device and semiconductor device |
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