CN114121629A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN114121629A CN114121629A CN202111327356.2A CN202111327356A CN114121629A CN 114121629 A CN114121629 A CN 114121629A CN 202111327356 A CN202111327356 A CN 202111327356A CN 114121629 A CN114121629 A CN 114121629A
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- side wall
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 64
- 229920005591 polysilicon Polymers 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 31
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 28
- 229910021332 silicide Inorganic materials 0.000 claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 102
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
Abstract
The invention provides a semiconductor device and a manufacturing method thereof.A substrate is provided, a gate oxide layer is formed on the surface of the substrate, and a polysilicon gate with a gap is formed on the gate oxide layer; forming silicon oxide layers on two sides of the polysilicon gate; depositing a silicon nitride layer; carrying out a first etching process to remove the silicon nitride layer covering the gate oxide layer and the top of the polysilicon gate and form a first side wall on the side surface of the silicon oxide layer; removing the exposed gate oxide layer on the surface of the substrate by utilizing a photoetching process; depositing a silicon nitride layer; and carrying out a second etching process to remove the silicon nitride layer covering the top of the substrate and the polysilicon gate and form a secondary side wall on the side surface of the primary side wall, so that the silicon oxide layer, the primary side wall and the secondary side wall jointly form a side wall structure of the polysilicon gate. The invention can protect the gate oxide layer from being damaged by the subsequent process while ensuring the thickness of the side wall structure, and reduce the fluctuation of the threshold voltage of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.
Background
With the development of semiconductor technology, High Voltage (HV) chip plays an increasingly important role in internet of things and LED display driving, and the difficulty of integrating HV device and MV device in the semiconductor process of 28nm and below is increasing. In HKMG-based semiconductor processes, MV devices typically require a metal gate CMP process to achieve better planarity by notching (Slot) the gate, as shown in fig. 1. Notching the gate exposes the gate oxide layer, as shown in fig. 2, where the solid circles 13 are the exposed gate oxide layer. Subsequent etching to remove the gate oxide layer over the source/drain regions and the trenched region exposes the sides of the gate oxide layer under the gate completely, as shown in fig. 3, where the solid coil 14 is the side of the gate oxide layer under the gate exposed by etching to remove the gate oxide layer.
The exposed side 14 of the gate oxide layer may be damaged by ion implantation, Physical Vapor Deposition (PVD) NiPt during the subsequent processes of forming source/drain and forming metal silicide, as shown in fig. 4, and the damage of the gate oxide layer may greatly affect the stability of the threshold voltage (Vt) of the MV device.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor device and a method for manufacturing the same, which are used to solve the problem in the prior art that the gate oxide is damaged to affect the stability of the threshold voltage.
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate, wherein a gate oxide layer is formed on the surface of the substrate, and a polysilicon gate with a gap is formed on the gate oxide layer; the polysilicon gate comprises a dielectric layer, polysilicon positioned on the dielectric layer, a hard mask layer positioned on the polysilicon and a first side wall;
forming silicon oxide layers on two sides of the polysilicon gate;
depositing a silicon nitride layer, wherein the silicon nitride layer covers the surface of the gate oxide layer and the surface of the polysilicon gate;
fourthly, performing a first etching process to remove the silicon nitride layer covering the gate oxide layer and the top of the polysilicon gate and form a first side wall on the side surface of the silicon oxide layer;
fifthly, removing the exposed gate oxide layer on the surface of the substrate by utilizing a photoetching process;
depositing a silicon nitride layer, wherein the silicon nitride layer covers the surface of the substrate and the surface of the polysilicon gate;
seventhly, performing a second etching process to remove the silicon nitride layer covering the substrate and the top of the polysilicon gate, forming a secondary side wall on the side surface of the primary side wall, and forming a side wall structure of the polysilicon gate by the silicon oxide layer, the primary side wall and the secondary side wall;
eighthly, with the polysilicon gate and the side wall structure as masks, performing impurity ion implantation on the substrate to form a source drain electrode;
and ninthly, forming metal silicide on the gap and the source and drain electrodes.
Preferably, the hard mask layer in the first step includes an upper oxide layer and a lower nitride layer.
Preferably, in the first step, a gap is formed in the polysilicon gate by patterning the polysilicon gate.
Preferably, in the first step, the first side wall is made of silicon oxide or silicon nitride.
Preferably, the thickness of the sidewall structure in the seventh step is the same as that of the sidewall structure formed in the prior art.
Preferably, the method further comprises: and removing the polysilicon gate, and forming a metal gate in the polysilicon gate removing area.
The present invention also provides a semiconductor device comprising:
a substrate;
a source and drain formed in the substrate;
a gate oxide layer formed over the substrate;
a metal gate formed over the gate oxide layer;
a gap formed in the metal gate and over the substrate;
the side wall structures are formed on two sides of the metal gate;
the metal silicide is formed above the gap and the source and drain electrodes;
the side wall structure comprises a silicon oxide layer, a primary side wall and a secondary side wall.
The invention splits the formation of the side wall structure into two times, wherein the first time is before the gate oxide is removed, and the second time is after the gate oxide is removed. The side wall formed after the gate oxide is removed can effectively protect the side face of the exposed gate oxide layer from being damaged by the subsequent processing, so that the gate oxide layer is greatly protected, and the fluctuation of the threshold voltage of the semiconductor device is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of trenching on a gate;
FIG. 2 is a schematic diagram of a gate oxide layer exposed by trenching on a gate;
FIG. 3 is a schematic side view of a gate oxide layer under a gate exposed by etching to remove a gate oxide layer over a source/drain region and a trench region;
FIG. 4 is a schematic view showing the side of the gate oxide layer under the exposed gate being damaged;
fig. 5 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 6 to 14 are schematic structural views showing steps in the method of manufacturing a semiconductor device according to the embodiment of the present invention;
fig. 15 shows a schematic view of a semiconductor device which is an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout this specification, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
The side wall is a process for defining the width of a Lightly Doped Drain (LDD) area and a source-drain junction and protecting a grid electrode during through hole etching, and is a structure which is manufactured on two sides of the grid electrode side wall (offset spacer) of the grid electrode through deposition, etching and other processes.
Fig. 5 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
As shown in fig. 5, the method comprises the following steps:
step one, as shown in fig. 6, providing a substrate 101, forming a gate oxide layer 102 on the surface of the substrate, and forming a polysilicon gate with a gap 107 on the gate oxide layer 102; the polysilicon gate includes a dielectric layer 103, polysilicon 104 on the dielectric layer, a hard mask layer on the polysilicon, and first sidewalls 108.
In an embodiment of the present invention, the hard mask layer includes a lower nitride layer 105 and an upper oxide layer 106. Specifically, the lower nitride layer 105 is SiN, and the upper oxide layer 106 is SiO 2.
Metal gates having high dielectric constant gate dielectric layers are commonly employed in processes below 28nm, often abbreviated as HKMG, where HK denotes a high dielectric constant (HK) gate dielectric layer and MG denotes a metal gate. In the forming process of the HKMG, in order to solve the problems of serious height loss and poor process controllability of a metal gate caused by a metal gate CMP process due to large area of the metal gate, a gap (Slot) is inserted in polysilicon to improve the controllability of the metal gate CMP process. As shown in fig. 6, a gap 107 is formed over the gate oxide layer 102. In an embodiment of the present invention, the gap 107 is formed in the polysilicon gate by patterning the polysilicon gate. Preferably, the gaps 107 are uniformly arranged in the polysilicon gate, and the number of the gaps 107 may be one or more according to actual needs. In the embodiment of the present invention, as shown in fig. 6, there is one gap 107.
The side wall is made of silicon oxide, silicon nitride or silicon oxynitride, and can be of a single-layer or multi-layer (more than or equal to two-layer) stacked structure. In the embodiment of the present invention, the first sidewall spacers 108 are a single-layer structure made of silicon oxide or silicon nitride material. The first side walls 108 can increase the channel length of the formed transistor, reduce short channel effects and hot carrier effects caused by the short channel effects, and serve as masks for subsequent LDD lightly doped source/drain ion implantation.
In step two, as shown in fig. 7, silicon oxide layers 109 are formed on both sides of the polysilicon gate.
Specifically, the step of forming the silicon oxide layer includes the steps of:
depositing a silicon oxide layer, wherein the silicon oxide layer covers the surfaces of the gate oxide layer and the polysilicon gate;
and b, performing an etching process to remove the silicon oxide layer covering the gate oxide layer and the top of the polysilicon gate. Thereby, silicon oxide layers 109 are formed on both sides of the polysilicon gate.
And step three, as shown in fig. 8, depositing a silicon nitride layer 110, wherein the silicon nitride layer 110 covers the surface of the gate oxide layer 102 and the surface of the polysilicon gate.
Step four, as shown in fig. 9, a first etching process is performed to remove the silicon nitride layer 110 covering the gate oxide layer 102 and the top of the polysilicon gate, and an initial sidewall 111 is formed on the side surface of the silicon oxide layer 109.
The first etching process adopts anisotropic etching. In the embodiment of the present invention, after the first etching process is performed, the surface of the gate oxide layer 102 and the silicon nitride layer 110 on the top of the polysilicon gate are removed, and the thickness of the formed initial sidewall 111 is not limited in the embodiment of the present invention, and is based on the thickness required in the actual process.
Step five, as shown in fig. 10, the gate oxide layer 102 exposed on the surface of the substrate 101 is removed by using a photolithography etching process.
Specifically, the step five comprises the following steps:
d, forming a photoresist layer with patterns of the polysilicon gate, the silicon oxide layer 109 and the initial side wall 111;
e, etching the gate oxide layer which is not blocked by the photoresist by using the photoresist layer as a mask through dry etching;
and f, removing the photoresist layer.
As shown in fig. 10, after etching, only the portion of the gate oxide layer 102 under the polysilicon gate 3 remains. The sides of the gate oxide layer under the polysilicon gate 3 are exposed.
Step six, as shown in fig. 11, a silicon nitride layer 112 is deposited, and the silicon nitride layer 112 covers the surface of the substrate 101 and the surface of the polysilicon gate.
Step seven, as shown in fig. 12, a second etching process is performed to remove the silicon nitride layer 112 covering the substrate 101 and the top of the polysilicon gate, and a secondary sidewall 113 is formed on the side surface of the initial sidewall 111.
The silicon oxide layer 109, the primary side wall 111 and the secondary side wall 113 together form a side wall structure of the polysilicon gate. In the embodiment of the invention, the thickness of the side wall structure is the same as that of the side wall structure formed by the prior art. That is, the total thickness of the silicon oxide layer 109, the primary side wall 111 and the secondary side wall 113 formed in two times before and after is the same as the thickness of the side wall structure in the prior art, so that the thickness of the side wall structure of the polysilicon gate is ensured to be unchanged.
Step eight, as shown in fig. 13, impurity ions are implanted into the substrate 101 by using the polysilicon gate and the sidewall structures as masks to form the source/drain 114.
At this time, impurity ions are implanted, and the secondary sidewall 113 protects the exposed side of the gate oxide layer.
Step nine, as shown in fig. 14, a metal silicide 115 is formed on the gap 107 and the source and drain 114.
Specifically, the ninth step includes the following steps:
step g, depositing NiPt and TiN by using a physical vapor deposition sputtering process;
h, carrying out first annealing treatment to generate high-resistance metal silicide Ni2 PtSi;
step i, removing TiN and NiPt which does not react with silicon by wet etching;
and j, carrying out secondary annealing treatment to convert the high-resistance state Ni2PtSi into low-resistance state NiPtSi 2.
Of course, a process step of forming a metal silicide blocking layer (SAB) is also included before step nine.
Similarly, the presence of the secondary sidewall 113 largely protects the gate oxide layer 102 from the process of forming the metal silicide 115, thereby ensuring the stability of the threshold voltage of the device.
In addition, the method for manufacturing a semiconductor device according to the embodiment of the present invention further includes: and step ten, removing the polysilicon gate and depositing to form a metal gate.
In the prior art, a complete sidewall structure is usually formed before step five, that is, before etching to remove gate oxide above a gap region and a source/drain formation region, which causes the side surface of a gate oxide layer below a polysilicon gate exposed by etching the gate oxide to be subjected to subsequent processes, for example, ion implantation is performed to form a source/drain, and a NiPt layer is deposited to damage the gate oxide layer, so that the gate oxide layer is corroded and damaged by impurity ions, resulting in fluctuation of the threshold voltage of a device. In the embodiment of the invention, the formation of the side wall structure is divided into two times, wherein one time is before the gate oxide is removed, the other time is after the gate oxide is removed, and the side wall formed after the gate oxide is removed can protect the exposed gate oxide layer from being damaged by the subsequent processing to a great extent, so that the stability of the threshold voltage of the device is improved.
Fig. 15 shows a schematic view of a semiconductor device which is an embodiment of the present invention. As shown in fig. 15, the device includes a substrate 101, a source/drain 114 formed in the substrate, a gate oxide layer 102 formed over the substrate, a metal gate 116 formed over the gate oxide layer and having a gap 107, a sidewall structure formed on both sides of the metal gate, and a metal silicide 115 formed over the gap 107 and the drain 114. The side wall structure comprises a silicon oxide layer 109, a primary side wall 111 and a secondary side wall 113. In addition, the semiconductor device of the embodiment of the present invention further includes a shallow trench isolation structure 117 formed in the substrate 101.
It will be appreciated that many other layers may be present, such as spacing elements and/or other suitable components, which are omitted from the illustration for simplicity.
The forming process of the side wall structure of the semiconductor device comprises the following steps: forming silicon oxide layers on two sides of the polysilicon gate; depositing a silicon nitride layer; performing a first etching process to remove the silicon nitride layer covering the gate oxide layer and the top of the polysilicon gate and form a first side wall on the side surface of the silicon oxide layer; removing the exposed gate oxide layer on the surface of the substrate by utilizing a photoetching process; depositing a silicon nitride layer; and carrying out a second etching process to remove the silicon nitride layer covering the top of the substrate and the polysilicon gate, forming a secondary side wall on the side surface of the primary side wall, and forming a side wall structure of the polysilicon gate by the silicon oxide layer, the primary side wall and the secondary side wall.
The semiconductor device of the embodiment of the invention ensures the thickness of the side wall structure, simultaneously protects the gate oxide from being damaged by the subsequent process, and improves the stability of the threshold voltage (Vt) of the semiconductor device.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate, wherein a gate oxide layer is formed on the surface of the substrate, and a polysilicon gate with a gap is formed on the gate oxide layer; the polysilicon gate comprises a dielectric layer, polysilicon positioned on the dielectric layer, a hard mask layer positioned on the polysilicon and a first side wall;
forming silicon oxide layers on two sides of the polysilicon gate;
depositing a silicon nitride layer, wherein the silicon nitride layer covers the surface of the gate oxide layer and the surface of the polysilicon gate;
fourthly, performing a first etching process to remove the silicon nitride layer covering the gate oxide layer and the top of the polysilicon gate and form a first side wall on the side surface of the silicon oxide layer;
fifthly, removing the exposed gate oxide layer on the surface of the substrate by utilizing a photoetching process;
depositing a silicon nitride layer, wherein the silicon nitride layer covers the surface of the substrate and the surface of the polysilicon gate;
seventhly, performing a second etching process to remove the silicon nitride layer covering the substrate and the top of the polysilicon gate, forming a secondary side wall on the side surface of the primary side wall, and forming a side wall structure of the polysilicon gate by the silicon oxide layer, the primary side wall and the secondary side wall;
eighthly, with the polysilicon gate and the side wall structure as masks, performing impurity ion implantation on the substrate to form a source drain electrode;
and ninthly, forming metal silicide on the gap and the source and drain electrodes.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the hard mask layer in the first step comprises an upper oxide layer and a lower nitride layer.
3. The method of manufacturing a semiconductor device according to claim 1, wherein a gap is formed in the polysilicon gate by patterning the polysilicon gate in the first step.
4. The method for manufacturing a semiconductor device according to claim 1, wherein in the first step, the first sidewall spacers are made of silicon oxide or silicon nitride.
5. The method according to claim 1, wherein the thickness of the sidewall structure in the seventh step is the same as the thickness of the sidewall structure formed by the conventional process.
6. The method for manufacturing a semiconductor device according to claim 1, further comprising: and removing the polysilicon gate, and forming a metal gate in the polysilicon gate removing area.
7. A semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 1 to 6, comprising at least:
a substrate;
a source and drain formed in the substrate;
a gate oxide layer formed over the substrate;
a metal gate formed over the gate oxide layer;
a gap formed in the metal gate and over the substrate;
the side wall structures are formed on two sides of the metal gate;
the metal silicide is formed above the gap and the source and drain electrodes;
the side wall structure comprises a silicon oxide layer, a primary side wall and a secondary side wall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111327356.2A CN114121629A (en) | 2021-11-10 | 2021-11-10 | Semiconductor device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111327356.2A CN114121629A (en) | 2021-11-10 | 2021-11-10 | Semiconductor device and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN114121629A true CN114121629A (en) | 2022-03-01 |
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| CN202111327356.2A Pending CN114121629A (en) | 2021-11-10 | 2021-11-10 | Semiconductor device and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114388358A (en) * | 2022-03-24 | 2022-04-22 | 晶芯成(北京)科技有限公司 | Method for manufacturing semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114388358A (en) * | 2022-03-24 | 2022-04-22 | 晶芯成(北京)科技有限公司 | Method for manufacturing semiconductor device |
| CN114388358B (en) * | 2022-03-24 | 2022-06-17 | 晶芯成(北京)科技有限公司 | Method for manufacturing semiconductor device |
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