CN105009093A - 对具有有限耐写性的高速缓存的集间损耗矫平 - Google Patents

对具有有限耐写性的高速缓存的集间损耗矫平 Download PDF

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Publication number
CN105009093A
CN105009093A CN201480009440.1A CN201480009440A CN105009093A CN 105009093 A CN105009093 A CN 105009093A CN 201480009440 A CN201480009440 A CN 201480009440A CN 105009093 A CN105009093 A CN 105009093A
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CN
China
Prior art keywords
cache
memory
swap
register
swapreg
Prior art date
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Pending
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CN201480009440.1A
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English (en)
Chinese (zh)
Inventor
X·董
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Qualcomm Inc
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Qualcomm Inc
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Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105009093A publication Critical patent/CN105009093A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
CN201480009440.1A 2013-02-21 2014-02-12 对具有有限耐写性的高速缓存的集间损耗矫平 Pending CN105009093A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/772,400 2013-02-21
US13/772,400 US9348743B2 (en) 2013-02-21 2013-02-21 Inter-set wear-leveling for caches with limited write endurance
PCT/US2014/015994 WO2014130317A1 (en) 2013-02-21 2014-02-12 Inter-set wear-leveling for caches with limited write endurance

Publications (1)

Publication Number Publication Date
CN105009093A true CN105009093A (zh) 2015-10-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480009440.1A Pending CN105009093A (zh) 2013-02-21 2014-02-12 对具有有限耐写性的高速缓存的集间损耗矫平

Country Status (6)

Country Link
US (1) US9348743B2 (https=)
EP (1) EP2959390A1 (https=)
JP (1) JP2016507847A (https=)
KR (1) KR20150119921A (https=)
CN (1) CN105009093A (https=)
WO (1) WO2014130317A1 (https=)

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CN111771184A (zh) * 2018-03-23 2020-10-13 美光科技公司 用于检测和减轻存储器媒体降级的方法以及使用所述方法的存储器装置
CN112214422A (zh) * 2019-07-12 2021-01-12 美光科技公司 静态slc高速缓存的动态大小

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US9921969B2 (en) 2015-07-14 2018-03-20 Western Digital Technologies, Inc. Generation of random address mapping in non-volatile memories using local and global interleaving
US10445232B2 (en) 2015-07-14 2019-10-15 Western Digital Technologies, Inc. Determining control states for address mapping in non-volatile memories
US10452560B2 (en) 2015-07-14 2019-10-22 Western Digital Technologies, Inc. Wear leveling in non-volatile memories
US10452533B2 (en) 2015-07-14 2019-10-22 Western Digital Technologies, Inc. Access network for address mapping in non-volatile memories
KR102788924B1 (ko) 2016-06-27 2025-04-02 에스케이하이닉스 주식회사 메모리 시스템, 이의 어드레스 맵핑 방법 및 억세스 방법
US10248571B2 (en) * 2016-08-11 2019-04-02 Hewlett Packard Enterprise Development Lp Saving position of a wear level rotation
US10101964B2 (en) 2016-09-20 2018-10-16 Advanced Micro Devices, Inc. Ring buffer including a preload buffer
US10503649B2 (en) * 2016-11-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit and address mapping method for cache memory
CN108920386B (zh) * 2018-07-20 2020-06-26 中兴通讯股份有限公司 面向非易失性内存的磨损均衡及访问方法、设备和存储介质
US11537307B2 (en) * 2018-08-23 2022-12-27 Micron Technology, Inc. Hybrid wear leveling for in-place data replacement media
US10761739B2 (en) 2018-08-23 2020-09-01 Micron Technology, Inc. Multi-level wear leveling for non-volatile memory
US11194582B2 (en) 2019-07-31 2021-12-07 Micron Technology, Inc. Cache systems for main and speculative threads of processors
US12223172B2 (en) * 2022-12-28 2025-02-11 SK hynix NAND Product Solutions Corporation Systems, methods, and media for controlling background wear leveling in solid-state drives

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CN111771184A (zh) * 2018-03-23 2020-10-13 美光科技公司 用于检测和减轻存储器媒体降级的方法以及使用所述方法的存储器装置
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CN111771184B (zh) * 2018-03-23 2022-09-09 美光科技公司 用于操作包含存储器阵列的存储器装置的方法和装置
CN112214422A (zh) * 2019-07-12 2021-01-12 美光科技公司 静态slc高速缓存的动态大小

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Publication number Publication date
US20140237160A1 (en) 2014-08-21
US9348743B2 (en) 2016-05-24
JP2016507847A (ja) 2016-03-10
WO2014130317A1 (en) 2014-08-28
EP2959390A1 (en) 2015-12-30
KR20150119921A (ko) 2015-10-26

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Application publication date: 20151028