CN104993826A - Frequency dividing method and frequency dividing device - Google Patents
Frequency dividing method and frequency dividing device Download PDFInfo
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Abstract
The invention relates to a frequency dividing method and a frequency dividing device. The method comprises the steps that a first calculating module and a second calculating module respectively generate a counting initial value m and a counting initial value a according to a frequency dividing ratio N preset in a first register; a reset device controls a first counter to acquire the counting initial value m and controls a second counter to acquire the counting initial value a, and a P/(P+1) prescaler sends a prescale signal to the first counter and the second counter separately, so that the first counter and the second counter can count; when stopping counting, the first counter sends a first control signal to the reset device, so that the reset device outputs a high level signal according to the first control signal; when stopping counting, the second counter sends a second control signal to the reset device, so that the reset device outputs a low level signal according to the second control signal. A mapping from the frequency dividing ratio N to the counting initial value m and the counting initial value a is realized through two calculating modules, thereby remarkably saving the area compared with a mapping table manner.
Description
Technical field
The present invention relates to frequency splitting technology, particularly relate to a kind of dividing method and device thereof.
Background technology
Modern communication technology is maked rapid progress, and various wireless communication standard emerges in an endless stream.In the reception of signal with in launching, frequency synthesizer is a kind of important module, be used for producing stable, accurately, the local oscillation signal of low noise and the mixing of reception (transmitting) signal.For realizing wider communications frequency range and narrower channel width, frequency synthesizer needs a frequency dividing ratio wide ranges, programmable decimal frequency divider.Based on continuous by frequency dividing ratio, the programmable integer frequency divider of decimal frequency divider.
A conventional programmable frequency divider is that frequency divider is swallowed in pulse, and primarily of P (P+1) pre-divider, the counter A of counting modulus value to be counter M and the counting modulus value of m be a forms.During frequency divider operation, voltage controlled oscillator (VCO) exports an oscillator signal and enters frequency divider, and frequency divider is first to this oscillator signal counting a cycle of (P+1) *, then skill counting P* (m-a) the individual cycle.A frequency divider output cycle just comprises P*m+a input cycle, so frequency dividing ratio N=P*m+a.Often feed a frequency dividing ratio N, all need to produce corresponding m and a, if by the method for tabling look-up, larger chip area can be taken when the frequency dividing ratio scope that cover is very wide.
Summary of the invention
For above-mentioned technical problem, an object of the present invention is to provide a kind of dividing method, and it can realize a kind of brand-new mode and complete the mapping of frequency dividing ratio N to count value, reduces the area occupied of chip.
One of for achieving the above object, the present invention adopts following technical scheme:
A kind of dividing method, comprises the steps:
Step one: the first computing module produces counting initial value m according to the frequency dividing ratio N defaulted in the first register, the second computing module produces counting initial value a according to the frequency dividing ratio N defaulted in the first register and initial value m;
Step 2: reset device controls the first counter and obtain counting initial value m from the first computing module, and control the second counter obtains counting initial value a from the second computing module, and m>a >=1;
Step 3: frequency dividing ratio is obtain pre-fractional frequency signal after the input signal of P/ (P+1) the pre-divider voltage controlled oscillator in future of P/ (P+1) carries out pre-frequency division, and this pre-fractional frequency signal is sent to the first counter and the second counter respectively, count to make the first counter and the second counter;
When step 4 first rolling counters forward stops, sending first and control signal to reset device, export high level signal to make reset device according to this first control signal; When second rolling counters forward stops, sending second and control signal to reset device, to make reset device according to this second control signal output low level signal, described frequency dividing ratio N=P*m+a.
Preferably, also comprise the steps: after described step 4
Step 5: when described first rolling counters forward stops, reset device control P/ (P+1) pre-divider carries out the pre-frequency division that frequency dividing ratio is P, when second rolling counters forward stops, reset device control P/ (P+1) pre-divider carries out the pre-frequency division that frequency dividing ratio is (P+1).
Preferably, the step that in described step 3, the first counter carries out counting comprises:
Step 31a: the first counter i with the formula
1=m-1 starts counting, wherein, and i
1it is the count value of the first counter;
Step 32a: judge this count value i
1whether be greater than 1, if so, then return step 31a, otherwise the first rolling counters forward stops;
The step that in described step 3, the second counter carries out counting comprises:
Step 31b: the second counter i with the formula
2=a-1 starts counting, wherein, and i
2it is the count value of the second counter;
Step 32b: judge this count value i
2whether be greater than 1, if so, then return step 31b, otherwise the second rolling counters forward stops.
Described step 4 specifically comprises following sub-step:
Step 41: the second rolling counters forward stops, the second counter sends second and controls signal to reset device;
Step 42: reset device is according to this second control signal signal output low level signal;
Step 43: the first rolling counters forward stops, the first counter sends first and controls signal to reset device;
Step 44: reset device exports high level signal according to this first control signal.
Two of object of the present invention is to provide a kind of frequency divider, and it can realize a kind of function of dividing method.
For achieving the above object two, the present invention adopts following technical scheme:
A kind of frequency divider, comprise the first computing module, the second computing module, the first counter, the second counter, reset device and P/ (P+1) pre-divider, described first computing module, for producing counting initial value m according to the frequency dividing ratio N defaulted in the first outside register; Described second computing module, produces initial value a for the initial value m produced according to the frequency dividing ratio N defaulted in the first register and the first computing module; Described reset device, obtain counting initial value m, and control the second counter obtains counting initial value a from the second computing module for controlling the first counter from the first computing module; Described P/ (P+1) pre-divider, for future voltage controlled oscillator input signal carry out pre-frequency division after obtain pre-fractional frequency signal, and this pre-fractional frequency signal is sent to the first counter and the second counter respectively; Described first counter, for starting to count to count initial value m according to pre-fractional frequency signal, and when counting stopping, sending first and controlling signal to reset device, export high level signal to make reset device according to this first control signal; Described second counter, for starting to count to count initial value a according to pre-fractional frequency signal, and when counting stopping, sending second and controlling signal to reset device, to make reset device according to this second control signal output low level signal.
Preferably, described counting initial value m> counts initial value a >=1.
Preferably, when described first rolling counters forward stops, reset device control P/ (P+1) pre-divider carries out the pre-frequency division that frequency dividing ratio is P, when second rolling counters forward stops, reset device control P/ (P+1) pre-divider carries out the pre-frequency division that frequency dividing ratio is (P+1).
Preferably, described first computing module comprises first adder, divider and the second register, the output of described first register is all connected with the input of first adder with the output of the second register, the output of described adder is connected with the input of divider, and described second computing module is all connected with the output of divider with the first counter.
Preferred further, described second computing module comprises multiplier and second adder, the input of described multiplier is connected with the output of divider, and the output of described multiplier connects the input of second adder, and the output of second adder connects the second counter.
Compared to prior art, beneficial effect of the present invention is:
The present invention is by the first computing module and the second computing module, realize the mapping of frequency dividing ratio N to counting initial value m and counting initial value a, instead of in conventional art the mode needing to be obtained corresponding m and a from frequency dividing ratio N by gimmick of tabling look-up, save the area of frequency divider in a large number, have good flexibility and adaptability.
Accompanying drawing explanation
Fig. 1 is the workflow diagram of a kind of dividing method of the embodiment of the present invention;
Fig. 2 is the cut-away view of the first computing module of the embodiment of the present invention;
Fig. 3 is the cut-away view of the second computing module of the embodiment of the present invention;
Fig. 4 is the module frame chart of a kind of frequency divider of the embodiment of the present invention.
Embodiment
Below, by reference to the accompanying drawings and embodiment, the present invention is described further:
See Fig. 1, the invention provides a kind of dividing method, it is as follows that it comprises step:
Step s1: the first computing module produces counting initial value m according to the frequency dividing ratio N defaulted in the first register, and the second computing module produces counting initial value a according to the frequency dividing ratio N defaulted in the first register and initial value m;
In above-mentioned steps s1, frequency dividing ratio N carries out being pre-set in the first register according to actual conditions, first computing module and the interior of the second computing module have logical circuit respectively, see Fig. 2, first computing module is inner by first adder, second register and divider are formed, see Fig. 3, second computing module inside is made up of multiplier and second adder, the output of the first register is all connected with the input of first adder with the output of the second register, the output of adder is connected with the input of divider, second computing module is all connected with the output of divider with the first counter, the input of multiplier is connected with the output of divider, and the output of multiplier connects the input of second adder, and the output of second adder connects the second counter.First computing module produces counting initial value m=floor (N-K)/P, in addition, N=P*m+a, wherein, N defaults in the frequency dividing ratio in the first register, K is the parameter introduced, K defaults in the second register, and K can select according to the scope of frequency dividing ratio N, floor function representation fractions omitted part, P is the frequency dividing ratio of P/ (P+1) pre-divider in the present embodiment, describes in detail below to this P/ (P+1) pre-divider.In this step, as long as one powers on, first computing module and the second computing module will produce corresponding initial value according to frequency dividing ratio N automatically respectively, do not need other signal controlling, all fixedly establish when programming circuitry for parameter K and frequency dividing ratio P, therefore the first computing module and the second computing module have known the numerical value of parameter K and frequency dividing ratio P in advance, in fact, first computing module first works than the second computing module, first computing module is according to frequency dividing ratio N, frequency dividing ratio P and parameter K can calculate initial value m, second computing module is according to frequency dividing ratio P afterwards, frequency dividing ratio N and initial value m obtains initial value a, because these two computing modules are all logical operations, speed quickly, the time that first computing module first works than the second computing module is almost negligible.
Step s2: reset device controls the first counter and obtain counting initial value m from the first computing module, and control the second counter obtains counting initial value a from the second computing module, and m>a >=1;
For step s2, reset device constantly sends acquisition and controls signal to the first counter and the second counter, after first counter and the second counter receive this acquisition control signal, respectively acquisition counting initial value m, counting initial value a are carried out to the first computing module and the second counting module.
Step s3: frequency dividing ratio is obtain pre-fractional frequency signal after the input signal of P/ (P+1) the pre-divider voltage controlled oscillator in future of P/ (P+1) carries out pre-frequency division, and this pre-fractional frequency signal is sent to the first counter and the second counter respectively, count to make the first counter and the second counter;
In above-mentioned steps s3, in P/ (P+1) pre-divider, namely P+1 frequency division is that P+1 input cycle is become 1 output cycle, and P frequency division becomes P input cycle into 1 output cycle exactly.Such as P=8, then this P/ (P+1) pre-divider can make the frequency divider that 9 frequency divisions also can do 8 frequency divisions.Input signal from voltage-controlled vibrator needs to carry out scaling down processing, P/ (P+1) pre-divider first carries out pre-scaling down processing to input signal, now such as carry out P frequency division, P=8, the frequency dividing ratio N=120 that finally will carry out, so then complete 8 frequency divisions at P/ (P+1) pre-divider, other frequency divisions are processed by follow-up two counters.
Count corresponding to the first counter in step s3, it specifically can be divided into following sub-step to carry out:
Step 31a: the first counter i with the formula
1=m-1 starts counting, wherein, and i
1it is the count value of the first counter;
Step 32a: judge this count value i
1whether be greater than 1, if so, then return step 31a, otherwise the first rolling counters forward stops;
Count corresponding to the second counter in step s3, it specifically can be divided into following sub-step to carry out:
Step 31b: the second counter i with the formula
2=a-1 starts counting, wherein, and i
2it is the count value of the second counter;
Step 32b: judge this count value i
2whether be greater than 1, if so, then return step 31b, otherwise the second rolling counters forward stops.
First counter of the present embodiment, the second counter, the first computing module, the second counting module, reset device and P/ (P+1) pre-divider are all belong in a frequency divider, and namely this frequency divider comprises these module devices above-mentioned.First counter and the second counter are all carry out subtracting a counting, whenever a rising edge appears in input signal, two counters just carry out a counting action, at the beginning, first counter and the second counter are synchronous countings, first counter does and subtracts a counting from counting initial value m, and the second counter does and subtracts a counting from counting initial value a, due to m>a, so necessarily the second counter makes last count value stop to 1 in advance, do simultaneously from two counters and subtract one and count up to the second rolling counters forward and stop this stage definitions to be the first half section of a dividing cycle of P/ (P+1) pre-divider, at this one-phase, frequency divider does P+1 frequency division, therefore each cycle of two counters in this stage comprises the input cycle of P+1, this input periodicity is (P+1) * a, the situation of second half section is that the second counter counts stopping, but the first counter continues counting until the count value of the second counter is 1, this stage is second half section of a dividing cycle of frequency divider, frequency divider does P frequency division in the meantime, therefore the input periodicity of second half section is P* (m-a).The input periodicity of two periods is added and is (P+1) * a+P* (m-a)=P* (m+a).
The method of counting that certain the present embodiment provides not is unique restriction, can be 0 by the initial value of setting two counters yet, then carry out adding 1 counting, can realize equally.
When step s4: the first rolling counters forward stops, sending first and control signal to reset device, export high level signal to make reset device according to this first control signal; When second rolling counters forward stops, sending second and control signal to reset device, to make reset device according to this second control signal output low level signal, described frequency dividing ratio N=P*m+a.Here the high level signal of reseting module and low level signal combine is exactly the final fractional frequency signal reaching frequency dividing ratio N.After first counting module and the second counting module carry out related operation process to pre-fractional frequency signal respectively, obtain the first control signal and the second control signal, reset device just can process according to these two signals and obtain final fractional frequency signal.
Specifically, due to m>a, the second counter must first stop counting than the first counter, and step s4 specifically comprises following sub-step:
Step 41: the second rolling counters forward stops, the second counter sends second and controls signal to reset device;
Step 42: reset device is according to this second control signal output low level signal;
Step 43: the first rolling counters forward stops, the first counter sends first and controls signal to reset device;
Step 44: reset device exports high level signal according to this first control signal.
When the second rolling counters forward stops, reset device is according to the second control signal output low level signal, when first rolling counters forward stops, reset device exports high level signal, and the low and high level of input signal can be distinguished thus, the frequency of input signal is fvco, the frequency of output signal is fdiv, then fdiv*N=fvco, namely output signal is the output of input signal after Fractional-N frequency, and this output signal includes high level signal and the low level signal of reset device output.Stop to the first rolling counters forward, whole frequency divider completes a complete dividing cycle, performs next step after this.
When step s5: the first counter and the second counter all count stopping, reset device control P/ (P+1) pre-divider resets, and P/ (P+1) pre-divider receives the new input signal of voltage controlled oscillator again.Start the frequency division work of new one-period thus.
The mapping mode mapping out initial value m and a by frequency dividing ratio Ν in the present embodiment can realize wider continuous frequency dividing ratio scope, specifically described below:
Due to N=P*m+a, and m=floor (N-K)/P, a=N-P*m, the above-mentioned K of mentioning is parameter, can select, further illustrate below by citing according to the scope of frequency dividing ratio N, suppose P=8, K=4, N=100, so can obtain m=12 by formula m=floor (N-K)/P, a=4 can be obtained by formula a=N-P*m, with formula N=P*m+a, the above results is verified, 8*12+4=100, illustrate that this frequency division mode is correctly feasible.Be described (in following table K=4, P=8) below by a form citing:
| N | m | a |
| 100 | 12 | 4 |
| 101 | 12 | 5 |
| 102 | 12 | 6 |
| 103 | 12 | 7 |
| 104 | 12 | 8 |
| 105 | 12 | 9 |
| 106 | 12 | 10 |
| 107 | 12 | 11 |
| 108 | 13 | 4 |
| 109 | 13 | 5 |
| 110 | 13 | 6 |
| 111 | 13 | 7 |
Can be found by upper table, the value of a is from K to m-1, and such as during m=12, a increases progressively with N's and increases progressively, and as m=13, same a increases progressively with N's and increases progressively.And work as K=4, P=8, during N=99, by formula m=floor (N-K)/P, known m=11, according to formula a=N-P*m, known a=11, does not now meet limitation type m>a >=1, and therefore the computational methods that provide of the present embodiment can the value of the K lower limit that limits continuous frequency dividing ratio be 100, namely as K=4, N >=100.
Another kind of situation, works as K=3, P=8, during N=99, m=1 can be obtained, 2, a=3, does not now violate the restriction of limitation type m>a >=1, illustrates in this case, 99 frequency divisions can be done, calculate in conjunction with formula, can learn at K=3, when P=8, the minimum value of frequency dividing ratio is 91, illustrates when K reduces, and has expanded the scope of continuous frequency dividing ratio.
Therefore in a practical situation, when the frequency dividing ratio N preset is less, K can get less value to obtain less frequency dividing ratio lower limit, and K is less, and possible minimum duty cycle is also less.
Continue the lower limit of derivation frequency dividing ratio below, if Ν=P*x+K-1, x is positive integer, represent the value of m, m can not be arbitrarily small, by formula m=floor (N-K)/P, can m=x-1 be obtained, by formula a=N-P*m, a=N-(x-1) * P=P+K-1 can be obtained, due to m>a, then x>P+K, therefore N>P* (P+K)+K-1, N >=P* (P+K)+K, as K=1, it is P* (P+1)+1. that frequency dividing ratio N can obtain minimum value
The frequency dividing ratio scope of this mapping mode support of the present embodiment does not have the upper limit, but when frequency dividing ratio is very large, duty ratio can be less, minimum duty cycle is there is, by formula m=floor (N-K)/P, m=x as N=x*P+K, by formula a=N-P*m, then a=N-x*P=K, duty ratio
visible, frequency dividing ratio N is larger, and duty ratio minimum value is less, and the derivative of duty ratio to K is greater than 0, so K is less, duty ratio minimum value is also less.
On the other hand, corresponding to a kind of dividing method of the present embodiment, a kind of frequency divider is also provided, the all functions of this dividing method can be realized, see Fig. 4, it comprises the first computing module, second computing module, first counter, second counter, P/ (P+1) pre-divider and reset device, first computing module and the second computing module are all connected with the first outside register, for obtaining the frequency dividing ratio N defaulted in the first register, P/ (P+1) pre-divider is connected with outside voltage controlled oscillator, for receiving the input signal of voltage controlled oscillator.First computing module, the second computing module, P/ (P+1) pre-divider and reset device are all connected with the first counter, first computing module is also all connected with the second computing module with the second counter, and the second counter is also all connected with reset device with P/ (P+1) pre-divider.The all functions of these module devices are all as described in a kind of dividing method, concrete, the first computing module, for producing counting initial value m according to the frequency dividing ratio N defaulted in the first outside register; Described second computing module, produces initial value a for the initial value m produced according to the frequency dividing ratio N defaulted in the first register and the first computing module; Described reset device, obtain counting initial value m, and control the second counter obtains counting initial value a from the second computing module for controlling the first counter from the first computing module; Described P/ (P+1) pre-divider, for future voltage controlled oscillator input signal carry out pre-frequency division after obtain pre-fractional frequency signal, and this pre-fractional frequency signal is sent to the first counter and the second counter respectively; Described first counter, for starting to count to count initial value m according to pre-fractional frequency signal, and when counting stopping, sending first and controlling signal to reset device, export high level signal to make reset device according to this first control signal; Described second counter, for starting to count to count initial value a according to pre-fractional frequency signal, and when counting stopping, sending second and controlling signal to reset device, to make reset device according to this second control signal output low level signal.Wherein, the present embodiment adopts the mode subtracting a counting equally, and preferably counting initial value m> counts initial value a >=1.When the first counter and the second counter all count stopping, described reset device also carries out for control P/ (P+1) pre-divider the pre-frequency division that frequency dividing ratio is P, when second rolling counters forward stops, reset device control P/ (P+1) pre-divider carries out the pre-frequency division that frequency dividing ratio is (P+1).Due to m>a >=1, therefore the second counter must stop counting in advance than the first counter, and therefore in fact, reset device is that control P/ (P+1) pre-divider frequency dividing ratio is the pre-frequency division of P when the first rolling counters forward stops.
Further, first computing module comprises first adder, divider and the second register, the output of described first register is all connected with the input of first adder with the output of the second register, the output of described adder is connected with the input of divider, and described second computing module is all connected with the output of divider with the first counter.Second computing module comprises multiplier and second adder, and the input of described multiplier is connected with the output of divider, and the output of described multiplier connects the input of second adder, and the output of second adder connects the second counter.
To one skilled in the art, according to technical scheme described above and design, other various corresponding change and deformation can be made, and all these change and deformation all should belong within the protection range of the claims in the present invention.
Claims (9)
1. a dividing method, is characterized in that, comprises the steps:
Step one: the first computing module produces counting initial value m according to the frequency dividing ratio N defaulted in the first register, the second computing module produces counting initial value a according to the frequency dividing ratio N defaulted in the first register and initial value m;
Step 2: reset device controls the first counter and obtain counting initial value m from the first computing module, and control the second counter obtains counting initial value a from the second computing module, and m>a >=1;
Step 3: frequency dividing ratio is obtain pre-fractional frequency signal after the input signal of P/ (P+1) the pre-divider voltage controlled oscillator in future of P/ (P+1) carries out pre-frequency division, and this pre-fractional frequency signal is sent to the first counter and the second counter respectively, count to make the first counter and the second counter;
Step 4: when the first rolling counters forward stops, sending first and controls signal to reset device, exports high level signal to make reset device according to this first control signal; When second rolling counters forward stops, sending second and control signal to reset device, to make reset device according to this second control signal output low level signal, described frequency dividing ratio N=P*m+a.
2. dividing method as claimed in claim 1, is characterized in that, also comprise the steps: after described step 4
Step 5: when described first rolling counters forward stops, reset device control P/ (P+1) pre-divider carries out the pre-frequency division that frequency dividing ratio is P, when second rolling counters forward stops, reset device control P/ (P+1) pre-divider carries out the pre-frequency division that frequency dividing ratio is (P+1).
3. dividing method as claimed in claim 1, it is characterized in that, the step that in described step 3, the first counter carries out counting comprises:
Step 31a: the first counter i with the formula
1=m-1 starts counting, wherein, and i
1it is the count value of the first counter;
Step 32a: judge this count value i
1whether be greater than 1, if so, then return step 31a, otherwise the first rolling counters forward stops;
The step that in described step 3, the second counter carries out counting comprises:
Step 31b: the second counter i with the formula
2=a-1 starts counting, wherein, and i
2it is the count value of the second counter;
Step 32b: judge this count value i
2whether be greater than 1, if so, then return step 31b, otherwise the second rolling counters forward stops.
4. dividing method as claimed in claim 1, it is characterized in that, described step 4 specifically comprises following sub-step:
Step 41: the second rolling counters forward stops, the second counter sends second and controls signal to reset device;
Step 42: reset device is according to this second control signal output low level signal;
Step 43: the first rolling counters forward stops, the first counter sends first and controls signal to reset device;
Step 44: reset device exports high level signal according to this first control signal.
5. a frequency divider, it is characterized in that, comprise the first computing module, the second computing module, the first counter, the second counter, reset device and P/ (P+1) pre-divider, described first computing module, for producing counting initial value m according to the frequency dividing ratio N defaulted in the first outside register; Described second computing module, produces initial value a for the initial value m produced according to the frequency dividing ratio N defaulted in the first register and the first computing module; Described reset device, obtain counting initial value m, and control the second counter obtains counting initial value a from the second computing module for controlling the first counter from the first computing module; Described P/ (P+1) pre-divider, for future voltage controlled oscillator input signal carry out pre-frequency division after obtain pre-fractional frequency signal, and this pre-fractional frequency signal is sent to the first counter and the second counter respectively; Described first counter, for starting to count to count initial value m according to pre-fractional frequency signal, and when counting stopping, sending first and controlling signal to reset device, export high level signal to make reset device according to this first control signal; Described second counter, for starting to count to count initial value a according to pre-fractional frequency signal, and when counting stopping, sending second and controlling signal to reset device, to make reset device according to this second control signal output low level signal.
6. frequency divider as claimed in claim 5, is characterized in that, described counting initial value m> counts initial value a >=1.
7. frequency divider as claimed in claim 5, it is characterized in that, when described first rolling counters forward stops, reset device control P/ (P+1) pre-divider carries out the pre-frequency division that frequency dividing ratio is P, when second rolling counters forward stops, reset device control P/ (P+1) pre-divider carries out the pre-frequency division that frequency dividing ratio is (P+1).
8. frequency divider as claimed in claim 5, it is characterized in that, described first computing module comprises first adder, divider and the second register, the output of described first register is all connected with the input of first adder with the output of the second register, the output of described adder is connected with the input of divider, and described second computing module is all connected with the output of divider with the first counter.
9. frequency divider as claimed in claim 8, it is characterized in that, described second computing module comprises multiplier and second adder, the input of described multiplier is connected with the output of divider, the output of described multiplier connects the input of second adder, and the output of second adder connects the second counter.
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| CN108880540A (en) * | 2018-06-08 | 2018-11-23 | 中国电子科技集团公司第四十研究所 | A method of improving phase-locked loop frequency switching time |
| CN110868212A (en) * | 2019-12-02 | 2020-03-06 | 深圳清华大学研究院 | High-speed counting and comparing circuit and method thereof |
| US11909407B2 (en) | 2022-06-17 | 2024-02-20 | Samsung Electronics Co., Ltd. | Method and system of dynamically controlling reset signal of IQ divider |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108880540A (en) * | 2018-06-08 | 2018-11-23 | 中国电子科技集团公司第四十研究所 | A method of improving phase-locked loop frequency switching time |
| CN110868212A (en) * | 2019-12-02 | 2020-03-06 | 深圳清华大学研究院 | High-speed counting and comparing circuit and method thereof |
| CN110868212B (en) * | 2019-12-02 | 2023-03-24 | 深圳清华大学研究院 | High-speed counting and comparing circuit and method thereof |
| US11909407B2 (en) | 2022-06-17 | 2024-02-20 | Samsung Electronics Co., Ltd. | Method and system of dynamically controlling reset signal of IQ divider |
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| Publication number | Publication date |
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| CN104993826B (en) | 2018-05-15 |
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