JPH10341156A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a PLL circuit where a pull-in time is reduced and power consumption is decreased by directly changing an operating frequency depending on the operating state of a system. SOLUTION: A control circuit 60 generates control signals SB, SC, SM used to set a frequency division ratio for frequency dividers 50, 40 and an initial count of a counter 20. Then an oscillated frequency of a frequency multiplier 30 is set to a frequency closer to a desired operating frequency f1 accordingly. In the case of changing the operating frequency, a count and a frequency division ratio after revision are calculated based on a control signal SA to instruct the change and on a current count SN latched in a register 70, and the control signals SB, SC, SM are newly set and the frequency division ratio of the frequency dividers 50, 40 and the count of the counter 20 are set to new values, then the pull-in time required for changing the operating frequency is reduced, the useless power consumption during the pull-in operation is suppressed and the operation stability of the system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL circuit, and more particularly to a PLL circuit that generates a clock signal having a predetermined frequency in response to an external reference signal.

[0002]

2. Description of the Related Art When an oscillation signal having a predetermined frequency is generated in response to an external reference signal, a PLL circuit is generally used. FIG. 3 shows a configuration example of the PLL circuit. As shown, the PLL circuit 100 includes a phase comparator 10, a counter 20, a frequency multiplier 30, and a frequency divider 40. The phase comparator 10 compares the phases of the reference clock RFCK of the frequency f _{0 and} the frequency-divided signal S40 from the frequency divider 40, and outputs up / down signals S _up and S _dw to the counter 20 according to the comparison result. . For example, when the frequency of the frequency-divided signal S40 from the frequency divider 40 is lower than the frequency of the reference clock RFCK, an up signal S _up is generated and output to the counter 20.
When the frequency of the frequency-divided signal S40 from the frequency divider 40 is higher than CK, a down signal _Sdw is generated and the counter 20
Output to

The counter 20 sets the count value S20 of n (n = 1, 2, 3,...) Bits in accordance with the up / down signal from the phase comparator 10, and sets the count value S20.
Is output to the frequency multiplier 30. The frequency multiplier 30 has a function similar to that of a voltage controlled oscillator (VCO), and controls the frequency of an oscillation signal to be output according to an input control signal. Here, the frequency multiplier 30 controls the frequency of the oscillation signal S30 according to the input count value S20. The frequency divider 40 has a preset frequency division ratio m (m = 1, 2, 3,
..), The oscillation signal S30 from the frequency multiplier 30 is frequency-divided, and the frequency-divided signal S40 is output to the phase comparator 10.

In the PLL circuit thus configured, the phase comparator 10 obtains a comparison result indicating that the phase of the frequency-divided signal S40 matches the phase of the reference clock RFCK.
When the LL circuit has reached a steady state, the frequency f ₁ of the output signal S30 of the frequency multiplier 30 is determined by the frequency f ₀ of the frequency dividing ratio m and the reference clock RFCK frequency divider 40, f
₁ = mf ₀ become.

[0005] An output signal S30 of the frequency multiplier 30 is supplied to the outside as a target clock signal PLCK. By setting the frequency division ratio m of the frequency divider 30, a clock signal PLCK having a desired frequency can be obtained.

[0006]

When an oscillation signal, for example, a target clock signal PLCK shown in FIG. 3 is generated by the above-described conventional PLL circuit, the operation of the system according to the occasional operating condition is performed by the system. The frequency of the clock signal may be converted. In the conventional case, the output clock signal is directly changed by directly changing the output frequency of the PLL circuit or by configuring a system as shown in FIG. 4 and providing a variable frequency divider on the output side of the PLL circuit. Change the frequency of

However, when the oscillation frequency of the PLL circuit is directly changed, the time required for changing the operating frequency to the desired frequency, that is, the so-called pull-in time, becomes longer, and the PLL circuit locks to the desired operating frequency. It takes a long time to be completed.

For example, as shown in FIG. 5, when the operating frequency of the system is changed from f to f / 2, which is half of that, the oscillation frequency of the PLL circuit is stabilized at f / 2 (D ₁ + D ₂ ) is required, during which the operating frequency of the system becomes unstable and the operating state of the system becomes unstable. For this reason, there is a disadvantage that changing the operating frequency while the system is operating involves risks.

When the oscillation signal S100 of the PLL circuit is frequency-divided by a frequency divider 120 having a variable frequency division ratio to generate a clock signal S120 having a predetermined frequency, as shown in FIG. The frequency of the output clock signal S120 can be changed only by changing the frequency division ratio N of the frequency divider 120 by the control signal S _C without changing the oscillation frequency of the output clock signal S120. However, in a system that operates with a high-frequency clock signal, for example, a 100-MHz clock signal, the current consumption of the frequency divider 120 increases significantly, which hinders realization of low power. At this time, the output frequency of the PLL circuit does not change, and the current consumption in the PLL does not change.

[0010] The present invention has been made in view of such circumstances, and its object is to provide a P based on the operating state of the system.
It is an object of the present invention to provide a PLL circuit that can directly reduce the operating frequency of an LL circuit, thereby shortening the pull-in time associated with the frequency change and reducing power consumption.

[0011]

In order to achieve the above object, a PLL circuit of the present invention divides a reference signal by a first frequency division ratio and outputs a first frequency-divided signal. Circuit,
A phase comparison circuit that compares the phases of the first frequency-divided signal and the second frequency-divided signal and outputs a phase difference signal corresponding to the comparison result; A counter that outputs a count value and that can externally set the count value; an oscillation circuit that oscillates at a predetermined frequency in accordance with the count value from the counter and outputs an oscillation signal; A second frequency divider for dividing the signal by a second frequency division ratio and outputting the obtained frequency-divided signal as the second frequency-divided signal to the phase comparator; A control circuit for setting the first and second frequency division ratios and the count value of the counter according to the frequency and the count value of the counter.

In the present invention, preferably, the control circuit is constituted by a multiplication / division circuit, and the first and second control circuits are provided in accordance with a desired oscillation frequency of the oscillation circuit and a frequency of the reference signal.
When the second frequency division ratio and the count value of the counter are calculated and the oscillation frequency of the oscillation circuit is changed, the first and second frequencies are changed according to the count value before the change and the desired oscillation frequency after the change. The frequency division ratio and the above count value

Further, the present invention preferably has a data holding means for holding the count value of the counter and supplying the held value to the control circuit.

According to the present invention, the first frequency-divided signal obtained by frequency-dividing the reference signal and the second frequency-divided signal obtained by frequency-dividing the oscillating signal of the oscillation circuit are combined by the phase comparator. Are compared,
A phase difference signal corresponding to the comparison result is generated. The count value of the counter is set according to the phase difference signal, and the oscillation circuit oscillates at a predetermined oscillation frequency in accordance with the count value, and an oscillation signal is generated. Further, the frequency division ratios of the first and second frequency division circuits and the count value of the counter are set by the control circuit based on the reference signal and the desired oscillation frequency. When changing the oscillation frequency, the control circuit changes and sets the first and second frequency division ratios and the count value of the counter according to the count value before the change and the desired oscillation frequency after the change.

By setting the frequency dividing ratio of the frequency dividing circuit and the count value of the counter according to the operating state of the system, the oscillation frequency can be directly changed, and the pull-in time required for the frequency change can be reduced. The power consumption can be shortened, and unnecessary power consumption can be reduced.

[0016]

FIG. 1 is a circuit diagram showing an embodiment of a PLL circuit according to the present invention. As shown in FIG. 1, the PLL circuit according to the present embodiment includes a phase comparator 10, a counter 2
0, a frequency multiplier 30, a frequency divider 40, a frequency divider 50, a control circuit 60, and a register 70.

The frequency divider 50, a reference clock RFCK input from the outside by dividing, as a result, and outputs a divided signal S50 having a frequency f _b. Incidentally, the frequency division ratio B (B = 1,2,3, ...) of the frequency divider 50 is controlled in response to the control signal S _B from the control circuit 60. Reference clock RFCK
Is f ₀ , the frequency f _b of the frequency-divided signal S50
Is determined by the following equation.

[0018]

[Number 1] _{f b = f 0 / B ...} (1)

The phase comparator 10 is divided signal S of frequency f _b
Comparing the phases of the frequency division signal S40 from the 50 frequency divider 40, and outputs an up / down signal S _{Stay up-/} S _dw in the counter 20 according to the comparison result. For example, when the frequency of the frequency-divided signal S40 is lower than the frequency-divided signal S50, the up signal S
_up is generated and output to the counter 20, and conversely, the frequency-divided signal S5
When the frequency of the frequency-divided signal S40 is higher than 0, a down signal _Sdw is generated and output to the counter 20.

The counter 20 responds to the up / down signals S _up / S _dw from the phase comparator 10 by n (n = 1, 2, 2).
3,...) Bits, and outputs the count value S20 to the frequency multiplier 30. Note that, in the counter 20 of this embodiment, in addition to the ability to set the count value S20 in accordance with the up / down signal S _{Stay up-/} S _dw from the phase comparator 10, according to a control signal S _M from the control circuit 60 It is also possible to set the count value and output the set value as the count value S20 to the frequency multiplier 30 and the register 70.

[0021] For example, when the operation start of the PLL circuit, set the initial value M of the counter in response to the control signal S _M from the control circuit 60, and outputs the initial value M as the count value S20 to the frequency multiplier 30 , And controls its oscillation frequency f ₁ . Further, when changing the operating frequency of the system during normal operation, the control signal S _M based on the new operating frequency from the control circuit is outputted, the counter 20 accordingly
Updates the count value and outputs a new count value S20. In the subsequent operations, for example, after the PLL circuit has reached the locked state, the count-up or count-down is performed in accordance with the up / down signals S _up / S _dw from the phase comparator 10, and the count value S20 is updated.

The frequency multiplier 30 has a function similar to that of the voltage controlled oscillator, oscillates at a predetermined oscillation frequency according to the input control signal, and outputs an oscillation signal S30. Here, to control the frequency f ₁ of the oscillation signal S30 in accordance with the count value S20 in the frequency multiplier 30 is a counter 20. Note that the oscillation signal S30 is supplied to an external circuit as a target clock signal PLCK.

The frequency divider 40 has a frequency division ratio C (C = 1, 2, 3,...) Set by a control signal S _C from the control circuit 60.
In the oscillation signal S30 from the frequency multiplier 30 frequency-divides and outputs the frequency dividing signal S40 having a frequency f _c to a phase comparator 10. Here, when the oscillation frequency of the frequency multiplier 30 and f _1, the frequency f _c of the frequency dividing signal S40 is obtained by the following equation.

[0024]

F _c = f ₁ / C (2)

The register 70 holds the n-bit count value S20 from the counter 20 and supplies the held count value S _N to the control circuit 60.

The control circuit 60 generates control signals S _B , S _C , and S _M according to the control signal S _A from the external circuit and the count value _SN held in the register 70, and respectively generates the frequency divider 50, It is supplied to the frequency divider 40 and the counter 20.
The control circuit 60 includes, for example, a multiplier / divider. The frequency f ₁ of the target clock signal PLCK set by the input control signal S _A and the reference clock RF
According to the frequency f _{0 of} CK and the count value S _N held in the register 70, the frequency divider 5
0, and calculates the frequency divider 40 frequency dividing ratio control signal S _B for setting the, S _C and for setting an initial count value M of the counter 20 the control signal S _M, respectively.

FIG. 2 is a frequency / time relationship diagram showing a change in frequency when the oscillation frequency is changed in the PLL circuit of the present embodiment. Hereinafter, the operation of the PLL circuit according to the present embodiment will be described in detail with reference to FIGS.

First, at the start of operation, the control circuit 60
Control signals S _B , S _C , and S _M are output, and the frequency division ratios of the frequency divider 50 and the frequency divider 40 are set to B and C, respectively, according to these control signals. M
Is set to When the PLL circuit reaches the locked state, the phase and frequency of the frequency-divided signal S40 from the frequency divider 40 and the frequency-divided signal S50 from the frequency divider 50 are controlled so as to match. At this time, assuming that the frequency of the reference clock RFCK is f ₀ , the oscillation frequency f ₁ of the frequency multiplier 30 is obtained by the following equation.

[0029]

F ₁ = f ₀ (C / B) (3)

At this time, the control circuit 60 controls the oscillation frequency f ₁ of the frequency multiplier 30 according to the count value M from the counter 20 so that the oscillation frequency f ₁ becomes a desired frequency of the target clock signal PLCK or a value close thereto. , The PLL circuit reaches the desired frequency of the target clock signal PLCK in a relatively short time from the rise, enters a lock state, and follows the reference clock RFCK in a stable state. To generate a clock signal PLCK and supply it to the outside.

Next, when the frequency of the target clock signal PLCK is changed, for example, when the target frequency f ₁ is changed to half of the initial value, a command to change the frequency is issued by the control signal S _A from the outside to the control circuit 60. Is transmitted to In response to this, the control circuit 60 calculates new control signals S _B , S _C , and S _M according to the new frequency of the target clock signal PLCK, and according to these control signals, the frequency divider 50 and the frequency divider 40. And the count value of the counter 20 are updated.

For example, when the frequency of the target clock signal is changed to half of the current value, the control circuit 60 uses the current count value S _N held by the register 70 to divide the frequency by half the division process. It calculates a value (S _N / 2), generates a control signal S _M for setting the count value of the counter 20 according to the calculated value, and outputs it to the counter 20.

In the counter 20, the count value S20 is updated in accordance with the control signal S _M , that is, half the current count value is set as a new count value S20. According to the new count value S20, the oscillation frequency of the frequency multiplier 30 is set to half of the oscillation frequency before the change.

When the count value of the counter 20 is updated,
The control circuit 60 updates the control signals S _B and S _C for setting the frequency division ratio of the frequency divider 50 and the frequency divider 40 according to the new operating frequency. Assuming that the new frequency division ratios of the frequency divider 50 and the frequency divider 40 are b and c, respectively, according to the equation (3), the new frequency division ratio is set so that (c / b) = (C / 2B). Control signals S _B and S _C for setting may be generated.

As described above, when the frequency of the target clock signal of the PLL circuit is changed, the count value of the counter 20 and the division ratio of the frequency divider 50 and the frequency divider 40 are set according to the new operating frequency. Control signals S _M , S _B ,
Generates S _C, by updating the count value and the division ratio in accordance with these control signals, the oscillation frequency of the setting change after the frequency multiplier 30 is set to the new target operating frequency or a frequency close thereto, PLL The circuit stabilizes to the new target operating frequency in a relatively short time, the transient time D required for updating the operating frequency is shortened, and the operating stability of the system is improved. Also, the operating frequency of the entire PLL circuit is 1
/ 2, and the power consumption is also reduced.

Furthermore, as shown in FIG. 2, when changing the operating frequency f ₁ of the system 3/4 of the initial value, the instruction of the frequency change by a control signal S _A from the outside is transmitted to the control circuit 60 You. In response, the control circuit 60 calculates new control signals S _B , S _C , and S _M according to the new frequency of the target clock signal, and according to these control signals, the frequency divider 50, the frequency divider 40, The count value of the counter 20 is updated.

Since the operating frequency of the PLL circuit before the change is set to の of the initial value, changing the setting of the frequency of the target clock signal to ／ of the initial value is equivalent to the PLL circuit after the change. Oscillation frequency increases 1.5 times before the change. For this reason, the control circuit 60 uses the value of the count value S _N held in the register 70, performs a multiplication operation on the value, and sets the count value so that the oscillation frequency becomes 3/2. The signal S _M is generated and output to the counter 20.

[0038] In the counter 20, the current value a count value S20 in accordance with the control signal S _M from the control circuit 60 3
/ 2 and output to the frequency multiplier 30. In response to this, the frequency multiplier 30 sets the oscillation frequency to 3/2 of the current value.

When the count value of the counter 20 is updated,
The control circuit 60 updates the control signals S _B and S _C for setting the frequency division ratio of the frequency divider 50 and the frequency divider 40 according to the new operating frequency. Assuming that the new frequency division ratios of the frequency divider 50 and the frequency divider 40 are b ′ and c ′, respectively, according to the equation (3), the new frequency division ratio becomes (c ′ / b ′) = (3c / 2b). Control signals S _B and S _C for setting the frequency division ratio
Should be generated.

For example, the frequency division ratio of the frequency divider 50 is set to twice that before the change by the control signals S _B and S _C , and the frequency division ratio of the frequency divider 40 is set to three times that before the change. Control signals S _B , S
The value of _C is set, and the value of the control signal S _M is set so that the count value of the counter 20 becomes 3/2 before the change. The frequency divider 50 and the frequency divider By changing the frequency division ratio of 40 and the count value of the count value 20, the oscillation frequency of the frequency multiplier 30 after the change is set to 3/2 before the change or a frequency close thereto. Therefore, the PLL circuit can stabilize to the new target operating frequency in a relatively short time, shorten the pull-in time required for updating the operating frequency, improve the operation stability of the system, and suppress unnecessary power consumption. it can.

As described above, according to the present embodiment, the reference clock RFCK and the target clock signal PL
The control circuit 60 generates control signals S _B , S _C , and S _M for setting the frequency division ratio of the frequency dividers 50 and 40 and the initial count value of the counter 20 according to the desired frequency of CK. The oscillation frequency of the frequency multiplier 30 is set to a frequency close to the desired target frequency f ₁ in accordance with the control signal S _A, and when the operating frequency is changed, the control signal S _A instructing the change and the current value held in the register 70 are set. The changed count value and frequency division ratio are calculated according to the count value _SN , and the control signals S _B , S _C , and S _M are set again, and the counter 20 and the frequency divider of the frequency dividers 50 and 40 are updated. Since the value is set to a value, the pull-in time required for changing the operating frequency can be shortened, unnecessary power consumption can be suppressed during the pull-in operation, and the operation stability of the system can be improved.

[0042]

As described above, according to the PLL circuit of the present invention, a control circuit including a multiplier / divider is provided, and the values of the counter and the frequency divider are changed according to the operation state of the system. The operating frequency of the PLL circuit can be directly changed, and the pull-in time required for the frequency change can be shortened.
There is an advantage that the power consumption can be reduced and the operation stability of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a PLL circuit according to the present invention.

FIG. 2 shows the frequency / frequency of the PLL circuit of the present invention when the frequency changes.
It is a figure which shows the relationship of time.

FIG. 3 is a circuit diagram illustrating a configuration example of a conventional PLL circuit.

FIG. 4 is a block diagram showing a configuration of a conventional system including a PLL circuit and a frequency division ratio variable frequency divider.

FIG. 5 is a diagram showing a frequency / time relationship when a frequency changes in a conventional PLL circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Phase comparator, 20 ... Counter, 30 ... Frequency multiplier, 40, 50, 120 ... Divider, 60 ... Control circuit, 7
0: register, 100: PLL circuit, RFCK: reference clock signal, PLCK: target clock signal.

Claims (5)

[Claims] A first dividing circuit for dividing a reference signal by a first dividing ratio and outputting a first divided signal; a first divided signal and a second divided signal; And a phase comparison circuit that compares the phases with each other and outputs a phase difference signal according to the comparison result. The phase comparison circuit counts according to the phase difference signal, outputs a predetermined count value, and sets the count value from outside. A possible counter, an oscillation circuit that oscillates at a predetermined frequency according to the count value from the counter and outputs an oscillation signal, and divides the oscillation signal from the oscillation circuit by a second division ratio.
A second frequency divider that outputs the obtained frequency-divided signal to the phase comparator as the second frequency-divided signal; and a second frequency divider that outputs the second frequency-divided signal according to a desired oscillation frequency of the oscillation circuit and a count value of the counter. A control circuit for setting a first division ratio and a count value of the counter.
L circuit. 2. The control circuit comprises a multiplication / division circuit, and the first and second frequency division ratios and the count value of the counter according to a desired oscillation frequency of the oscillation circuit and the frequency of the reference signal. 2. The PLL circuit according to claim 1, wherein 3. The control circuit, when changing the oscillation frequency of the oscillation circuit, controls the first and second frequency division ratios and the count value in accordance with a count value before the change and a desired oscillation frequency after the change. 2. The PLL according to claim 1, wherein the value is changed.
circuit. 4. The PLL circuit according to claim 1, further comprising data holding means for holding a count value of said counter and supplying the held value to said control circuit. 5. The PLL circuit according to claim 4, wherein said data holding means comprises a register.