CN104993826B - A kind of dividing method and its device - Google Patents
A kind of dividing method and its device Download PDFInfo
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- CN104993826B CN104993826B CN201510439323.5A CN201510439323A CN104993826B CN 104993826 B CN104993826 B CN 104993826B CN 201510439323 A CN201510439323 A CN 201510439323A CN 104993826 B CN104993826 B CN 104993826B
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Abstract
The present invention relates to a kind of dividing method and its device, this method includes：First computing module and the second computing module produce respectively according to the frequency dividing ratio N defaulted in the first register counts initial value m and counting initial value a；Reset device controls the first counter and the second counter counts initial value m and counts initial value a, P/ (P+1) pre-divider sends pre- fractional frequency signal to the first counter and the second counter respectively, so that the first counter and the second counter are counted；When first counter counts stopping, first control signal is sent to reset device, so that reset device exports high level signal according to the first control signal；When second counter counts stopping, second control signal is sent to reset device, so that reset device exports low level signal according to the second control signal.Realize that, from frequency dividing ratio N to the mapping for counting initial value m and a, the mode compared to mapping table can save significantly on area using two computing modules.
Description
Technical field
The present invention relates to frequency splitting technology, more particularly to a kind of dividing method and its device.
Background technology
Modern communication technology is maked rapid progress, and various wireless communication standards emerge in an endless stream.In the reception and transmitting of signal, frequency
Rate synthesizer is a kind of important module, is mixed for producing stable, the accurate, local oscillation signal of low noise and reception (transmitting) signal
Frequently.To realize wider communications frequency range and relatively narrow channel width, frequency synthesizer need a frequency dividing ratio scope it is wide, can
The decimal frequency divider of programming.Decimal frequency divider by frequency dividing ratio is continuous, based on programmable integer frequency divider.
One common programmable frequency divider is that frequency divider is swallowed in pulse, mainly by P (P+1) pre-divider, one
Count the counter M that modulus value is m and the counter A compositions that a counting modulus value is a.During frequency divider operation, voltage controlled oscillator
(VCO) export an oscillator signal and enter frequency divider, frequency divider first counts this oscillator signal (P+1) * a cycles, then skill meter
Number P* (m-a) a cycle.One frequency divider output cycle just inputs the cycle comprising P*m+a, so frequency dividing ratio N=P*m+a.Often
A frequency dividing ratio N is fed, is required for producing corresponding m and a, if with the method tabled look-up, the frequency dividing ratio scope to be covered is very wide
When can take larger chip area.
The content of the invention
For above-mentioned technical problem, it is an object of the present invention to providing a kind of dividing method, it can realize a kind of complete
New mode completes mappings of the frequency dividing ratio N to count value, reduces the area occupied of chip.
One of to achieve the above object, the present invention adopts the following technical scheme that：
A kind of dividing method, includes the following steps：
Step 1：First computing module is produced according to the frequency dividing ratio N defaulted in the first register counts initial value m, the
Two computing modules produce according to the frequency dividing ratio N and initial value m defaulted in the first register and count initial value a；
Step 2：Reset device controls the first counter to be obtained from the first computing module and counts initial value m, and control
Second counter is obtained from the second computing module counts initial value a, and m>a≥1；
Step 3：Frequency dividing ratio is that the input signal of P/ (P+1) pre-divider voltage controlled oscillator in future of P/ (P+1) carries out
Pre- fractional frequency signal is obtained after pre- frequency dividing, and the pre- fractional frequency signal is respectively sent to the first counter and the second counter, so that
First counter and the second counter are counted；
When the first counter of step 4 counts stopping, first control signal is sent to reset device, so that reset device root
High level signal is exported according to the first control signal；When second counter counts stopping, second control signal is sent to restorer
Part, so that reset device exports low level signal, the frequency dividing ratio N=P*m+a according to the second control signal.
Preferably, following steps are further included after the step 4：
Step 5：When first counter counts stopping, reset device control P/ (P+1) pre-divider carries out frequency dividing ratio
For the pre- frequency dividing of P, when the second counter counts stopping, it is (P+1) that reset device, which controls P/ (P+1) pre-divider to carry out frequency dividing ratio,
Pre- frequency dividing.
Preferably, the step of the first counter is counted in the step 3 includes：
Step 31a：First counter is with formula i1=m-1 is started counting up, wherein, i1For the count value of the first counter；
Step 32a：Judge count value i1Whether 1 is more than, if so, then return to step 31a, otherwise, the first counter counts
Number stops；
The step of the second counter is counted in the step 3 includes：
Step 31b：Second counter is with formula i2=a-1 is started counting up, wherein, i2For the count value of the second counter；
Step 32b：Judge count value i2Whether 1 is more than, if so, then return to step 31b, otherwise, the second counter counts
Number stops.
The step 4 specifically includes following sub-step：
Step 41：Second counter, which counts, to be stopped, and the second counter sends second control signal to reset device；
Step 42：Reset device is according to the second control signal signal output low level signal；
Step 43：First counter, which counts, to be stopped, and the first counter sends first control signal to reset device；
Step 44：Reset device exports high level signal according to the first control signal.
The second object of the present invention is to provide a kind of frequency divider, it can realize a kind of function of dividing method.
To achieve the above object two, the present invention adopts the following technical scheme that：
A kind of frequency divider, including the first computing module, the second computing module, the first counter, the second counter, reset
Device and P/ (P+1) pre-divider, first computing module, for according to point in the first register for defaulting in outside
Frequency ratio N, which is produced, counts initial value m；Second computing module, for according to default in frequency dividing ratio N in the first register and
First computing module produce initial value m and produce initial value a；The reset device, for controlling the first counter from first
Obtained in computing module and count initial value m, and the second counter of control obtains from the second computing module and counts initial value a；
P/ (P+1) pre-divider, the input signal for voltage controlled oscillator in future carry out obtaining pre- fractional frequency signal after dividing in advance,
And the pre- fractional frequency signal is respectively sent to the first counter and the second counter；First counter, for according to pre- point
Frequency signal proceeds by counting to count initial value m, and when counting stopping, transmission first control signal to reset device, with
Reset device is set to export high level signal according to the first control signal；Second counter, for according to pre- fractional frequency signal
Counting is proceeded by count initial value a, and when counting stopping, sending second control signal to reset device, so as to reset
Device exports low level signal according to the second control signal.
Preferably, the counting initial value m>Count initial value a >=1.
Preferably, when first counter counts stopping, reset device control P/ (P+1) pre-divider carries out frequency dividing ratio
For the pre- frequency dividing of P, when the second counter counts stopping, it is (P+1) that reset device, which controls P/ (P+1) pre-divider to carry out frequency dividing ratio,
Pre- frequency dividing.
Preferably, first computing module includes first adder, divider and the second register, first deposit
Input terminal of the output terminal of the output terminal of device and the second register with first adder is connected, the output terminal of the adder with
The input terminal connection of divider, second computing module and the first counter are connected with the output terminal of divider.
It is further preferred that second computing module includes multiplier and second adder, the input of the multiplier
End is connected with the output terminal of divider, the input terminal of the output terminal connection second adder of the multiplier, second adder
Output terminal connects the second counter.
Compared with the prior art, the beneficial effects of the present invention are：
The present invention realizes that frequency dividing ratio N is first to initial value m and counting is counted by the first computing module and the second computing module
The mapping of initial value a, instead of needs tabling look-up gimmick by way of frequency dividing ratio N obtains corresponding m and a, greatly in conventional art
Amount saves the area of frequency divider, there is preferable flexibility and adaptability.
Brief description of the drawings
Fig. 1 is a kind of work flow diagram of dividing method of the embodiment of the present invention；
Fig. 2 is the cut-away view of the first computing module of the embodiment of the present invention；
Fig. 3 is the cut-away view of the second computing module of the embodiment of the present invention；
Fig. 4 is a kind of module frame chart of frequency divider of the embodiment of the present invention.
Embodiment
In the following, with reference to attached drawing and embodiment, the present invention is described further：
Referring to Fig. 1, the present invention provides a kind of dividing method, and it is as follows that it includes step：
Step s1：First computing module is produced according to the frequency dividing ratio N defaulted in the first register counts initial value m, the
Two computing modules produce according to the frequency dividing ratio N and initial value m defaulted in the first register and count initial value a；
In above-mentioned steps s1, frequency dividing ratio N is according to actual conditions be pre-set in the first register, the first meter
Calculating module and the interior of the second computing module respectively has logic circuit, referring to Fig. 2, by the first addition inside the first computing module
Device, the second register and divider are formed, and referring to Fig. 3, are made of inside the second computing module multiplier and second adder, the
Input terminal of the output terminal of the output terminal of one register and the second register with first adder is connected, the output terminal of adder
It is connected with the input terminal of divider, the second computing module and the first counter are connected with the output terminal of divider；Multiplier
The output terminal of input terminal and divider connects, the input terminal of the output terminal connection second adder of multiplier, second adder
Output terminal connects the second counter.First computing module, which produces, counts initial value m=floor (N-K)/P, in addition, N=P*m+a,
Wherein, N is the frequency dividing ratio defaulted in the first register, and K is the parameter introduced, and K is defaulted in the second register, and K can
To be selected according to the scope of frequency dividing ratio N, floor function representation fractions omitteds part, P is that P/ (P+1) is divided in advance in the present embodiment
The frequency dividing ratio of device, below describes P/ (P+1) pre-divider in detail.In this step, as long as one powers on, first calculates
Module and the second computing module will produce corresponding initial value respectively automatically according to frequency dividing ratio N, and other signal controls are not required
System, is all that fixation is set in programming circuitry for parameter K and frequency dividing ratio P, therefore the first computing module and second calculates
Module has been known a priori by the numerical value of parameter K and frequency dividing ratio P, in fact, the first computing module is than the second computing module elder generation work
Make, the first computing module can calculate initial value m according to frequency dividing ratio N, frequency dividing ratio P and parameter K, afterwards the second computing module according to
Frequency dividing ratio P, frequency dividing ratio N and initial value m obtain initial value a, and since the two computing modules are all logical operations, speed is very
It hurry up, the first computing module almost can be ignored than the time that the second computing module first works.
Step s2：Reset device controls the first counter to be obtained from the first computing module and counts initial value m, and control
Second counter is obtained from the second computing module counts initial value a, and m>a≥1；
For step s2, reset device, which is constantly sent, obtains control signal to the first counter and the second counter, the
After one counter and the second counter receive the acquisition control signal, respectively to the first computing module and the second counting module into
Row, which obtains, to be counted initial value m, counts initial value a.
Step s3：Frequency dividing ratio is that the input signal of P/ (P+1) pre-divider voltage controlled oscillator in future of P/ (P+1) carries out
Pre- fractional frequency signal is obtained after pre- frequency dividing, and the pre- fractional frequency signal is respectively sent to the first counter and the second counter, so that
First counter and the second counter are counted；
In above-mentioned steps s3, in P/ (P+1) pre-divider, P+1 frequency dividings are that P+1 input cycle is become 1 output
Cycle, P frequency dividings are exactly that P input cycle is become 1 output cycle.Such as P=8, then P/ (P+1) pre-divider be exactly can
The frequency divider of 8 frequency dividings can also be made so that 9 frequency dividings can be done.Input signal from voltage-controlled vibrator is to need to carry out scaling down processing
, P/ (P+1) pre-dividers first carry out pre- scaling down processing to input signal, such as are to carry out P frequency dividings at this time, and P=8, finally will
The frequency dividing ratio N=120 of progress, then then complete 8 frequency dividings in P/ (P+1) pre-divider, other frequency dividings are by two follow-up countings
Device is handled.
Counted corresponding to the first counter in step s3, it can specifically be divided into following sub-step and carry out：
Step 31a：First counter is with formula i1=m-1 is started counting up, wherein, i1For the count value of the first counter；
Step 32a：Judge count value i1Whether 1 is more than, if so, then return to step 31a, otherwise, the first counter counts
Number stops；
Counted corresponding to the second counter in step s3, it can specifically be divided into following sub-step and carry out：
Step 31b：Second counter is with formula i2=a-1 is started counting up, wherein, i2For the count value of the second counter；
Step 32b：Judge count value i2Whether 1 is more than, if so, then return to step 31b, otherwise, the second counter counts
Number stops.
First counter of the present embodiment, the second counter, the first computing module, the second counting module, reset device with
And P/ (P+1) pre-divider is belonged in a frequency divider, i.e., the frequency divider includes these above-mentioned module devices.First counts
Device and the second counter are to carry out subtracting one counting, as soon as whenever a rising edge occurs in input signal, two counters carry out one
A counting action, at the beginning, the first counter and the second counter are synchronous countings, and the first counter is from counting initial value m
Start to do the counting that subtracts one, and since the second counter do the counting that subtracts one counting initial value a, due to m>A, so necessarily second
Counter causes last count value to stop to 1 in advance, starts simultaneously to do from two counters and subtracts one and count up to the second counter
Count and stop front half section of this stage definitions for a dividing cycle of P/ (P+1) pre-divider, in this stage, frequency divider
It is to do P+1 frequency dividings, therefore each cycle of two counters in this stage includes the input cycle of P+1, the input periodicity
For (P+1) * a, the situation of second half section is that the second counter has counted stopping, but the first counter continues to count until the second meter
The count value of number device is 1, which is the second half section of a dividing cycle of frequency divider, and frequency divider does P frequency dividings in the meantime,
Therefore the input periodicity of second half section is P* (m-a).The input periodicity of twice be added as (P+1) * a+P* (m-a)=
P*(m+a)。
Certain method of counting provided in this embodiment is not uniquely to limit, can also be by setting two countings
The initial value of device is 0, then carries out plus 1 counts, can equally realize.
Step s4：When first counter counts stopping, first control signal is sent to reset device, so that reset device root
High level signal is exported according to the first control signal；When second counter counts stopping, second control signal is sent to restorer
Part, so that reset device exports low level signal, the frequency dividing ratio N=P*m+a according to the second control signal.Here mould is resetted
The high level signal and low level signal of block combine the exactly final fractional frequency signal for reaching frequency dividing ratio N.First count module
After block and the second counting module carry out related computing to pre- fractional frequency signal respectively, first control signal and the second control are obtained
Signal, reset device can handle to obtain final fractional frequency signal according to the two signals.
Specifically, due to m>A, the second counter necessarily first stop counting than the first counter, and step s4 is specifically included
Following sub-step：
Step 41：Second counter, which counts, to be stopped, and the second counter sends second control signal to reset device；
Step 42：Reset device exports low level signal according to the second control signal；
Step 43：First counter, which counts, to be stopped, and the first counter sends first control signal to reset device；
Step 44：Reset device exports high level signal according to the first control signal.
When the second counter, which counts, to be stopped, reset device exports low level signal, the first meter according to second control signal
When rolling counters forward stops, reset device output high level signal, it is possible thereby to which the low and high level of input signal is distinguished, inputs
The frequency of signal is fvco, and the frequency for exporting signal is fdiv, then fdiv*N=fvco, that is, it is that input signal is passed through to export signal
Output after Fractional-N frequency, the output signal include the high level signal and low level signal of reset device output.To the first meter
Rolling counters forward stops, and whole frequency divider completes a complete dividing cycle, performs next step after this.
Step s5：When first counter and the second counter count stopping, reset device control P/ (P+1) pre-divider
Reset, P/ (P+1) pre-divider receives the new input signal for carrying out voltage controlled oscillator again.Thus new a cycle is started
Divide work.
Wider continuous frequency dividing can be realized by mapping out the mapping mode of initial value m and a in the present embodiment by frequency dividing ratio Ν
It is specifically described below than scope：
Due to N=P*m+a, and m=floor (N-K)/P, a=N-P*m, K mentioned above are parameter, can be according to frequency dividing
Scope selection than N, further illustrates, it is assumed that P=8, K=4, N=100, then by formula m=floor below by citing
(N-K)/P can obtain m=12, can obtain a=4 by formula a=N-P*m, the above results are verified with formula N=P*m+a,
8*12+4=100, it is correct feasible to illustrate the frequency dividing mode.(K=in following table is illustrated below by the citing of form
4, P=8)：
| N | m | a |
| 100 | 12 | 4 |
| 101 | 12 | 5 |
| 102 | 12 | 6 |
| 103 | 12 | 7 |
| 104 | 12 | 8 |
| 105 | 12 | 9 |
| 106 | 12 | 10 |
| 107 | 12 | 11 |
| 108 | 13 | 4 |
| 109 | 13 | 5 |
| 110 | 13 | 6 |
| 111 | 13 | 7 |
By upper table it can be found that the value of a is from K to m-1, such as during m=12, a is incremented by with being incremented by for N, works as m=13
When, same a is incremented by with being incremented by for N.And work as K=4, when P=8, N=99, by formula m=floor (N-K)/P, it is known that m=
11, according to formula a=N-P*m, it is known that a=11, at this time and is unsatisfactory for limitation type m>A >=1, therefore calculating provided in this embodiment
Method can the value of K limit the lower limit of continuous frequency dividing ratio as 100, i.e., as K=4, N >=100.
Another situation, works as K=3, when P=8, N=99, can obtain m=1, and 2, a=3, do not violate limitation type m at this time>
The restriction of a >=1, illustrates in this case, can do 99 frequency dividings, be calculated with reference to formula, can learn in K=3,
In the case of P=8, the minimum value of frequency dividing ratio is 91, illustrates, when K reduces, to have expanded the scope of continuous frequency dividing ratio.
Therefore in a practical situation, when default frequency dividing ratio N is smaller, K can take less value to obtain point of smaller
Frequency ratio lower limit, K is smaller, and possible minimum duty cycle is also smaller.
The lower limit for deriving frequency dividing ratio is continued with, if Ν=P*x+K-1, x are positive integer, represents the value of m, m cannot appoint
Anticipate small, by formula m=floor (N-K)/P, m=x-1 can be obtained, by formula a=N-P*m, a=N- (x-1) * P=P+K-1 can be obtained,
Due to m>A, then x>P+K, therefore N>P* (P+K)+K-1, N >=P* (P+K)+K, as K=1, frequency dividing ratio N can obtain minimum value
For P* (P+1)+1.
The frequency dividing ratio scope that this mapping mode of the present embodiment is supported does not have the upper limit, but when frequency dividing ratio is very big, accounts for
It is empty smaller than meeting, there is minimum duty cycle as N=x*P+K, by formula m=floor (N-K)/P, m=x, by formula a=N-
P*m, then a=N-x*P=K, duty cycleAs it can be seen that frequency dividing ratio N is bigger, duty cycle minimum value is got over
Small, duty cycle is more than 0 to the derivative of K, so K is smaller, duty cycle minimum value is also smaller.
On the other hand, corresponding to a kind of dividing method of the present embodiment, a kind of frequency divider is also provided, can realize this point
The all functions of frequency method, referring to Fig. 4, it includes the first computing module, the second computing module, the first counter, the second counting
The first register of device, P/ (P+1) pre-dividers and reset device, the first computing module and the second computing module with outside
Connection, connects for obtaining frequency dividing ratio N, P/ (P+1) pre-divider defaulted in the first register with exterior voltage controlled oscillator
Connect, the input signal of voltage controlled oscillator is carried out for receiving.First computing module, the second computing module, P/ (P+1) pre-divider
And reset device is connected with the first counter, the first computing module and the second counter also connect with the second computing module
Connect, the second counter and P/ (P+1) pre-divider are also connected with reset device.The all functions of these module devices are such as one
Described in kind dividing method, specifically, the first computing module, for according to the frequency dividing ratio N in the first register for defaulting in outside
Produce and count initial value m；Second computing module, for according to the frequency dividing ratio N and first defaulted in the first register
Computing module produce initial value m and produce initial value a；The reset device, for controlling the first counter to be calculated from first
Obtained in module and count initial value m, and the second counter of control obtains from the second computing module and counts initial value a；It is described
P/ (P+1) pre-divider, the input signal for voltage controlled oscillator in future carry out obtaining pre- fractional frequency signal after dividing in advance, and will
The pre- fractional frequency signal is respectively sent to the first counter and the second counter；First counter, for being believed according to pre- frequency dividing
Number proceed by counting to count initial value m, and count stop when, first control signal is sent to reset device, so that multiple
Position device exports high level signal according to the first control signal；Second counter, by according to pre- fractional frequency signal in terms of
Number initial value a proceeds by counting, and when counting stopping, second control signal is sent to reset device, so that reset device
Low level signal is exported according to the second control signal.Wherein, the present embodiment is same by the way of the counting that subtracts one, preferably counts
Initial value m>Count initial value a >=1.When the first counter and the second counter count stopping, the reset device is also used
The pre- frequency dividing that frequency dividing ratio is P, when the second counter counts stopping, reset device control are carried out in controlling P/ (P+1) pre-divider
P/ (P+1) pre-divider processed carries out the pre- frequency dividing that frequency dividing ratio is (P+1).Due to m>A >=1, therefore the second counter is necessarily than
One counter stops counting in advance, therefore in fact, reset device be when the first counter count stop when, control P/ (P+1)
Pre-divider frequency dividing ratio is the pre- frequency dividing of P.
Further, the first computing module includes first adder, divider and the second register, first register
Output terminal and the output terminal of the second register be connected with the input terminal of first adder, the output terminal of the adder is with removing
The input terminal connection of musical instruments used in a Buddhist or Taoist mass, second computing module and the first counter are connected with the output terminal of divider.Second calculates
Module includes multiplier and second adder, and the input terminal of the multiplier and the output terminal of divider connect, the multiplier
Output terminal connection second adder input terminal, the output terminal of second adder connects the second counter.
It will be apparent to those skilled in the art that technical solution that can be as described above and design, make other various
Corresponding change and deformation, and all these changes and deformation should all belong to the protection domain of the claims in the present invention
Within.
Claims (9)
1. a kind of dividing method, it is characterised in that include the following steps：
Step 1：First computing module is produced according to the frequency dividing ratio N defaulted in the first register counts initial value m, the second meter
Calculate module and counting initial value a is produced according to the frequency dividing ratio N and initial value m defaulted in the first register；
Step 2：Reset device controls the first counter to be obtained from the first computing module and counts initial value m, and control second
Counter is obtained from the second computing module counts initial value a, and m>a≥1；
Step 3：Frequency dividing ratio is that the input signal of P/ (P+1) pre-divider voltage controlled oscillator in future of P/ (P+1) is divided in advance
Pre- fractional frequency signal is obtained after frequency, and the pre- fractional frequency signal is respectively sent to the first counter and the second counter, so that first
Counter and the second counter are counted；
Step 4：When first counter counts stopping, first control signal is sent to reset device, so that reset device is according to this
First control signal exports high level signal；When second counter counts stopping, transmission second control signal to reset device, with
Reset device is set to export low level signal, the frequency dividing ratio N=P*m+a according to the second control signal.
2. dividing method as claimed in claim 1, it is characterised in that further include following steps after the step 4：
Step 5：When first counter counts stopping, it is P that reset device, which controls P/ (P+1) pre-divider to carry out frequency dividing ratio,
Pre- frequency dividing, the second counter counts when stopping, and it is (P+1) that reset device, which control P/ (P+1) pre-divider to carry out frequency dividing ratio,
Pre- frequency dividing.
3. dividing method as claimed in claim 1, it is characterised in that the step that the first counter is counted in the step 3
Suddenly include：
Step 31a：First counter is with formula i1=m-1 is started counting up, wherein, i1For the count value of the first counter；
Step 32a：Judge count value i1Whether 1 is more than, if so, then return to step 31a, otherwise, the first counter, which counts, to stop
Only；
The step of the second counter is counted in the step 3 includes：
Step 31b：Second counter is with formula i2=a-1 is started counting up, wherein, i2For the count value of the second counter；
Step 32b：Judge count value i2Whether 1 is more than, if so, then return to step 31b, otherwise, the second counter, which counts, to stop
Only.
4. dividing method as claimed in claim 1, it is characterised in that the step 4 specifically includes following sub-step：
Step 41：Second counter, which counts, to be stopped, and the second counter sends second control signal to reset device；
Step 42：Reset device exports low level signal according to the second control signal；
Step 43：First counter, which counts, to be stopped, and the first counter sends first control signal to reset device；
Step 44：Reset device exports high level signal according to the first control signal.
5. a kind of frequency divider, it is characterised in that including the first computing module, the second computing module, the first counter, the second meter
Number device, reset device and P/ (P+1) pre-divider, first computing module, for being posted according to default in outside first
Frequency dividing ratio N in storage, which is produced, counts initial value m；Second computing module, defaults in the first register for basis
Initial value m that frequency dividing ratio N and the first computing module produce and produce initial value a；The reset device, by controlling based on first
Number device is obtained from the first computing module counts initial value m, and the second counter of control obtains meter from the second computing module
Number initial value a；P/ (P+1) pre-divider, the input signal for voltage controlled oscillator in future obtained after dividing in advance
Pre- fractional frequency signal, and the pre- fractional frequency signal is respectively sent to the first counter and the second counter；First counter, is used
In proceeding by counting according to pre- fractional frequency signal to count initial value m, and count stop when, send first control signal to multiple
Position device, so that reset device exports high level signal according to the first control signal；Second counter, for according to pre-
Fractional frequency signal proceeds by counting to count initial value a, and when counting stopping, transmission second control signal to reset device,
So that reset device exports low level signal according to the second control signal.
6. frequency divider as claimed in claim 5, it is characterised in that the counting initial value m>Count initial value a >=1.
7. frequency divider as claimed in claim 5, it is characterised in that when first counter counts stopping, reset device
P/ (P+1) pre-divider is controlled to carry out the pre- frequency dividing that frequency dividing ratio is P, when the second counter counts stopping, reset device control P/
(P+1) pre-divider carries out the pre- frequency dividing that frequency dividing ratio is (P+1).
8. frequency divider as claimed in claim 5, it is characterised in that first computing module includes first adder, removes
Musical instruments used in a Buddhist or Taoist mass and the second register, the output terminal of first register and the output terminal of the second register are defeated with first adder
Enter end connection, the output terminal of the adder and the input terminal of divider connect, second computing module and the first counter
It is connected with the output terminal of divider.
9. frequency divider as claimed in claim 8, it is characterised in that second computing module includes multiplier and second and adds
Musical instruments used in a Buddhist or Taoist mass, the input terminal of the multiplier and the output terminal of divider connect, the output terminal connection second adder of the multiplier
Input terminal, the output terminal of second adder connects the second counter.
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| CN201510439323.5A CN104993826B (en) | 2015-07-22 | 2015-07-22 | A kind of dividing method and its device |
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| CN110868212B (en) * | 2019-12-02 | 2023-03-24 | 深圳清华大学研究院 | High-speed counting and comparing circuit and method thereof |
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| JPH10341156A (en) * | 1997-06-10 | 1998-12-22 | Sony Corp | Pll circuit |
| CN101557225A (en) * | 2009-05-05 | 2009-10-14 | 复旦大学 | Pulse swallow counter for fractional-crossover frequency synthesizer |
| CN102412836A (en) * | 2011-09-30 | 2012-04-11 | 杭州电子科技大学 | Dual programmable subtraction frequency divider |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH10341156A (en) * | 1997-06-10 | 1998-12-22 | Sony Corp | Pll circuit |
| CN101557225A (en) * | 2009-05-05 | 2009-10-14 | 复旦大学 | Pulse swallow counter for fractional-crossover frequency synthesizer |
| CN102412836A (en) * | 2011-09-30 | 2012-04-11 | 杭州电子科技大学 | Dual programmable subtraction frequency divider |
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