CN103326714A

CN103326714A - Digital control oscillator and method, system and detector for hardware performance detection

Info

Publication number: CN103326714A
Application number: CN2013102133215A
Authority: CN
Inventors: 金鑫; 王新入; 谢谦
Original assignee: Huawei Technologies Co Ltd
Current assignee: Shandong Jinhui Technology Consulting Co ltd
Priority date: 2013-05-31
Filing date: 2013-05-31
Publication date: 2013-09-25
Anticipated expiration: 2033-05-31
Also published as: CN103326714B

Abstract

The invention discloses a digital control oscillator, a method, system and detector for hardware performance detection and belongs to the technical field of electron. The detector for hardware performance detection comprises the digital control oscillator, a first frequency divider, a second frequency divider, a first counter, a second counter and a control unit. The control unit is connected with the digital control oscillator, so that the digital control oscillator is controlled to output an oscillation clock. Frequency division is conducted on a reference clock and the oscillation clock through the first frequency divider and the second frequency divider respectively so that a first frequency dividing clock and a second frequency dividing clock can be obtained. The first counter and the second counter count for the first frequency dividing clock and the second frequency dividing clock respectively in a preset counting period. A difference obtained through counting is output by the control unit. A parameter signal is determined under a correction mode; under an operation mode, the parameter signal is received and a detection value is output; voltage is reduced appropriately according to the detection value so that the power consumption can be reduced, or voltage is increased appropriately so that the stability of a circuit can be guaranteed.

Description

Numerically-controlled oscillator, hardware performance detection method, system and detector

Technical field

The present invention relates to electronic technology field, particularly a kind of numerically-controlled oscillator, hardware performance detection method, system and detector.

Background technology

AVS(Adaptive Voltage Scaling, the adaptive voltage adjustment) technology is as a kind of important method in the chip low power dissipation design, can detect the ruuning situation of current circuit automatically, promote or reduce the supply power voltage of chip, realize the self adaptation adjustment of chip power supply voltage.A typical AVS system as shown in Figure 1, configuration core CORE carries out parameter configuration by bus to the AVS system, and starts the AVS controller; Each HPM(Hardware Performance Monitor, the hardware performance detector) detects the performance of circuit in the zones of different respectively, and detected value returned to the AVS controller, the AVS controller determines whether to carry out pressure regulation according to the current HPM detected value that returns, when determining pressure regulation, realize the outer PMU(Power Management Unit of chip, Power Management Unit by the power management bus) control, finish the voltage adjustment.

HPM is as part important in the AVS system, the quality of its performance directly influences the income of AVS, the HPM performance is more good, more can correctly react the deferred message of critical path in the current chip, just can under the condition that guarantees the circuit operate as normal, adopt littler supply power voltage to reach the purpose of saving power consumption.

Prior art provides a kind of hardware performance detector (DC-HPM based on the time delay chain structure, Delay Chain Based HPM), see also shown in Fig. 2 A, this DC-HPM is made of some delay cells 211 time delay chain of forming and the latch (Latch) that is connected on this time delay chain, wherein reference clock T _RefIt is T that frequency divider 212 by a M frequency division obtains width _RefThe running clock of/2M, this running clock be as the enable signal of Latch on the time delay chain, and this running clock enters time delay chain and propagate at time delay chain, and the output valve by Latch can access this signal at T preset time _RefSpread length on the inherent time delay chain of/2M, the output valve of DC-HPM is this signal by the number of delay unit on the time delay chain 211.

Prior art also provides a kind of hardware performance detector (RO-HPM based on the ring oscillator structure, Ring Oscillator Based HPM), see also shown in Fig. 2 B, this RO-HPM comprises several annular oscillation rings 221 of being made up of delay unit 221a and XNOR gate 221b, the end of each annular oscillation rings 221 all connects a counting unit 222, and the input and output of delay unit 221a are connected on the XNOR gate 221b in the annular oscillation rings 221.When the Start signal is effective, this Start signal enters the delay unit in the annular oscillation rings 221, and the one-level delay unit is propagated backward, when XNOR gate 221b is output as 1, shows that the Start signal is transmitted to the corresponding delay unit 221a of this XNOR gate 221b; When the Stop signal is effective, counting unit 222 is deposited output with the output valve of XNOR gate 221b, also be that counting unit 222 is calculated a Start signal number of enclosing the delay unit 221a that walks in the end according to the output of XNOR gate 221b, the value that counting unit 222 will be calculated is sent to compiler Encoder.Counter Gray Counter can calculate the number of turns of the time delay chain that the Start signal walks, and this Gray Counter is connected with a counting unit 223, so that this counting unit 223 is sent to Encoder with the value that Gray Counter calculates.Encoder then can calculate the number of the delay unit 221a that the Start signal walks altogether like this.

Prior art also provides a kind of hardware performance detector (PLL-HPM based on phase-locked loop structures, Phase-locked Loop HPM), see also shown in Fig. 2 C, this PLL-HPM realizes the numerically-controlled oscillator (DCO that a frequency adjustable is whole by phase-locked loop, Digital Control Oscillator), change output signal frequency, wherein T by the length that changes time delay chain among this DCO _RefBe the reference clock of input, this reference clock carries out frequency division by M frequency divider 231, and the output signal of DCO is carried out frequency division by Fractional-N frequency device 232, and the locked clock cycle that obtains is T _Osc=T _Ref* M/N, the output valve HPM value of PLL-HPM is the number of delay unit in the oscillation rings.

In realizing process of the present invention, the inventor finds that there is the time delay chain indefinite length of following problem: DC-HPM at least in prior art, and the difference that detects clock frequency can cause time delay chain long, needs more delay unit, and adaptability is relatively poor; Having relatively high expectations in the circuit sequence of RO-HPM aspect, is had relatively high expectations in the front and back end of chip design, occurs easily because the unreasonable vibration linearity that causes of link design; Need long locking time when the output of PLL-HPM value is effective, can bring extra time-delay and power consumption thus.

Summary of the invention

Cause bad adaptability, the front and back end of chip design is required problem too high and that locking time is long in order to solve time delay chain indefinite length in the prior art, the embodiment of the invention provides a kind of numerically-controlled oscillator, hardware performance detection method, system and detector.Described technical scheme is as follows:

First aspect provides a kind of numerically-controlled oscillator, and described numerically-controlled oscillator comprises NAND gate, first time delay chain, second time delay chain and not gate,

Described first time delay chain is formed by several first delay unit cascades, and described first time delay chain receives the first group selection signal, determines effective first delay unit in described first time delay chain according to the described first group selection signal;

Described second time delay chain is formed by several second delay unit cascades, and described second time delay chain receives the second group selection signal, determines effective second delay unit in described second time delay chain according to the described second group selection signal;

The signal of the first input end input of described NAND gate is first enable signal, the output of described NAND gate is connected with the input of described not gate and first first delay unit of described first time delay chain respectively, first second delay unit in described second time delay chain is connected with first first delay unit of described first time delay chain and second input of described NAND gate respectively, and the signal of the output output of described not gate is running clock.

In first kind of first aspect possible execution mode, described first delay unit in described first time delay chain comprises first NOR gate and first selector,

The signal that the first input end of described first NOR gate receives is first group of threshold signal, second input of first NOR gate in first first delay unit is connected with the output of described NAND gate, the output of first NOR gate in second input of first NOR gate in i first delay unit and individual first delay unit of i-1 is connected, the first input end of the first selector in individual first delay unit of j is connected with the output of first NOR gate of j first delay unit, second input of the first selector of j first delay unit is connected with the output of the first selector of j+1 first delay unit, and the output of the first selector of first first delay unit is connected with first second delay unit in described second time delay chain;

Described delay unit in described second time delay chain comprises second NOR gate and second selector,

The signal that the first input end of described second NOR gate receives is second group of threshold signal, second input of second NOR gate in first second delay unit is connected with first first delay cell in described first time delay chain, the output of second NOR gate in second input of second NOR gate in i second delay unit and individual second delay unit of i-1 is connected, the first input end of the second selector in individual second delay unit of j is connected with the output of second NOR gate of j second delay unit, second input of the second selector of j second delay unit is connected with the output of the second selector of j+1 second delay unit, and the output of the second selector of first second delay unit is connected with second input of described NAND gate;

Wherein, described first group of threshold signal comprises the first threshold signal of predetermined number, and described second group of threshold signal comprises second threshold signal of predetermined number, i more than or equal to 2, j more than or equal to 1.

In conjunction with first kind of first aspect or first aspect possible execution mode, in second kind of possible execution mode,

If the selecting side receives described first and selects signal, assert that first delay unit of described first selector correspondence is effective, if receiving described first, the selecting side do not select signal, assert that first delay unit of described first selector correspondence is invalid;

If the selecting side receives described second and selects signal, assert that second delay unit of described second selector correspondence is effective, if receiving described second, the selecting side do not select signal, assert that second delay unit of described second selector correspondence is invalid;

Wherein, the described first selection signal is 0 or 1, and the described second selection signal is 0 or 1.

Second kind of possible execution mode in conjunction with first kind of first aspect, first aspect possible execution mode or first aspect, in the third possible execution mode, when described first selector receive described first when selecting signal to be 0, with one in the first input end of described first selector and second input as effective input, when described first selector receive described first when selecting signal to be 1, with the first input end of described first selector and in second input another as effective input;

When described selector receive described second when selecting signal to be 0, with one in the first input end of described second selector and second input as effective input, when described second selector receive described second when selecting signal to be 1, with the first input end of described second selector and in second input another as effective input.

In conjunction with second kind of possible execution mode of first kind of first aspect, first aspect possible execution mode, first aspect or the third possible execution mode of first aspect, in the 4th kind of possible execution mode, be set to 1 with being identified as the described first threshold signal that the first invalid delay unit receives in first time delay chain in the described numerically-controlled oscillator, be set to 1 with being identified as described second threshold signal that the second invalid delay unit receives in second time delay chain in the described numerically-controlled oscillator.

Second aspect provides a kind of hardware performance detector, and described hardware performance detector comprises: numerically-controlled oscillator, first frequency divider, second frequency divider, first counter, second counter and control unit,

Described control unit is used for the described numerically-controlled oscillator output of control running clock;

Described first frequency divider carries out frequency division to obtain first frequency-dividing clock to the predetermined reference clock, and described first counter counts to obtain first count value to described first frequency-dividing clock in the preset count cycle;

Described second frequency divider carries out frequency division to obtain second frequency-dividing clock to described running clock, and described second counter counts to obtain second count value to described second frequency-dividing clock in the preset count cycle;

Described control unit asks poor to described first count value and described second count value, and asks the difference that obtains after the difference to export as detected value described first count value and second count value, in order to carry out the voltage adjustment according to described detected value.

In first kind of second aspect possible execution mode, described control unit sends concrete be used for the sending first group selection signal and the second group selection signal;

Described numerically-controlled oscillator comprises: NAND gate, first time delay chain, second time delay chain and not gate,

Described first time delay chain is formed by several first delay unit cascades, and described first time delay chain receives the first group selection signal that described control unit sends, and determines effective first delay unit in described first time delay chain according to the described first group selection signal;

Described second time delay chain is formed by several second delay unit cascades, and described second time delay chain receives the second group selection signal that described control unit sends, and determines effective second delay unit in described second time delay chain according to the described second group selection signal;

The signal of the first input end input of described NAND gate is first enable signal, the output of described NAND gate is connected with the input of described not gate and first first delay unit of described first time delay chain respectively, first second delay unit in described second time delay chain is connected with first first delay unit of described first time delay chain and second input of described NAND gate respectively, and the signal of the output output of described not gate is described running clock.

In conjunction with first kind of second aspect or second aspect possible execution mode, in second kind of possible execution mode, described control unit sends concrete be used for sending first group of threshold signal and second group of threshold signal;

Described first delay unit in described first time delay chain comprises first NOR gate and first selector,

The signal of the first input end input of described first NOR gate is first group of threshold signal that described control unit sends, second input of the NOR gate in first first delay unit is connected with the output of described NAND gate, the output of first NOR gate in second input of first NOR gate in i first delay unit and individual first delay unit of i-1 is connected, the first input end of the first selector in individual first delay unit of j is connected with the output of first NOR gate of j first delay unit, second input of the first selector of j first delay unit is connected with the output of the first selector of j+1 first delay unit, and the output of the first selector of first first delay unit is connected with first second delay unit in described second time delay chain;

The signal of the first input end input of described second NOR gate is second group of threshold signal that described control unit sends, second input of second NOR gate in first second delay unit is connected with first first delay cell in described first time delay chain, the output of second NOR gate in second input of second NOR gate in i second delay unit and individual second delay unit of i-1 is connected, the first input end of the second selector in individual second delay unit of j is connected with the output of second NOR gate of j second delay unit, second input of the second selector of j second delay unit is connected with the output of the second selector of j+1 second delay unit, and the output of the second selector of first second delay unit is connected with second input of described NAND gate;

Second kind of possible execution mode in conjunction with first kind of second aspect, second aspect possible execution mode or second aspect, in the third possible execution mode, described first frequency divider carries out the M frequency division to described reference clock, described second frequency divider carries out Fractional-N frequency to the running clock of described numerically-controlled oscillator output, described control unit comprises mode selection module and control module

Described mode selection module be used for to be selected a kind of signal of calibrating signal or operation signal, and the signal of described selection is inputed to described control module;

Described control module, be used for receiving ratio signal, described calibrating signal according to the described ratio signal that receives and the selection of described mode selection module generates the described first group selection signal and the described second group selection signal, and the described first group selection signal and the described second group selection signal exported to described numerically-controlled oscillator, so that described numerically-controlled oscillator is determined effective delay unit in described first time delay chain and described second time delay chain respectively according to the described first group selection signal that receives and the described second group selection signal, so that T _DCO﹒ N=T _Core﹒ M is at T _DCO﹒ N=T _CoreDuring ﹒ M, the described ratio signal of current correspondence is regarded as parameter signal, wherein, described T _DCOBe the cycle of the running clock of described numerically-controlled oscillator output, described T _CoreBe the cycle of described reference clock;

Described control module, be used for receiving described parameter signal, operation signal according to the described parameter signal that receives and the selection of described mode selection module generates the described first group selection signal and the described second group selection signal, and the described first group selection signal and the described second group selection signal exported to described numerically-controlled oscillator, so that described numerically-controlled oscillator is according to the described first group selection signal that receives and described second group selection signal output running clock

Wherein, M and N are the natural number greater than 0.

In conjunction with second kind of possible execution mode of first kind of second aspect, second aspect possible execution mode, second aspect or the third possible execution mode of second aspect, in the 4th kind of possible execution mode, described first time delay chain receives the first group selection signal, determine effective first delay unit in described first time delay chain according to the described first group selection signal, comprising:

If the selecting side receives first in the described first group selection signal and selects signal, first delay unit of assert described first selector correspondence is effective, if the selecting side does not receive first in the described first group selection signal and selects signal, assert that first delay unit of described first selector correspondence is invalid;

Described second time delay chain receives the second group selection signal, determines effective second delay unit in described second time delay chain according to the described second group selection signal, comprising:

If the selecting side receives second in the described second group selection signal and selects signal, second delay unit of assert described second selector correspondence is effective, if the selecting side does not receive second in the described second group selection signal and selects signal, assert that second delay unit of described second selector correspondence is invalid;

In conjunction with second aspect, first kind of possible execution mode of second aspect, second kind of possible execution mode of second aspect, the 4th kind of possible execution mode of the execution mode that the third of second aspect is possible or second aspect, in the 5th kind of possible execution mode, when described first selector receive described first when selecting signal to be 0, with one in the first input end of described first selector and second input as effective input, when described first selector receive described first when selecting signal to be 1, with the first input end of described selector and in second input another as effective input;

When described second selector receive described second when selecting signal to be 0, with one in the first input end of described second selector and second input as effective input, when described second selector receive described second when selecting signal to be 1, with the first input end of described second selector and in second input another as effective input.

In conjunction with second aspect, first kind of possible execution mode of second aspect, second kind of possible execution mode of second aspect, the execution mode that the third of second aspect is possible, the 4th kind of possible execution mode of second aspect or the 5th kind of possible execution mode of second aspect, in the 6th kind of possible execution mode, be set to 1 with being identified as the described first threshold signal that the first invalid delay unit receives in first time delay chain in the described numerically-controlled oscillator, be set to 1 with being identified as described second threshold signal that the second invalid delay unit receives in second time delay chain in the described numerically-controlled oscillator.

The third aspect provides a kind of voltage adjustment system, described system comprise that configuration nucleus module, voltage regulation controller, Power Management Unit and at least one various implementation as second aspect and second aspect provide as described in the hardware performance detector,

Described configuration nucleus module carries out the predetermined parameters configuration and starts described voltage adjustment system described hardware performance detection system by bus;

Described hardware performance detector is connected with described voltage regulation controller, and described hardware performance detector to obtain detected value, feeds back to described voltage regulation controller with described detected value for detection of the performance of circuit in the presumptive area;

Described voltage regulation controller determines whether that according to described detected value needs carry out the voltage adjustment, if when determining to carry out pressure regulation, then by the described Power Management Unit of the total line traffic control of power management, so that described Power Management Unit is carried out the voltage adjustment.

In first kind of the third aspect possible execution mode, the detected value of described hardware performance detector output is that first count value deducts the difference that second count value obtains, described voltage regulation controller determines whether that according to described detected value needs carry out the voltage adjustment, comprising:

When described detected value greater than zero the time, reduce voltage; When described detected value less than zero the time, heighten voltage;

Or,

The detected value of described hardware performance detector output is that second count value deducts the difference that first count value obtains, and described voltage regulation controller determines whether that according to described detected value needs carry out the voltage adjustment, comprising:

When described detected value greater than zero the time, heighten voltage; When described detected value less than zero the time, reduce voltage.

Fourth aspect provides a kind of hardware performance detection method, and described method comprises:

Receive operation signal, predefined parameter signal and reference clock;

Regulate numerically-controlled oscillator so that described numerically-controlled oscillator output running clock according to described parameter signal;

Described reference clock is carried out the M frequency division to obtain first frequency-dividing clock;

Described running clock is carried out Fractional-N frequency to obtain second frequency-dividing clock;

In the preset count cycle, described first frequency-dividing clock is counted to obtain first count value, described second frequency-dividing clock is counted to obtain second count value;

Export the difference of described first count value and described second count value,

Wherein, M and N are the natural number greater than 0.

In first kind of fourth aspect possible execution mode, describedly regulate described numerically-controlled oscillator so that described numerically-controlled oscillator output running clock comprises according to described parameter signal:

Export the first group selection signal and the second group selection signal according to described parameter signal;

Determine in the described numerically-controlled oscillator effective first delay unit in first time delay chain according to the described first group selection signal;

Determine in the described numerically-controlled oscillator effective second delay unit in second time delay chain according to the described second group selection signal;

According to effective second delay unit output running clock in effective first delay unit and described second time delay chain in described first time delay chain of determining.

In conjunction with first kind of fourth aspect or fourth aspect possible execution mode, in second kind of possible execution mode, before described reception operation signal, predefined parameter signal and the reference clock, described method also comprises:

Receive calibrating signal, ratio signal and reference clock;

Regulate described numerically-controlled oscillator so that described numerically-controlled oscillator output running clock according to described ratio signal;

When described running clock and described reference clock satisfy T _DCO﹒ N=T _CoreDuring ﹒ M, described ratio signal is regarded as predefined parameter signal, described T _DCOBe the cycle of the described running clock of described numerically-controlled oscillator output, described T _CoreBe the cycle of described reference clock.

The beneficial effect that the technical scheme that the embodiment of the invention provides is brought is:

Under calibration mode, determine parameter signal; Under operator scheme, receive this parameter signal with the ratio of effective second delay unit on effective first delay unit and second time delay chain on inner first time delay chain of definite numerically-controlled oscillator, and then output running clock, respectively reference clock and this running clock that receives carried out frequency division to obtain first frequency-dividing clock and second frequency-dividing clock, in the preset count cycle this first frequency-dividing clock and second frequency-dividing clock are counted to obtain first count value and second count value simultaneously, when first count value during greater than second count value, the better performances that shows detected circuit, it is less to delay time, reduction voltage that at this moment can be suitable is with the reduction power consumption, otherwise lifting voltage that can be suitable is to guarantee the stationarity of circuit; Therefore this hardware performance detector no longer limits the number of delay unit, do not need the number of delay unit is counted, do not need the delay unit in the numerically-controlled oscillator is repeatedly adjusted yet, having solved time delay chain indefinite length in the prior art causes bad adaptability, the front and back end of chip design is required problem too high and that locking time is long, having reached only needs to import predefined parameter signal and just can determine whether that needs adjust voltage, simplify the calibration flow process, and the effect of the application of high-speed sampling is satisfied in the designing requirement of facilitating chip front and back end.

Description of drawings

In order to be illustrated more clearly in the technical scheme in the embodiment of the invention, the accompanying drawing of required use is done to introduce simply in will describing embodiment below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.

Fig. 1 is the schematic diagram of the AVS application system that provides in the prior art;

Fig. 2 A is the structural representation of the DC-HPM that provides in the prior art one;

Fig. 2 B is the structural representation of the RO-HPM that provides in the prior art two;

Fig. 2 C is the structural representation that PLL-HPM is provided in the prior art three;

Fig. 3 is the structural representation of the hardware performance detector that provides of the embodiment of the invention one;

Fig. 4 is the structural representation of numerically-controlled oscillator in the hardware performance detector that provides of the embodiment of the invention two;

Fig. 5 is the method flow diagram of the hardware performance detection method that provides of the embodiment of the invention three;

Fig. 6 is the schematic diagram of the voltage adjustment system that provides of the embodiment of the invention four.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.

Embodiment one

See also shown in Figure 3ly, it shows the structural representation of the hardware performance detector that the embodiment of the invention one provides.This hardware performance detector 30, can but be not limited to comprise: control unit 31, numerically-controlled oscillator 32, first frequency divider 33, second frequency divider 34, first counter 35 and second counter 36.

Control unit 31 is connected with numerically-controlled oscillator 32, so that control figure control generator 32 output running clocks, running clock is the clock signal of numerically-controlled oscillator 32 outputs.

33 pairs of predetermined reference clocks of first frequency divider carry out frequency division to obtain first frequency-dividing clock, and the running clock of 34 pairs of numerically-controlled oscillators of second frequency divider, 32 outputs carries out frequency division to obtain second frequency-dividing clock.In actual applications, the predetermined reference clock is the clock that system provides, and is used for comparing with running clock.

First counter 35 was counted first frequency-dividing clock in the preset count cycle; In the same preset count cycle, 36 pairs of second frequency-dividing clocks of second counter are counted.Usually, first counter 35 and second counter 36 receive second enable signal synchronously, so that pick up counting under the situation that second enable signal enables.

Obviously, first counter 35 and second counter 36 can be two separate equipment, also can be to be integrated in two counters in the same equipment, even can be two counting modules in the same counter.

Concrete, control unit 31 can but be not limited to comprise: mode selection module 311, control module 312 and difference block 313.

Mode selection module 311 can be used for selecting a kind of signal of calibrating signal or operation signal, generally, before circuit is detected, at first needs this hardware performance detector 30 is calibrated.Mode selection module 311 can be for including the module of selector, and then can select needed signal by this selector is calibrating signal or operation signal.

After mode selection module 311 is selected calibrating signal, this hardware performance detector 30 is calibration mode, under calibration mode, control module 312 receives ratio signal, after control module 312 receives ratio signal, generate corresponding signal to send to numerically-controlled oscillator 32 so that numerically-controlled oscillator 32 output running clocks.Corresponding, second frequency divider 34 carries out Fractional-N frequency with this running clock, and first frequency divider carries out the M frequency division with reference clock, and the M here and N are the natural number greater than 0.

Difference block 313 is used for calculating the difference of second count value that first counter 35 obtains in same predetermined count cycle first count value and second counter 36 obtain, and with the detected value output as this hardware performance detector 30 of the difference of first count value and second count value.By way of example, first count value can be deducted second count value, and this first count value be deducted the difference of second count value as the detected value output of this hardware performance detector; Again by way of example, second count value can also be deducted first count value, and this second count value be deducted the difference of first count value as the detected value output of this hardware performance detector.

When the value of detected value is 0, just work as T _DCO﹒ N=T _CoreDuring ﹒ M, the ratio signal of current correspondence is regarded as parameter signal, be about to the ratio signal of current correspondence as the parameter signal under the operator scheme.Wherein, T _DCOBe the cycle of the running clock of numerically-controlled oscillator 32 output, T _CoreBe the cycle of reference clock.

When circuit is detected, mode selection module 311 is selected operation signal, this moment, this hardware performance detector 30 was operator scheme, and corresponding control module 312 is received in the parameter signal that obtains under the calibration mode, with control figure control generator 32 output running clocks.Same, first frequency divider 33 and second frequency divider 34 carry out frequency division to obtain first frequency-dividing clock and second frequency-dividing clock to the running clock of reference clock and numerically-controlled oscillator 32 outputs respectively, and first counter 35 and second counter 36 count to obtain first count value and second count value to first frequency-dividing clock and second frequency-dividing clock respectively in the preset count cycle.Difference block 313 calculates the difference of first count value and second count value, and the difference that obtains is exported as the detected value of hardware performance detector 30.

It should be noted that, in same measurement environment, if under calibration mode, what difference block 313 was used for calculating is that first count value deducts second count value, also needing under operator scheme so is that first count value deducts second count value, so just has comparativity.Obviously, in same measurement environment, if under calibration mode, what difference block 313 was used for calculating is that second count value deducts first count value, and also needing under operator scheme so is that second count value deducts first count value.

In the scene that specifically circuit is detected, what calculate with difference block 313 is that to deduct second count value be example to first count value, if the value of the detected value of hardware performance detector 30 is greater than zero, the better performances that then shows this detected circuit, circuit delay is less, can suitably reduce voltage to reduce power consumption; If the value of detected value less than zero, then shows the poor-performing of this detected circuit, circuit delay is bigger, and suitably booster tension is steady to guarantee circuit.

Need to prove, include first time delay chain and second time delay chain in the numerically-controlled oscillator 32, comprise first delay unit of at least two cascades in first time delay chain, comprise second delay unit of at least two cascades in second time delay chain.First time delay chain can receive the first group selection signal of control module 312 generations to determine effective first delay unit, second time delay chain can receive the second group selection signal of control module 312 generations to determine effective second delay unit, numerically-controlled oscillator 32 can be according to effective first delay unit of determining and second delay unit output running clock, the concrete structure of numerically-controlled oscillator 32 can referring among the embodiment two to the description of Fig. 4, just repeat no more here.

In sum, the hardware performance detector that the embodiment of the invention provides under calibration mode, is determined parameter signal; Under operator scheme, receive this parameter signal with the output detected value; Such as, when detected value greater than zero the time, show the better performances of detected circuit, it is less delay time, the reduction voltage that this moment can be suitable is reducing power consumption, otherwise lifting voltage that can be suitable is with the stationarity of assurance circuit; Therefore this hardware performance detector no longer limits the number of delay unit, do not need the number of delay unit is counted, do not need the delay unit in the numerically-controlled oscillator is repeatedly adjusted yet, having solved time delay chain indefinite length in the prior art causes bad adaptability, the front and back end of chip design is required problem too high and that locking time is long, having reached only needs to import predefined parameter signal and just can determine whether that needs adjust voltage, simplify the calibration flow process, and the effect of the application of high-speed sampling is satisfied in the designing requirement of facilitating chip front and back end.

Embodiment two

See also shown in Figure 4ly, it shows the structural representation of numerically-controlled oscillator in the hardware performance detector that the embodiment of the invention two provides.This numerically-controlled oscillator can be the numerically-controlled oscillator 32 shown in Fig. 1, and this numerically-controlled oscillator can comprise: NAND gate 410, first time delay chain 420, second time delay chain 430 and not gate 440.

First time delay chain 420 is formed by at least two first delay unit cascades, and as shown in Figure 4, first time delay chain 420 comprises first delay unit that a plurality of cascades such as the first delay unit 420a, the first delay unit 420b and the first delay unit 420c form.First time delay chain 420 can receive the first group selection signal that control unit 31 sends, and determines effective first delay unit in first time delay chain 420 according to the first group selection signal.Wherein, the first group selection signal is one group of signal that includes at least one first selection signal composition that control unit 31 produces after receiving ratio signal or parameter signal.That is to say, the first group selection signal can select signal to form by first of predetermined number, such as, the first group selection signal can be 0001, namely include four first in this group selection signal and select signal, select the value of signal to be respectively 0,0,0 and 1 for these four first.

By way of example, when receiving the selection of first in first group selection signal signal in some first delay units, then this first delay unit is effective, and when not receiving the selection of first in first group selection signal signal in some first delay units, then this first delay unit is invalid.

Second time delay chain 430 is formed by at least two second delay unit cascades, and as shown in Figure 4, second time delay chain 430 comprises second delay unit that a plurality of cascades such as the second delay unit 430a, the second delay unit 430b and the second delay unit 430c form.Second time delay chain 430 receives the second group selection signal that control unit 31 sends, and determines effective second delay unit in second time delay chain according to the second group selection signal.Wherein the second group selection signal is the one group of signal that includes at least one second selection signal that control unit 31 produces after receiving ratio signal or parameter signal.That is to say that the second group selection signal can select signal to form by second of predetermined number, such as, the second group selection signal can be 01, namely includes two second in this group selection signal and selects signal, selects the value of signal to be respectively 0 and 1 for these two second.

By way of example, when receiving the second selection signal in second delay unit, then this second delay unit is effective, and when not receiving the second selection signal in second delay unit, then this second delay unit is invalid.

The signal of the first input end input of NAND gate 410 is first enable signal, this first enable signal is normally sent by control unit 31, certainly, first enable signal also can send for other components and parts, this first enable signal can enable NAND gate, so that this numerically-controlled oscillator 32 can be exported running clock.The input of the output difference NAND gate 440 of NAND gate 410 and first first delay unit 420a of first time delay chain 420 connect, first second delay unit 430a in second time delay chain 430 is connected with first first delay unit 420a of first time delay chain 420 and second input of NAND gate 410 respectively, and the signal of the output output of not gate 440 is the running clock of numerically-controlled oscillator 32 outputs.

Generally, first delay unit in first time delay chain is normally identical, and second delay unit in second time delay chain is normally identical.In a concrete application scenarios, first delay unit in first time delay chain 420 comprises first NOR gate and first selector, the signal of the first input end input of first NOR gate in first time delay chain 420 in each first delay unit is first group of threshold signal that control unit 312 sends, second input of first NOR gate among first first delay unit 420a is connected with the output of NAND gate, the output of first NOR gate in second input of first NOR gate in i first delay unit and individual first delay unit of i-1 is connected, the first input end of the first selector in individual first delay unit of j is connected with the output of first NOR gate of j first delay unit, second input of the first selector of j first delay unit is connected with the output of the first selector of j+1 first delay unit, and the output of the first selector of first first delay unit 420a is connected with first second delay unit 430a in second time delay chain 430; Wherein, first group of threshold signal comprises the first threshold signal of predetermined number, i more than or equal to 2, j more than or equal to 1.

The selecting side of the first selector in first delay unit receives first and selects signal, and two inputs of first selector receive the output signal of first selector in the output signal of first NOR gate of first delay unit under this first selector and back first delay unit respectively.When the selecting side of first selector receives first to select signal is a kind of in 0 or 1, select one of them input as effective input of this first selector, be about to the input signal of effective input as effective input signal, and export this effective input signal by the output of first selector; When first selector receives first to select signal is another kind of in 0 or 1, select another input as effective input of this first selector, be about to the input signal of effective input as effective input signal, and export this effective input signal by the output of first selector.Such as, if first selector receive first when to select signal be a kind of in 0 or 1, this first selector is selected the output signal of the NOR gate of its affiliated first delay unit effective input signal as this first selector; If first selector receive first when to select signal be another kind of in 0 or 1, this first selector is selected the output signal of the first selector of the back first delay unit effective input signal as this first selector.

By way of example, when the first selector among the first delay unit 420a receive first when selecting signal to be 0, then select the output signal of first selector among the back first delay unit 420b as effective input signal of this first selector 420a; When first selector among the first delay unit 420b receive first when selecting signal to be 1, then select the output signal of first NOR gate among this first delay unit 420b as effective input signal of this first selector.Like this, when the first time-delay link, the 420 first group selection signals of receiving are 0001, show that preceding four first delay units in first time delay chain are effective delay unit, that is to say that the signal of NAND gate output is through first NOR gate in first first delay unit, first NOR gate of second first delay unit, first NOR gate of the 3rd first delay unit, first NOR gate of the 4th first delay unit, the first selector of the 4th first delay unit, the first selector of the 3rd first delay unit, the first selector output of the first selector of second first delay unit and first first delay unit.In other words, effective input signal of first selector all is that the output of first selector from back first delay unit receives in first three first delay unit; Effective input signal of first selector is the output signal of first NOR gate in the 4th first delay unit in the 4th first delay unit.

Similarly, second delay unit in second time delay chain 430 comprises second NOR gate and second selector, wherein, the signal of the first input end input of second NOR gate of all second delay units in second time delay chain 430 is second group of threshold signal that control unit sends, second input of second NOR gate in first second delay unit is connected with first first delay cell in first time delay chain, the output of second NOR gate in second input of second NOR gate in i second delay unit and individual second delay unit of i-1 is connected, the first input end of the second selector in individual second delay unit of j is connected with the output of second NOR gate of j second delay unit, second input of the second selector of j second delay unit is connected with the output of the second selector of j+1 second delay unit, and the output of the second selector of first second delay unit is connected with second input of NAND gate; Wherein, second group of threshold signal comprises second threshold signal of predetermined number, i more than or equal to 2, j more than or equal to 1.

The selecting side of the second selector in second delay unit receives second and selects signal, and two inputs of second selector receive the output signal of second selector in the output signal of second NOR gate of second delay unit under this second selector and back second delay unit respectively.When the selecting side of second selector receives first to select signal is a kind of in 0 or 1, select one of them input as effective input of this second selector, be about to the input signal of effective input as effective input signal, and export this effective input signal by the output of second selector; When second selector receives first to select signal is another kind of in 0 or 1, select another input as effective input of this second selector, be about to the input signal of effective input as effective input signal, and export this effective input signal by the output of second selector.Such as, if second selector receive first when to select signal be a kind of in 0 or 1, this second selector is selected the output signal of the NOR gate of delay unit under it effective input signal as this second selector; If second selector receive first when to select signal be another kind of in 0 or 1, this second selector is selected the output signal of the second selector of a back delay unit effective input signal as this second selector.

By way of example, when the second selector among the second delay unit 430a receive second when selecting signal to be 0, then select the output signal of second selector among the back second delay unit 430b as effective input signal of second selector 430a; When second selector among the second delay unit 430b receive second when selecting signal to be 1, then select the output signal of second NOR gate among the second delay unit 430b as effective input signal of second selector 430b.Like this, when second selects signal to be 01, show that preceding two second delay units in second time delay chain are effective second delay unit, that is to say that the output signal of the first selector of first first delay unit 420a is through the second selector of second NOR gate of first second delay unit 430a in second time delay chain 430, second NOR gate of second second delay unit 430b, second second delay unit 430b, the second selector output of first second delay unit 430a in first time delay chain 420.In other words, effective input signal of second selector is that the output of second selector from second second delay unit 430b receives among first second delay unit 430a; Effective input signal of second selector is the output signal of second NOR gate among second second delay unit 430b among second second delay unit 430b.

In a more excellent scene, after first time delay chain 420 and second time delay chain 430 receive the first group selection signal and the second group selection signal, can determine effective first delay unit in first time delay chain 420 and effective second delay unit in second time delay chain 430.The first threshold signal that first invalid in first time delay chain 420 delay unit can be received is set to 1 so that with the output clamper of first NOR gate in this first delay unit on 0, and then can avoid extra upset to save power consumption.In like manner, second threshold signal that second invalid in second time delay chain 430 delay unit can be received is set to 1 so that with the output clamper of second NOR gate in this second delay unit on 0, and then can avoid extra upset to save power consumption.

It should be noted that here in order more to be conducive to adjust running clock, when first time delay chain and second time delay chain are set, the different delay unit that adopts usually.By way of example, first delay unit all can be set to by high threshold voltage (HVT, High Voltage Transistor) delay unit of transistor composition, corresponding, second delay unit all is set to the delay unit formed by low threshold voltage (LVT, Low Voltage Transistor) transistor.Again by way of example, first delay unit all can also be set to by low threshold voltage (LVT, Low Voltage Transistor) delay unit of transistor composition, corresponding, second delay unit all is set to the delay unit formed by high threshold voltage (HVT, High Voltage Transistor) transistor.Wherein, high threshold voltage is greater than low threshold voltage.

It should be noted that, first delay unit and second delay unit that include NOR gate and selector have only been described above, in actual applications, first delay unit or second delay unit can also be other structure, such as being the delay unit that is made of transistor in first delay unit or second delay unit.Present embodiment is not done restriction to the concrete components and parts in the delay unit.

Under calibration mode, hardware performance detector 30 can be determined parameter signal, under operator scheme, after control module 312 receives this parameter signal, then can export the first group selection signal, the second group selection signal, first group of threshold signal and second group of threshold signal according to the parameter signal that receives, and these signals are sent to numerically-controlled oscillator 32; Numerically-controlled oscillator 32 is after receiving the first group selection signal and the second group selection signal, effective second delay unit in effective first delay unit and second time delay chain 430 can be determined in first time delay chain 420, and then corresponding running clock can be exported.Corresponding, 33 pairs of reference clocks of first frequency divider carry out frequency division to obtain first frequency-dividing clock, the running clock of 34 pairs of numerically-controlled oscillators of second frequency divider, 32 outputs is to obtain second frequency-dividing clock, 35 pairs of first frequency-dividing clocks of first counter count to obtain first count value, and second counter 36 can count to obtain second count value to second frequency-dividing clock.Second count value that 313 pairs of first count values that first counter 35 gets access in the preset count cycle of difference block and second counter 36 get access to asks poor, and will ask the poor difference that obtains as the detected value of hardware performance detector 30.By way of example, deduct in first count value under the situation of difference as the detected value of difference block 313 of second count value, when the value of this detected value greater than zero the time, show that then detected circuit performance is better, it is less to delay time, and therefore can suitably reduce voltage to reduce power consumption; When the value of this detected value less than zero the time, show that then detected circuit performance is relatively poor, it is bigger delay time, therefore suitable lifting voltage steady with the assurance circuit.

In sum, the numerically-controlled oscillator that the embodiment of the invention provides under calibration mode, is determined parameter signal; Under operator scheme, receive this parameter signal to determine the ratio of effective delay unit on inner first time delay chain of numerically-controlled oscillator and second time delay chain, and then output running clock, respectively reference clock and this running clock that receives carried out frequency division to obtain first frequency-dividing clock and second frequency-dividing clock, simultaneously this first frequency-dividing clock and second frequency-dividing clock are counted to obtain first count value and second count value, at one time in the section, when first count value during greater than second count value, the better performances that shows detected circuit, it is less to delay time, reduction voltage that at this moment can be suitable is with the reduction power consumption, otherwise lifting voltage that can be suitable is to guarantee the stationarity of circuit; Therefore this hardware performance detector no longer limits the number of delay unit, do not need the number of delay unit is counted, do not need the delay unit in the numerically-controlled oscillator is repeatedly adjusted yet, having solved time delay chain indefinite length in the prior art causes bad adaptability, the front and back end of chip design is required problem too high and that locking time is long, having reached only needs to import predefined parameter signal and just can determine whether that needs adjust voltage, simplify the calibration flow process, and the effect of the application of high-speed sampling is satisfied in the designing requirement of facilitating chip front and back end.

Embodiment three

See also shown in Figure 5ly, it shows the method flow diagram of the hardware performance detection method that the embodiment of the invention three provides.This hardware performance detection method can comprise:

501, after receiving operation signal, receive predefined parameter signal and reference clock;

In concrete application scenarios, the hardware performance detection method also comprised the process of calibration before step 501, can obtain this predefined parameter signal by calibration process.The process of calibration can comprise:

The first, after receiving calibrating signal, receive ratio signal and reference clock;

Usually, the mode selection module 311 in the control unit 31 is receiving calibrating signal, shows that hardware performance detector 30 enters calibration mode.Entering under the calibration mode, hardware performance detector 30 receives ratio signal and reference clock.

The second, regulate numerically-controlled oscillator so that numerically-controlled oscillator output running clock according to ratio signal;

Control module 312 can generate the first group selection signal after receiving ratio signal and the second group selection signal is exported running clock with the control figure control generator.

Wherein, the first group selection signal is the one group of signal that includes at least one first selection signal.That is to say, the first group selection signal can select signal to form by first of predetermined number, such as, the first group selection signal can be 0001, namely include four first in this group selection signal and select signal, select the value of signal to be respectively 0,0,0 and 1 for these four first; The second group selection signal is the one group of signal that includes at least one second selection signal.That is to say that the second group selection signal can select signal to form by second of predetermined number, such as, the second group selection signal can be 01, namely includes two second in this group selection signal and selects signal, selects the value of signal to be respectively 0 and 1 for these two second.

The 3rd, reference clock is carried out the M frequency division to obtain first frequency-dividing clock;

The 4th, running clock is carried out Fractional-N frequency to obtain second frequency-dividing clock;

The 5th, when running clock and reference clock satisfy T _DCO﹒ N=T _CoreDuring ﹒ M, ratio signal is regarded as predefined parameter signal, so that hardware performance detector 30 detects T according to the performance of this parameter signal to circuit under operator scheme _DCOBe the cycle of the running clock of numerically-controlled oscillator output, T _CoreBe the cycle of reference clock.

That is to say, adjust ratio signal, so that running clock and reference clock satisfy T _DCO﹒ N=T _Core﹒ M, this moment, ratio signal namely can be as the parameter signal under the operator scheme.Like this, select operation signals at mode selection module 311, namely hardware performance detector 30 enters operator scheme following time, and the ratio signal of this moment is set to this parameter signal.

502, regulate the numerically-controlled oscillator numerically-controlled oscillator so that numerically-controlled oscillator output running clock according to parameter signal;

In concrete scene, numerically-controlled oscillator can comprise first time delay chain that is formed by several first delay unit cascades, second time delay chain that is formed by several second delay unit cascades.Regulate the numerically-controlled oscillator numerically-controlled oscillator so that numerically-controlled oscillator output running clock can comprise according to parameter signal:

The first, export the first group selection signal and the second group selection signal according to parameter signal;

The second, determine in the numerically-controlled oscillator effective first delay unit in first time delay chain according to the first group selection signal;

By way of example, when first delay unit receives the selection of first in first group selection signal signal, show that then this first delay unit is effective; When first delay unit does not receive the selection of first in first group selection signal signal, show that then this first delay unit is invalid.

The 3rd, determine in the numerically-controlled oscillator effective second delay unit in second time delay chain according to the second group selection signal;

By way of example, when second delay unit receives the selection of second in second group selection signal signal, show that then this second delay unit is effective; When second delay unit does not receive the selection of second in second group selection signal signal, show that then this second delay unit is invalid.

The 4th, according to effective second delay unit output running clock in effective first delay unit and second time delay chain in first time delay chain of determining.

503, reference clock is carried out the M frequency division to obtain first frequency-dividing clock;

504, running clock is carried out Fractional-N frequency to obtain second frequency-dividing clock;

505, in the preset count cycle, first frequency-dividing clock is counted to obtain first count value, second frequency-dividing clock is counted to obtain second count value;

506, export the difference of first count value and second count value.

By way of example, deduct second count value and obtain if this difference is first count value, when this difference is positive number, show usually that then the performance of this detected circuit is good, it is little delay time, therefore can suitably reduce voltage, with the minimizing power consumption; When this difference is negative, then show the poor-performing of this detected circuit usually, it is bigger to delay time, and therefore suitable booster tension is with assurance circuit operate as normal.

In sum, the hardware performance detection method that the embodiment of the invention provides under calibration mode, is determined parameter signal; Under operator scheme, receive this parameter signal to determine the ratio of effective delay unit on inner first time delay chain of numerically-controlled oscillator and second time delay chain, and then output running clock, respectively reference clock and this running clock that receives carried out frequency division to obtain first frequency-dividing clock and second frequency-dividing clock, simultaneously this first frequency-dividing clock and second frequency-dividing clock are counted to obtain first count value and second count value, at one time in the section, when first count value during greater than second count value, the better performances that shows detected circuit, it is less to delay time, reduction voltage that at this moment can be suitable is with the reduction power consumption, otherwise lifting voltage that can be suitable is to guarantee the stationarity of circuit; Therefore this hardware performance detector no longer limits the number of delay unit, do not need the number of delay unit is counted, do not need the delay unit in the numerically-controlled oscillator is repeatedly adjusted yet, having solved time delay chain indefinite length in the prior art causes bad adaptability, the front and back end of chip design is required problem too high and that locking time is long, having reached only needs to import predefined parameter signal and just can determine whether that needs adjust voltage, simplify the calibration flow process, and the effect of the application of high-speed sampling is satisfied in the designing requirement of facilitating chip front and back end.

Embodiment four

See also shown in Figure 6ly, it shows the schematic diagram of the voltage adjustment system that the embodiment of the invention four provides.This voltage adjustment system can include but not limited to: configuration nucleus module 610, voltage regulation controller 620, at least one hardware performance detector 630 and Power Management Unit 640.

In actual applications, the hardware performance detector that can provide for embodiment one of at least one hardware performance detector 630 here.

Described configuration nucleus module 610 carries out the predetermined parameters configuration and starts described voltage adjustment system described hardware performance detection system by bus.By way of example, the parameter here can be reference clock mentioned among the embodiment one, ratio signal, reference signal or operation signal etc.

Each described hardware performance detector 630 all is connected with described voltage regulation controller 620, described hardware performance detector 630 to obtain detected value, feeds back to described voltage regulation controller 630 with described detected value for detection of the performance of circuit in the presumptive area.By way of example, the detected value here is the difference that difference block 313 mentioned among the embodiment one is exported.

Described voltage regulation controller 620 determines whether that according to described detected value needs carry out the voltage adjustment, when if described voltage regulation controller 620 determines that according to described detected value needs carry out pressure regulation, then by the described Power Management Unit 640 of the total line traffic control of power management, so that Power Management Unit 640 is carried out the voltage adjustment.By way of example, when the detected value of hardware performance detector 630 be according to embodiment one in first count value when deducting the difference that second count value obtains, then when this detected value greater than zero the time, the better performances that then shows detected circuit, it is less to delay time, reduction voltage that at this moment can be suitable is with the reduction power consumption, otherwise lifting voltage that can be suitable is to guarantee the stationarity of circuit.Again by way of example, the detected value that obtains when hardware performance detector 630 is that second count value is when deducting the difference that first count value obtains, then when this detected value greater than zero the time, the poor-performing that then shows detected circuit, it is bigger to delay time, this moment can be suitable heighten voltage guaranteeing the stationarity of detected circuit, otherwise reduction voltage that can be suitable is to reduce power consumption.

In sum, the hardware performance detection system that the embodiment of the invention provides, finish Performance Detection to circuit in the presumptive area on the chip by being arranged on hardware performance detector on the chip, and finish adjustment to the supply power voltage of chip according to testing result, thereby realized the self adaptation adjustment of chip power supply voltage.

The invention described above embodiment sequence number does not represent the quality of embodiment just to description.

The all or part of step that one of ordinary skill in the art will appreciate that realization above-described embodiment can be finished by hardware, also can instruct relevant hardware to finish by program, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium of mentioning can be read-only memory, disk or CD etc.

The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. a numerically-controlled oscillator is characterized in that, described numerically-controlled oscillator comprises NAND gate, first time delay chain, second time delay chain and not gate,

Described first time delay chain is formed by at least two first delay unit cascades, and described first time delay chain receives the first group selection signal, determines effective first delay unit in described first time delay chain according to the described first group selection signal;

Described second time delay chain is formed by at least two second delay unit cascades, and described second time delay chain receives the second group selection signal, determines effective second delay unit in described second time delay chain according to the described second group selection signal;

2. numerically-controlled oscillator according to claim 1 is characterized in that, described first delay unit in described first time delay chain comprises first NOR gate and first selector,

The signal that the first input end of described NOR gate receives is first group of threshold signal, second input of the NOR gate in first first delay unit is connected with the output of described NAND gate, the output of the NOR gate in second input of the NOR gate in i first delay unit and individual first delay unit of i-1 is connected, the first input end of the first selector in individual first delay unit of j is connected with the output of the NOR gate of j first delay unit, second input of the first selector of j first delay unit is connected with the output of the first selector of j+1 first delay unit, and the output of the first selector of first first delay unit is connected with first first delay unit in described second time delay chain;

Described second delay unit in described second time delay chain comprises NOR gate and second selector,

The signal that the first input end of described NOR gate receives is second group of threshold signal, second input of the NOR gate in first second delay unit is connected with first first delay cell in described first time delay chain, the output of the NOR gate in second input of the NOR gate in i second delay unit and individual second delay unit of i-1 is connected, the first input end of the second selector in individual second delay unit of j is connected with the output of the NOR gate of j second delay unit, second input of the second selector of j second delay unit is connected with the output of the second selector of j+1 second delay unit, and the output of the second selector of first second delay unit is connected with second input of described NAND gate;

3. numerically-controlled oscillator according to claim 2 is characterized in that, described first time delay chain receives the first group selection signal, determines effective first delay unit in described first time delay chain according to the described first group selection signal, comprising:

If first selector receives first in the described first group selection signal and selects signal, first delay unit of assert described first selector correspondence is effective, do not receive the selection of first in described first group selection signal signal if first selector connects, assert that first delay unit of described first selector correspondence is invalid;

If second selector receives second in the described second group selection signal and selects signal, second delay unit of assert described second selector correspondence is effective, if second selector does not receive second in the described second group selection signal and selects signal, assert that second delay unit of described second selector correspondence is invalid;

Wherein, the first selection signal is that 0 or 1, the second selection signal is 0 or 1.

4. hardware performance detector according to claim 3, it is characterized in that, when described first selector receive described first when selecting signal to be 0, with one in the first input end of described first selector and second input as effective input, when described first selector receive described first when selecting signal to be 1, with the first input end of described first selector and in second input another as effective input;

When described second selector receive described second when selecting signal to be 0, with one in the first input end of described second selector and second input as effective input, when described second selector receive described second when selecting signal to be 1, select second to select the first input end of device and in second input another as effective input with described.

5. numerically-controlled oscillator according to claim 3, it is characterized in that, be set to 1 with being identified as the described first threshold signal that the first invalid delay unit receives in first time delay chain in the described numerically-controlled oscillator, be set to 1 with being identified as described second threshold signal that the second invalid delay unit receives in second time delay chain in the described numerically-controlled oscillator.

6. a hardware performance detector is characterized in that, comprising: numerically-controlled oscillator, first frequency divider, second frequency divider, first counter, second counter and control unit,

Described second frequency divider carries out frequency division to obtain second frequency-dividing clock to described running clock, and described second counter counts to obtain second count value to described second frequency-dividing clock in the described preset count cycle;

Described control unit asks poor to described first count value and described second count value, and will ask the difference that obtains after the difference to export as detected value to described first count value and described second count value, in order to carry out the voltage adjustment according to described detected value.

7. hardware performance detector according to claim 6 is characterized in that, described control unit sends concrete be used for the sending first group selection signal and the second group selection signal;

Described first time delay chain is formed by at least two first delay unit cascades, described first time delay chain receives the first group selection signal that described control unit sends, and determines effective first delay unit in described first time delay chain according to the described first group selection signal;

Described second time delay chain is formed by at least two second delay unit cascades, described second time delay chain receives the second group selection signal that described control unit sends, and determines effective second delay unit in described second time delay chain according to the described second group selection signal;

The signal of the first input end input of described NAND gate is first enable signal, the output of described NAND gate is connected with the input of described not gate and first first delay unit of described first time delay chain respectively, first second delay unit in described second time delay chain is connected with first first delay unit of described first time delay chain and second input of described NAND gate respectively, the signal of the output output of described not gate is described running clock

Wherein, the described first group selection signal comprises at least one first selection signal, and the described second group selection signal comprises at least one second selection signal.

8. hardware performance detector according to claim 7 is characterized in that, described control unit specifically is used for sending first group of threshold signal and second group of threshold signal;

Described first delay unit comprises: first NOR gate and first selector,

The signal of the first input end input of described NOR gate is first group of threshold signal that described control unit sends, second input of first NOR gate in first first delay unit is connected with the output of described NAND gate, the output of first NOR gate in second input of first NOR gate in i first delay unit and individual first delay unit of i-1 is connected, the first input end of the first selector in individual first delay unit of j is connected with the output of first NOR gate of j first delay unit, second input of the first selector of j first delay unit is connected with the output of the first selector of j+1 first delay unit, and the output of the first selector of first first delay unit is connected with first second delay unit in described second time delay chain;

Described second delay unit comprises: second NOR gate and second selector,

9. hardware performance detector according to claim 8, it is characterized in that, described first frequency divider carries out the M frequency division to described reference clock, described second frequency divider carries out Fractional-N frequency to the running clock of described numerically-controlled oscillator output, described control unit comprises mode selection module and control module

Described control module, be used for receiving ratio signal, described calibrating signal according to the described ratio signal that receives and the selection of described mode selection module generates the described first group selection signal and the described second group selection signal, and the described first group selection signal and the described second group selection signal exported to described numerically-controlled oscillator, so that described numerically-controlled oscillator is determined in described first time delay chain effective second delay unit in effective first delay unit and described second time delay chain respectively according to the described first group selection signal that receives and the described second group selection signal, so that T _DCO﹒ N=T _Core﹒ M is at T _DCO﹒ N=T _CoreDuring ﹒ M, the described ratio signal of current correspondence is regarded as parameter signal, wherein, T _DCOBe the cycle of the running clock of described numerically-controlled oscillator output, T _CoreBe the cycle of described reference clock;

Wherein, described M and N are the natural number greater than 0.

10. according to Claim 8 or 9 described hardware performance detectors, it is characterized in that described first time delay chain receives the first group selection signal, determine effective first delay unit in described first time delay chain according to the described first group selection signal, comprising:

If first selector receives first in the described first group selection signal and selects signal, first delay unit of assert described first selector correspondence is effective, if first selector does not receive first in the described first group selection signal and selects signal, assert that first delay unit of described first selector correspondence is invalid;

11. hardware performance detector according to claim 10, it is characterized in that, when described first selector receive described first when selecting signal to be 0, with one in the first input end of described first selector and second input as effective input, when described first selector receive described first when selecting signal to be 1, with the first input end of described first selector and in second input another as effective input;

12. hardware performance detector according to claim 10, it is characterized in that, the first threshold signal that is identified as in first time delay chain in the described numerically-controlled oscillator in described first group of threshold signal that the first invalid delay unit receives is set to 1, second threshold signal that is identified as in second time delay chain in the described numerically-controlled oscillator in described second group of threshold signal that the second invalid delay unit receives is set to 1.

13. a voltage adjustment system is characterized in that, comprising: configuration nucleus module, voltage regulation controller, Power Management Unit and at least one be as arbitrary described hardware performance detector in the claim 6 to 12,

Described configuration nucleus module carries out the predetermined parameters configuration and starts described voltage adjustment system described voltage adjustment system by bus;

Described hardware performance detector is connected with described voltage regulation controller, and the performance of described hardware performance detector by detecting circuit in the presumptive area to be obtaining detected value, and described detected value is fed back to described voltage regulation controller;

14. system according to claim 13, it is characterized in that, the detected value of described hardware performance detector output is that described first count value deducts the difference that described second count value obtains, and described voltage regulation controller determines whether that according to described detected value needs carry out the voltage adjustment, comprising:

Or,

The detected value of described hardware performance detector output is that described second count value deducts the difference that described first count value obtains, and described voltage regulation controller determines whether that according to described detected value needs carry out the voltage adjustment, comprising:

15. a hardware performance detection method is characterized in that, described method comprises:

Receive operation signal, predefined parameter signal and reference clock;

Wherein, M and N are the natural number greater than 0.

16. method according to claim 15 is characterized in that, describedly regulates described numerically-controlled oscillator so that described numerically-controlled oscillator output running clock comprises according to described parameter signal:

17. method according to claim 16 is characterized in that, before described reception operation signal, predefined parameter signal and the reference clock, described method also comprises:

Receive calibrating signal, ratio signal and reference clock;