CN104973566A - 具精确间隙的微机电晶圆结构与其制作方法 - Google Patents

具精确间隙的微机电晶圆结构与其制作方法 Download PDF

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CN104973566A
CN104973566A CN201510151343.2A CN201510151343A CN104973566A CN 104973566 A CN104973566 A CN 104973566A CN 201510151343 A CN201510151343 A CN 201510151343A CN 104973566 A CN104973566 A CN 104973566A
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wafer
doped region
electro
micro
oxide layer
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殷宏林
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Asia Pacific Microsystems Inc
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Asia Pacific Microsystems Inc
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Abstract

本发明提供一种具精确间隙的微机电晶圆结构及其制作方法，该制作方法包括以下步骤。首先，提供一第一晶圆，第一晶圆具有一第一表面。接着，于该第一表面的形成至少两个以上具有不同掺杂浓度或不同掺杂物的掺杂区，以使每一该掺杂区具有不同的氧化速率。再来，对第一晶圆进行热氧化，以使不同的掺杂区上形成不同厚度的氧化层。之后，提供一第二晶圆。然后，将第二晶圆与第一晶圆相结合。本发明的有益效果是可以制造出成本较低、电容间极板具精确间隙的微机电晶圆结构。

Description

具精确间隙的微机电晶圆结构与其制作方法
技术领域
本发明是关于一种具精确间隙的微机电晶圆结构与其制作方法，且特别是关于一种利用氧化层厚度来精确控制间隙的微机电晶圆结构的制作方法。
背景技术
精确的超声波传感或压力监控在现今许多技术中扮演相当重要的角色，例如：医学上的超音波扫描探头或是汽车上的轮胎压力传感器。因此许多技术都需要高精度传感的传感器。
现今电容式传感器的灵敏度取决于如何精确的控制薄膜(membrane)厚度及上下极板间的间隙(gap)，而在常见的电容式传感器的制造方法上仍有缺陷，以下列举部分前案进行说明：
在美国专利第5013396号中，是利用氢氧化钾(KOH)等碱基溶液预先于硅晶圆上蚀刻定义出间隙深度，采用局部掺杂及电化学蚀刻并搭配玻璃接合的方式来制作薄膜，此方法可精确控制硅薄膜厚度，成本较SOI(Silicon On Insulator)低，但是无法得到均一且精确的间隙控制。
在美国专利第5445991号中，是采用阳极处理使硅晶圆表面局部形成多孔硅(porous Si)区域，利用磊晶方式于硅晶圆表面形成硅薄膜层后，借由硅薄膜层上的蚀刻穿孔利用氢氟酸(HF)来蚀刻该多孔硅区域以制作出硅薄膜层与硅晶圆间的间隙，此方法可精确控制间隙，磊晶硅层成本也较SOI低，但是电容极板间绝缘不佳，且需要额外的密封层来封闭硅薄膜层上的蚀刻穿孔。
在美国专利第5706565号中，亦是利用蚀刻方式来定义间隙大小，并利用接合另一晶圆的方式来制作硅薄膜，此制造方法较为简单，但无法精确的控制间隙。
在美国专利第6958255号中，是利用蚀刻及多次热氧化步骤及晶圆接合方式来制作出电容极板间的间隙，此方法虽可精确控制间隙，电容极板间也具有绝缘，但是制造过程步骤较多，需要许多时间制造。
在美国专利第7745248号中，是利用沉积并定义氧化阻挡层(OXblock layer)及热氧化步骤来得到不同氧化层厚度，并利用晶圆接合方式制作薄膜，此方法可以精确控制间隙，电容极板间也具有绝缘，但是制造过程步骤较多，需要许多时间制造，且不易制作出含多个大小不同的间隙。
综合上述可知，目前公知传感器的制造方法仍存在缺陷，因此如何设计出制造方法简单、成本较低、电容极板间可绝缘且可以精确控制间隙的电容式传感器，便是值的本领域技术人员去思量改进之处。
发明内容
为了解决上述的问题，本发明的目的在提供一种具精确间隙的微机电晶圆结构的制作方法，其较佳的是利用掺杂浓度不同来产生不同厚度的氧化层，可以精确的控制间隙。因此可以制造出成本较低、电容间极板间可绝缘的微机电晶圆结构。而此方法可应用于制造电容传感器或微流体通道等。
基于上述目的与其他目的，本发明提供一种供一种微机电晶圆结构的制作方法，其包括以下步骤：
(a)提供一第一晶圆，第一晶圆具有一第一表面，第一晶圆已均匀掺杂一定掺杂浓度的掺杂物。
(b)对该第一表面的局部区域进行掺杂，使该第一表面形成至少两个以上具不同掺杂浓度或不同掺杂物的掺杂区，以使每一该掺杂区具有不同的氧化速率。
(c)对第一晶圆进行热氧化，以使不同的掺杂区上形成不同厚度的氧化层。
(d)提供一第二晶圆。
(e)将第二晶圆与第一晶圆相结合。
其中，第二晶圆是承靠在厚度最大的氧化层上，使第一晶圆与第二晶圆间存在有至少一间隙。
在上述的微机电晶圆结构的制作方法中，于(b)步骤中，这些掺杂区包括多个第一掺杂区与多个第二掺杂区，且各该第二掺杂区围绕该各第一掺杂区。其中，第一掺杂区的氧化速率小于在第二掺杂区的氧化速率。
在上述的微机电晶圆结构的制作方法中，于(b)步骤中，这些掺杂区包括多个第一掺杂区、多个第二掺杂区、与多个第三掺杂区，各该第三掺杂区围绕各该第二掺杂区，且各该第二掺杂区围绕各该第一掺杂区。其中，第一掺杂区的氧化速率小于第二掺杂区的氧化速率，且第二掺杂区的氧化速率小于第三掺杂区的氧化速率。
在上述的微机电晶圆结构的制作方法中，于(b)步骤中，这些掺杂区包括多个第一掺杂区、多个第二掺杂区、与多个第三掺杂区，各该第三掺杂区围各该第一掺杂区，且有一个以上的第二掺杂区是分布在第一掺杂区中。其中，第一掺杂区的氧化速率小于第二掺杂区的氧化速率，且第二掺杂区的氧化速率小于第三掺杂区的氧化速率。
在上述的微机电晶圆结构的制作方法中，第二晶圆具有一第二表面，且于该第二表面形成氧化层，于(e)步骤中，第二晶圆是通过第二表面上的氧化层与第一晶圆上的氧化层结合。而且，于第二晶圆的第二表面形成至少两个以上具不同掺杂浓度或不同掺杂物的掺杂区；且对第二晶圆进行热氧化，以使不同的掺杂区上形成不同厚度的氧化层。
在上述的微机电晶圆结构的制作方法中，第二晶圆包括：一硅组件层、一绝缘层、与一硅底材；于(e)步骤后还包括以下步骤：移除该硅底材及移除该绝缘层。
在上述的微机电晶圆结构的制作方法中，于(e)步骤后，还包括以下步骤：
(f)开设多个窗口，各该窗口贯穿该第二晶圆与该氧化层，而使该第一晶圆的部分表面裸露。
(g)设置多个第一金属接点通过该窗口与该第一晶圆的部分表面电性相连，并设置多个第二金属接点于该第二晶圆上。
在上述的微机电晶圆结构的制作方法中，第一晶圆包括：一硅组件层、一绝缘层、与一硅底材，且掺杂区是位于硅组件层。
在上述的微机电晶圆结构的制作方法中，还包括以下步骤：移除硅底材及移除绝缘层。。
在上述的微机电晶圆结构的制作方法中，其中于步骤(e)后，还包括以下步骤：
(f)于该第一晶圆上开设多个窗口，各该窗口贯穿该硅组件层及该氧化层，而使第二晶圆的部分表面裸露。
(g)设置多个第一金属接点通过该窗口与该第二晶圆的表面电性相连，并设置多个第二金属接点于该硅组件层上。
在上述的微机电晶圆结构的制作方法中，其中于(b)步骤中，第一表面形成至少两个以上具不同掺杂浓度且具有至少两个不同掺杂物。
相较于公知的微机电晶圆结构的制作方法，本发明的微机电晶圆结构的制作方法是一种简化的制程，能够精确的控制间隙的大小，基板之间的绝缘性较佳，且制造步骤较少也较容易，成本也较低。
为让本发明的上述目的、特征和优点更能明显易懂，下文将以实施例并配合所附图式，作详细说明如下。需注意的是，所附图式中的各组件仅是示意，并未按照各组件的实际比例进行绘示。
附图说明
图1A～图1F所示为本发明的一种具精确间隙的微机电晶圆结构的制造方法的第一实施例。
图2所示为微机电组件。
图3所示为第二实施例。
图4所示为第三实施例。
图5所示为第四实施例。
图6所示为不同掺杂物在不同状态下氧化速率的曲线图。
图7A～图7F所示为第五实施例。
实施方式
请参照图1A～图1F，图1A～图1F所示为本发明的一种微机电晶圆结构30的制造方法的实施例。首先，请参照图1A，提供一第一晶圆10，第一晶圆10上具有一第一表面11。在本实施例中，第一晶圆10整体上已预先掺杂了N型掺杂物，这些N型掺杂物例如为磷、砷或锑，这样第一晶圆10就会成为N型晶圆。接着，请参照图1B，于第一表面11利用涂布光阻12及曝光显影等黄光微影技术画分出多个第一掺杂区111(为表示更清楚，在图1A至图1F中只绘示一个掺杂区111，但是本领域具通常知识者应可知，由于会有多个微机电组件30’(如图2所示)的制造同时在进行，故在第一晶圆10的第一表面11上实际上是画分有多个第一掺杂区111)与多个第二掺杂区112，接着对未被光阻12遮蔽的第一表面11进行掺杂，在此例如是使用离子植入法(Implantation)对第一表面11进行掺杂。经过上述掺杂程序后，未被光阻12所遮蔽的第二掺杂区112会拥有较高的掺杂浓度，因此于之后进行热氧化反应时第二掺杂区112的氧化速率大于第一掺杂区111的氧化速率。
再来，请参照图1C，接着对第一晶圆10进行热氧化反应形成氧化层13，该氧化层13包含位于第一掺杂区111上所形成一第一氧化层131，及于第二掺杂区112上形成一第二氧化区132，由于第二掺杂区112的氧化速率大于第一掺杂区111的氧化速率，故于第二掺杂区112上所形成的第二氧化层132会较第一掺杂区111上所形成的第一氧化层131来得厚。
然后，请参照图1D，将一第二晶圆20与第一晶圆10相结合，在本实施例中第二晶圆20包含一硅组件层23、一绝缘层22以及一硅底材21。由于第一氧化层131与第二氧化层132的厚度具有差异，且第二晶圆20是通过该硅组件层23承靠在厚度最大的第二氧化层132上，因此第一晶圆10与第二晶圆20间会存在有一间隙14。在本实施例中，例如是使用硅对氧化硅的熔融键合(fusion bonding)或等离子体活化键合(plasmaactivated bonding)，来结合第一晶圆10与第二晶圆20。
之后，请参照图1E，将第二晶圆20移除一定厚度，例如利用研磨或蚀刻来将硅底材21与绝缘层22移除。在此，蚀刻分别是使用氢氧化钾溶液及氢氟酸溶液来将硅底材21与绝缘层22移除。
再来，请参阅图1F，在第二晶圆20上开设至少一窗口16(在本实施例中为多个)，窗口16贯穿第二晶圆20与氧化层13，使第二掺杂区112部分表面裸露。接着，形成多个第一金属接点151(如同第一掺杂区111，为表示更清楚，在图1F中只绘示一个第一金属接点151，但是本领域具通常知识者应可知，由于会有多个微机电组件30’(如图2所示)的制造同时在进行，故在第二晶圆20上实际上会形成有多个第一金属接点151)通过窗口16与第二掺杂区112的部分表面电性相连，而第二金属接点152则设置在第二晶圆20上，在本实施例中第二晶圆20可为一具低电阻的导电硅晶圆，因此该第二金属接点152可与第二晶圆20电性相连。在本实施例中，由于第二掺杂区112具有较高的掺杂浓度，故将第一金属接点151设置在第二掺杂区112可以有效降低接触电阻，进而提升导电性。在完成图1F所示的程序后，便形成一微机电晶圆结构30。
之后，对此微机电晶圆结构30进行切割，以形成多个微机电组件30’(如图2所示)。在本实施例中，此微机电组件30’为电容式传感器，当第一金属接点151与第二金属接点152通电后，第一电极10’(即切割后的第一晶圆10)与第二电极20’(即切割后的第二晶圆20)间便会存在一电容。当电容式传感器受到外在物理因素(例如压力变化)的影响时，第一电极10’与第二电极20’间的空隙14的距离就会产生变化，而此距离的改变也会使第一电极10’与第二电极20’间的电容值产生变化，通过量测电容值变化就能换算出外在物理因素的变化(例如压力变化)；反之，亦可于第一电极10’与第二电极20’间施加一电压，由于电位差所造成的静电力将使第二电极20’产生形变而改变间隙14的大小，借由输入不同电压及频率的信号即可驱动该电容式传感器30’。
综上所述，本发明的微机电晶圆结构30的制作方法，是一种简化的制程，先对第一晶圆10的第一表面11进行不同浓度的掺杂，使第一晶圆10产生不同掺杂浓度的掺杂区(即：第一掺杂区111与第二掺杂区112)，再利用各掺杂区热氧化速率的不同，进行热氧化时就可以同时产生不同厚度的氧化层(即：第一氧化层131及第二氧化层132)，借由不同厚度的氧化层来控制间隙的大小。在某些公知技术中(例如：美国专利第5013396号与第5706565号)，是采用蚀刻法来控制微机电晶圆结构中间隙的大小，但蚀刻法在控制上较为困难，因此无法均匀且精确控制整片晶圆上各间隙的大小，而上述实施例是采用热氧化反应的方法，故较能够精确的控制整片晶圆上各间隙大小。另外，在某些公知技术中(例如：美国专利第6958255号、第7745248号)，其采用的制程虽可以较精确控制间隙，但制造过程步骤较多，需要许多时间制造，而上述实施例仅需进行一次热氧化反应，故制造过程步骤较少，可减少时间成本。另外，在本实施例中，第一电极10’与第二电极20’间由第一氧化层131隔开，第一电极本10’与第二电极20’间就拥有良好的绝缘性，即使两电极因传感信号过大等因素而碰触亦不致于发生短路烧毁等现象。故本发明的微机电晶圆结构的制作方法有下列优点：
可精确控制第一电极10’与第二电极20’间的间隙14大小。
可精确控制经过研磨或蚀刻后的第二晶圆20厚度。
第一电极10’与第二电极20’间的绝缘性佳。
制程步骤较少也较容易。
然而，上述的微机电晶圆结构的制作方法并不限于制作电容式传感器，也可用于制作微流体通道。相较于电容式传感器，在制作微流体通道时，可仅执行图1A至图1E所示的步骤后便对微机电晶圆结构进行切割以形成微流体组件，而不一定需要执行图1F所示的步骤。此外，在上述的实施例中，第一晶圆10是预先掺杂了N型掺杂物，但其实并不局限于N型掺杂物，也可以使用P型掺杂物(例如为硼)进行掺杂，这样第一晶圆就会成为P型晶圆。另外，在上述的实施例中，第二晶圆20是使用具有SOI结构(Silicon On Insulator layer)的晶圆，如此便可较精确地控制研磨或蚀刻后第二晶圆20厚度。但其实并不局限于具有SOI结构的晶圆，也可依状况而使用与第一晶圆10相同均质的晶圆做为第二晶圆20。
请参阅图3，图3所示为第二实施例。本实施例所示的微机电晶圆结构40的制造程序与图1A～图1E所示的制造程序相似，差别在于是将第一晶圆10的第一表面11再画分出多个第三掺杂区113，各第三掺杂区113是环绕在各第二掺杂区112与各第一掺杂区111周围。之后，在进行掺杂程序时第二掺杂区112与第三掺杂区113会被分别以不同浓度的掺杂物进行掺杂，因此这三个掺杂区会因为掺杂浓度不同而有不同的氧化速率。在掺杂程序中可先对第二掺杂区112进行掺杂，再对第三掺杂区113进行掺杂；或着先对第三掺杂区113进行掺杂，再对第二掺杂区112进行掺杂；又或者先对第二掺杂区112及第三掺杂区113同时进行第一次掺杂，再单独对第三掺杂区113进行第二次掺杂。在本实施例中，第三掺杂区113的掺杂浓度大于第二掺杂区112的掺杂浓度，而第二掺杂区112的掺杂浓度大于第一掺杂区111的掺杂浓度。因此，第三掺杂区113的氧化速率大于第二掺杂区112的氧化速率，而第二掺杂区112的氧化速率大于第一掺杂区111的氧化速率。
也因此，在进行热氧化反应后，第一掺杂区111、第二掺杂区112及第三掺杂区113分别产生第一氧化层131、第二氧化层132及第三氧化层133，且第三氧化层133的厚度大于第二氧化层132的厚度，第二氧化层132的厚度则大于第一氧化层131的厚度。如此一来，当第二晶圆20与第一晶圆10结合之后，第一晶圆10与第二晶圆20之间会形成一具阶梯状的空隙14’。用此方法所制成的电容传感器，传感外在物理因素可得到更佳的线性度及灵敏度等优点。
请参阅图4，图4所示为第三实施例。本实施例所示的微电机晶圆结构40’的制造程序与图1A～图1E所示的制造程序相似，差别在于是将第一晶圆10的第一表面11画分为多个第一掺杂区111、多个第二掺杂区114、以及多个第三掺杂区115。一个以上的第二掺杂区114分布在各第一掺杂区111之中，且第二掺杂区114未与第三掺杂区115相连。之后，在掺杂程序时，第三掺杂区115会被进一步地掺杂更高浓度的掺杂物，而第二掺杂区114在本实施例则进一步地使用P型掺杂物进行掺杂，因此这三个掺杂区会因为掺杂浓度及掺杂物不同而有不同的氧化速率。在本实施例中，第三掺杂区115的氧化速率大于第二掺杂区114的氧化速率，而第二掺杂区114的氧化速率大于第一掺杂区111的氧化速率。
也因此，在进行热氧化反应后，第一掺杂区111及第三掺杂区115分别产生第一氧化层131及第三氧化层135，而第二掺杂区114则产生一第二氧化层134，且第三氧化层135的厚度大于第二氧化层134的厚度，第二氧化层134的厚度则大于第一氧化层131的厚度。由于第二氧化层134的厚度大于第一氧化层131的厚度，因此第二氧化层134会呈现凸起状。用此方法所制成的电容传感器，在传感外在物理因素时会因为呈凸起状的第二氧化层134，从而避免第一电极10’与第二电极20’发生沾黏(stiction)的情形。在本实施例中，第二掺杂区114是使用P型掺杂物进行掺杂，但并不局限于P型掺杂物，也可以使用N型掺杂物。
请参阅图5，图5所示为第四实施例的微机电晶圆结构40”。本实施例与图3所示的第二实施例相似。在本实施例中，是在第二晶圆20上的第二表面再画分出多个第四掺杂区214及多个第五掺杂区215，而第五掺杂区215的掺杂浓度高于第四掺杂区214的掺杂浓度。在进行热氧化反应之后，第五掺杂区215所产生的第五氧化层235厚度会大于第四掺杂区214所产生的第四氧化层234的厚度。然后，再将第二晶圆20与第一晶圆10对准接合，使第一晶圆10最厚的氧化层与第二晶圆20最厚的氧化层接合。通过此方法完成的微机电晶元结构40”，具有较大而且能够精确控制的间隙24。由于利用氧化层厚度差异所完成的间隙通常是1um以下的大小，因此借由第一晶圆与第二晶圆两边的氧化层接合，就能够得到较大而且较为精确的间隙，而间隙在设计上就可以有更多组合变化(例如：上下层流道交错或连通的布局方式)。
请参阅图6，图6所示为不同掺杂物在不同状态下氧化速率的曲线图。图6中绘示了4条曲线，分别代表硼(Boron)、磷(Phosphorus)、砷(Arsenic)以及锑(Antimony)，其中硼为P型掺杂物，磷、砷及锑则为N型掺杂物。由图中可得知，于相同掺杂浓度下掺杂砷的硅氧化速率略大于掺杂磷的氧化速率，掺杂磷的硅氧化速率大于掺杂锑的氧化速率，而掺杂锑的硅氧化速率大于掺杂硼的氧化速率。因此，在上述实施例中(即：第一实施例至第四实施例)，除了通过掺杂浓度来控制不同掺杂区的氧化速率，也可以用掺杂不同元素的方式让不同掺杂区具有不同的氧化速率。例如，在第二实施例中，可以在第一掺杂区111用锑进行掺杂，在第二参杂区112用磷进行掺杂，在第三掺杂区113则用砷进行掺杂。如此一来各个掺杂区也都具有不同的氧化速率，进行热氧化反应时也能够产生出不同厚度的氧化层，同样可以制造出具有阶梯状的空隙14’。
在上述的实施例中，第一晶圆10为均质的晶圆，然而也可将第一晶圆10改为具有SOI结构的晶圆。请参阅图7A至图7F，图7A至图7F所示为第五实施例。首先，请参照图7A，提供一第一晶圆50，第一晶圆50上具有一第一表面51。第一晶圆50还包含一硅组件层503、一绝缘层502以及一硅底材501，该第一表面51位于该硅组件层503上。接着，请参照图7B，于第一表面51利用黄光微影及涂布光阻52方式画分多个第一掺杂区511及多个第二掺杂区512，接着对第一表面51进行掺杂。经过上述掺杂程序后，未被光阻52所遮蔽的第二掺杂区512会拥有较高的掺杂浓度，因此于后进行热氧化反应时第二掺杂区512的氧化速率大于第一掺杂区511的氧化速率。
再来，请参照图7C，接着对第一晶圆50进行热氧化反应，于第一掺杂区511会形成一第一氧化层531，于第二掺杂区512上则会形成一第二氧化区532，由于第二掺杂区512的氧化速率大于第一掺杂区511的氧化速率，故于第二掺杂区512上所形成的第二氧化层532会较第一掺杂区511上所形成的第一氧化层531来得厚。
然后，请参照图7D，将第二晶圆60与第一晶圆50结合。由于第一氧化层531与第二氧化层532的厚度具有差异，且第二晶圆60是承靠在厚度最大的第二氧化层532上，因此第一晶圆50与第二晶圆60间会存在有一间隙54。
之后，请参照图7E，将第一晶圆50移除一定厚度，也就是将硅底材501与绝缘层502移除。再来，请参阅图7F，在第一晶圆50上开设至少一窗口56(在本实施例中为多个)，窗口56贯穿第一晶圆50与第二氧化层532，使第二晶圆60的表面裸露。接着，形成多个第一金属接点551通过窗口56与第二晶圆60表面电性相连，该第二晶圆60为一低阻值硅晶圆，而第二金属接点552则设置在第一晶圆50上，便形成一微机电晶圆结构70。
上述实施例仅是为了方便说明而举例，虽遭所属技术领域的技术人员任意进行修改，均不会脱离如权利要求书中所欲保护的范围。

Claims (12)

1.一种微机电晶圆结构的制作方法，其特征在于，包括下列步骤：
(a)提供一第一晶圆，该第一晶圆具有一第一表面；
(b)使该第一表面形成至少两个以上具不同掺杂浓度或不同掺杂物的掺杂区；
(c)对该第一晶圆进行热氧化，以使不同的掺杂区上形成不同厚度的氧化层；
(d)提供一第二晶圆；及
(e)将该第二晶圆与该第一晶圆上的该氧化层相结合形成该微机电晶圆结构；
其中，该微机电晶圆结构至少具有一间隙。
2.如权利要求1所述的微机电晶圆结构的制作方法，其特征在于，于(b)步骤中，这些掺杂区包括多个第一掺杂区与多个第二掺杂区，且各该第二掺杂区围绕各该第一掺杂区，该第一掺杂区的氧化速率小于在该第二掺杂区的氧化速率。
3.如权利要求1所述的微机电晶圆结构的制作方法，其特征在于，于(b)步骤中，这些掺杂区包括多个第一掺杂区、多个第二掺杂区、与多个第三掺杂区，各该第三掺杂区围绕一该第二掺杂区，且该第二掺杂区围绕一该第一掺杂区，该第一掺杂区的氧化速率小于该第二掺杂区的氧化速率，且该第二掺杂区的氧化速率小于该第三掺杂区的氧化速率。
4.如权利要求1所述的微机电晶圆结构的制作方法，其特征在于，于(b)步骤中，这些掺杂区包括多个第一掺杂区、多个第二掺杂区、与多个第三掺杂区，各该第三掺杂区围绕各该第一掺杂区，且一个以上的第二掺杂区是分布在各该第一掺杂区中，该第一掺杂区的氧化速率小于该第二掺杂区的氧化速率，且该第二掺杂区的氧化速率小于该第三掺杂区的氧化速率。
5.如权利要求1所述的微机电晶圆结构的制作方法，其特征在于，该第二晶圆具有一第二表面，且于该第二表面形成氧化层，于(e)步骤中，该第二晶圆是通过该第二表面上的氧化层与该第一晶圆上的该氧化层结合。
6.如权利要求5所述的微机电晶圆结构的制作方法，其特征在于，于该第二晶圆的该第二表面形成至少两个以上具不同掺杂浓度或不同掺杂物的掺杂区；且对该第二晶圆进行热氧化，以使不同的掺杂区上形成不同厚度的氧化层。
7.如权利要求1所述的微机电晶圆结构的制作方法，其特征在于，该第二晶圆包括：一硅组件层、一绝缘层、与一硅底材，且于(e)步骤后还包括以下步骤：
移除该硅底材及移除该绝缘层。
8.如权利要求1所述的微机电晶圆结构的制作方法，其特征在于，于(e)步骤后，还包括以下步骤：
(f)开设多个窗口，该窗口贯穿该第二晶圆与该氧化层，而使该第一晶圆的部分第一表面裸露；及
(g)设置多个第一金属接点通过各该窗口与该第一晶圆的部分第一表面电性相连，并设置多个第二金属接点于该第二晶圆上。
9.如权利要求1所述的微机电晶圆结构的制作方法，其特征在于，该第一晶圆包括：一硅组件层、一绝缘层、与一硅底材，且该掺杂区是位于该硅组件层。
10.如权利要求9所述的微机电晶圆结构的制作方法，其特征在于，于(e)步骤后还包括以下步骤：
移除该硅底材及移除该绝缘层。
11.如权利要求1所述的微机电晶圆结构的制作方法，其特征在于，于步骤(e)后，还包括以下步骤：
(f)于该第一晶圆上开设多个窗口，各该窗口贯穿该该氧化层及该第一晶圆，而使该第二晶圆的部分表面裸露；及
(g)设置多个第一金属接点通过该窗口与该第二晶圆的表面电性相连，并设置多个第二金属接点于该第一晶圆上。
12.如权利要求1所述的微机电晶圆结构的制作方法，其特征在于，于(b)步骤中，该第一表面形成至少两个以上具不同掺杂浓度且具有至少两个不同掺杂物。
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Application publication date: 20151014